CN106932794B - A kind of hardware accelerator and method of satellite navigation baseband signal track algorithm - Google Patents
A kind of hardware accelerator and method of satellite navigation baseband signal track algorithm Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/24—Acquisition or tracking or demodulation of signals transmitted by the system
- G01S19/29—Acquisition or tracking or demodulation of signals transmitted by the system carrier including Doppler, related
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7817—Specially adapted for signal processing, e.g. Harvard architectures
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Abstract
The present invention relates to the hardware accelerators and method of a kind of satellite navigation baseband signal track algorithm, including data transmission module, data cache module, access control module, operation accumulator module and statistical module, operation accumulator module includes multiple operation summing elements.The step of hardware-accelerated method is as follows: the NCS data of DFT data and last time operation are written in hardware accelerator before operation；Start DFT operation after the completion of data write-in；Hardware accelerator generates twiddle factor, parallel to carry out DFT operation, then by obtaining updated NCS data to the cumulative of DFT operation result；Statistical result is obtained according to DFT operation result and updated NCS data, and updated NCS data are transferred in base band SoC system；Hardware accelerator stops operation and counts and generate hardware interrupts, and base band SoC system carries out subsequent algorithm processing after responding hardware interrupts.This programme can be improved GNSS signal carrier track frequency domain frequency discrimination calculating speed, to improve system processing capacity.
Description
Technical field
The present invention relates to satellite navigation receiver digital signal processing chip technical fields, more particularly to lead applied to satellite
The receiver frequency domain carriers that navigate carry out the hardware accelerator and method of frequency domain frequency discrimination.
Background technique
Global Navigation Satellite System (Global Navigation Satellite System, GNSS) receiver it is main
Task is capture and tracking satellite signal, after signal transforms to baseband signal from radiofrequency signal, is completed by base band signal process
Navigator fix resolves.
The capture of GNSS signal searches for from reception signal, captures each visible GPS satellite signal, and is therefrom defended
The carrier frequency and C/A code phase rough estimate value of star signal.In the tracking phase of GNSS signal, what is obtained from acquisition phase is defended
Star signal(-) carrier frequency and code phase rough estimate value are set out, and multiple correlators are arranged centered on the code phase of initial estimation,
And set carrier frequency to the carrier frequency of initial estimation, gradually finely two signal parameters are estimated by track loop
Meter, while exporting to the various measured values of signal, then demodulate the navigation message bit in signal in passing.Track loop is generally by phase
Close device, discriminator, loop filter composition.Wherein correlator is often through hardware realization, by the integral accumulation of integer number of milliseconds
It exports and gives loop discriminator, and loop discriminator and loop filter are often by software realization.Track loop is functionally divided into
Code tracking and carrier track are respectively completed the accurate lock of ranging code phase and carrier frequency.
Frequency deviation need to be estimated using frequency discriminator by carrying out carrier track, and general there are two types of methods: utilizing arc tangent
The phase difference that function asks the correlator of adjacent time to export integrated value obtains frequency divided by time interval, and another method is to utilize
Fast Fourier Transform (FFT) (Fast Fourier Transform, FFT) or discrete Fourier transform (Discrete Fourier
Transform, DFT) frequency spectrum then frequency discrimination is converted to the integrated value progress frequency domain of correlator continuous time point output, it is latter
Kind method has been widely used because bigger frequency identifies range.
It needs to find frequency spectrum maximum value within the scope of defined frequency and correlator when carrying out frequency domain identification, then in maximum
Nearby frequency discrimination obtains the fine values of offset estimation to value；In addition loop circuit state is monitored and is also required in some pre-determined frequency
Rate and correlator range count the maximum Distribution value of frequency spectrum, that is, need to carry out multiple and different frequencies and correlator range
Maximum Data-Statistics.Due to being modulated with navigation message in GNSS signal, coherent integration time is often limited, to improve signal-to-noise ratio,
It often will do it noncoherent accumulation；In addition, also needing to calculate the mean value of frequency spectrum to the monitoring of loop.Due to the meeting when DFT is calculated
Frequency spectrum is traversed, be can be convenient and sought maximum value and mean value, calculate noncoherent accumulation value.
Calculation amount can be saved relative to DFT using FFT, the calculation amount of saving increases with frequency point number and increased, but frequency point
Number cannot choose at random, and frequency interval is determined by frequency point number, and to increase frequency domain resolution, fft algorithm is required to input time domain
Data padding, this will increase calculation amount again, and when frequency point number is less, the advantage that calculation amount is saved is unobvious.It, can when using DFT
With flexible choice frequency interval and frequency point number.In view of GNSS signal tracks typical scene, required frequency point number is simultaneously little, adopts at this time
With DFT scheme, zero padding can be avoided, calculation amount when practical application is suitable with FFT scheme, and can flexible configuration frequency interval
With frequency point number.The present invention is to carry out frequency domain decomposition to the integrated value that correlator exports using DFT.
Currently using DFT carry out frequency domain frequency discrimination and when frequency discrimination, statistics and search for frequency spectrum maximum value by Receiver Software or
Firmware realizes that DFT operation can be used software and calculate or be realized using DSP device.Software, which calculates, to be realized DFT operation that there are speed is low
Defect；DSP device realizes that arithmetic speed can be improved in DFT operation, but can not realize in large scale integrated circuit, not clever enough
It is living.Industry needs to improve a kind of scheme, to improve GNSS signal carrier track calculating speed, to improve system processing capacity.
Summary of the invention
In order to overcome the above-mentioned deficiencies of the prior art, the present invention provides a kind of satellite navigation baseband signal track algorithms
Hardware accelerator and method can be improved GNSS signal carrier track calculating speed, to improve system processing capacity, this hair
The bright technical solution for solving above-mentioned technical problem is as follows: a kind of hardware accelerator of satellite navigation baseband signal track algorithm,
Including data transmission module, data cache module, access control module, operation accumulator module and statistical module, the operation is tired
Adding module includes multiple operation summing elements, and the data cache module is connected by data transmission module with base band SoC system,
The operation accumulator module is connected with data cache module, and the access control module is transmitted with base band SoC system, data respectively
Module, data cache module, operation accumulator module are connected with statistical module, by the data transmission module by DFT data and
In the NCS data write-in data cache module of last time operation, access control module generates starting DFT operation after the completion of data write-in
Indication signal, operation accumulator module generate twiddle factor and carry out DFT fortune to DFT data parallel by multiple operation summing elements
It calculates, then by the way that the cumulative of DFT operation result is obtained new NCS data and be updated to the NCS data of last time operation, counts
Module obtains statistical result according to DFT operation result and updated NCS data, and data transmission module is again by updated NCS
Data are transmitted back to base band SoC system.
It further, further include data arbitration modules, the data cache module is passed by data arbitration modules and data
Defeated module, access control module, operation accumulator module are connected with statistical module, and data arbitration modules are used for before operation and statistics
Data transmission module and the interface of data cache module carry out arbitration selection afterwards.
It further, further include interface configuration module, the access control module passes through interface configuration module and base band SoC
System is connected.
Further, the data transmission module is connected by AHB host device interface with base band SoC system.
Further, the data cache module includes DFT data cell and NCS data cell, and DFT data cell is used for
The DFT operation result is deposited, NCS data cell is for depositing the NCS data.
A kind of hardware-accelerated method of satellite navigation baseband signal track algorithm, comprising the following steps:
1) DFT data and the NCS data of last time operation are stored in advance in base band SoC system, and hardware accelerator is being transported
The write-in of the NCS data of DFT data and last time operation is executed before calculating；
2) after the completion of DFT data and the NCS data of last time operation are written, hardware accelerator refers to according to starting DFT operation
Show that signal starts DFT operation；
3) hardware accelerator reads DFT data, and generates twiddle factor by the parameter of software configuration, passes through multiple operations
Summing elements carry out DFT operation parallel, then by obtaining updated NCS data to the cumulative of DFT operation result；
4) hardware accelerator statistics DFT operation result and updated NCS data, according to DFT operation result and update
NCS data afterwards obtain statistical result, and updated NCS data are transferred in base band SoC system；
5) after completing operation result statistics and the transmission of NCS data, hardware accelerator stops operation and counts and generate hard
Part interrupts, and reads updated NCS data after base band SoC system response hardware interrupts and carries out subsequent algorithm processing.
Further, in the step 1), DFT number is written by AHB host device interface with dma mode in hardware accelerator
According to the NCS data with last time operation.
Further, in the step 3), the parameter of software configuration specifically include correlator number, DFT operation frequency point number,
DFT operation sampling number and whether add up.
Further, in the step 4), it is equal that statistical result specifically includes energy peak, energy peak location and energy
Value.
Further, in the step 4), obtain after statistical result that there are in hardware accelerator statistical result.
Beneficial effect using above-mentioned further scheme is: the present invention proposes a kind of frequency domain realized in on-chip system chip
The hardware accelerator and method of carrier track algorithm specially carry out track algorithm time-frequency domain frequency discrimination in frequency domain to GNSS signal
DFT operation, while DFT operation result is counted, such as to searching for frequency spectrum maximum value within the scope of specified frequency and correlator,
And circuit and performance progress height optimization for the hardware accelerator, GNSS signal carrier track calculating speed is improved, from
And improve system processing capacity.
Detailed description of the invention
Fig. 1 is the schematic diagram of hardware accelerator of the present invention；
Fig. 2 is the flow chart of the hardware-accelerated method of the present invention.
Specific embodiment
The principle and features of the present invention will be described below with reference to the accompanying drawings, and the given examples are served only to explain the present invention, and
It is non-to be used to limit the scope of the invention.
A kind of hardware accelerator and method of satellite navigation baseband signal track algorithm are applied to base band SoC system, i.e.,
Baseband signal on-chip system chip System on Chip.Base band SoC system mainly include microcontroller, baseband processing module with
And system RAM module, it is integrated with the base band SoC system special disposal GNSS intermediate-freuqncy signal of this hardware accelerator, it is hardware-accelerated
Device is integrated in base band SoC system with AMBA AHB interface.This hardware accelerator external interface uses AMBA AHB interface
And hardware interrupts indication signal, i.e. Advanced Microprocessor Bus Architecture Advanced Microcontroller Bus
Structure and Advanced High-performance Bus Advanced High-Performance Bus, interface is simple, can be straight in the form of IP module
It connects and is integrated in base band SoC system.AMBA AHB interface includes AHB host device interface and AHB from equipment interface, is added in this hardware
In speed variator, data transmission module 1 is connected by AHB host device interface with base band SoC system, and interface configuration module 7 passes through AHB
It is connected from equipment interface with base band SoC system.Data are transmitted through the progress of AHB host device interface, the software of hardware accelerator
Configuration is carried out by AHB from equipment interface.The course of work and principle of hardware-accelerated method are as follows:
The GNSS intermediate-freuqncy signal of input is after Signal Pretreatment, respectively by the trapping module of base band SoC system and tracking mould
Each correlator coherent integration results that tracking module exports can be write system by block processing, the firmware program for running on microcontroller
In RAM module；
The source data for needing to carry out DFT operation is passed through AHB from equipment in the initial address of system RAM module by firmware program
Interface configures related register inside hardware accelerator, and configures other parameters such as correlator number, DFT operation frequency point
Number, DFT operation sampling number etc., last configuration register start DFT operation；
Hardware accelerator copies DFT operation source data from system RAM module with dma mode by AHB host device interface
And DFT operation cumulative data, after starting DFT operation and adding up, statistical result is stored in data and delayed by programming count calculated result
In storing module 2, and the resulting NCS data that will add up copy back system RAM module by AHB host device interface with dma mode, most
Interruption is generated afterwards；
After firmware program receives interruption, the resulting NCS data that add up directly are read from system RAM module, and slow from data
Storing module 2 reads statistical result, then carries out frequency domain tracking carrier wave ring algorithm, realizes and stablizes quickly tracking.
As shown in Figure 1, a kind of hardware accelerator of satellite navigation baseband signal track algorithm, including data transmission module
1, data cache module 2, access control module 3, operation accumulator module 4, statistical module 5, data arbitration modules 6 and interface configuration
Module 7.
Data transmission module 1 realizes that the bursting data between this hardware accelerator and base band SoC system are transmitted, and reduces number
According to moving the time, and realize that dma mode transmits data, i.e. the mode of Direct Memory Access directly accesses base band SoC
The system RAM module of system is not necessarily to microcontroller intervention, improves performance.Specifically, it realizes from base band SoC system and carries DFT fortune
Data cache module 2 inside the evidence that counts and NCS data to hardware accelerator, and from the data inside hardware accelerator
Cache module 2 reads the operation of updated NCS data writing systems RAM module.Wherein, NCS data are the energy after DFT operation
Magnitude accumulation result, i.e. non-coherent integration values.
Data cache module 2 include DFT data cell and NCS data cell, be respectively used to deposit DFT operation source data and
NCS data.
Access control module 3 realizes the timing control and starting control of this hardware accelerator, including single DFT operation
Or energy value after DFT operation it is cumulative when to the access control of data cache module 2.
Operation accumulator module 4 includes multiple operation summing elements；Specifically, operation accumulator module 4 includes that four operations are tired
Add unit, realize four DFT concurrent operations, and by operation result Serial output, be converted to energy value, realizes the energy that DFT is calculated
Magnitude is cumulative and data cache module 2 is written in the resulting NCS data that will add up.
Statistical module 5 realizes the statistics to DFT operation result and updated NCS data, such as to specified frequency and phase
It closes and searches for frequency spectrum maximum value within the scope of device.
The realization of data arbitration modules 6 carries out arbitration selection to the interface of data transmission module 1 and data cache module 2.Firmly
When part accelerator needs to be written the NCS data of DFT data and last time operation, data arbitration modules 6 pass through data transmission module 1
Data cache module 2 is written from base band SoC system in DFT data and the NCS data of last time operation；After the completion of write-in, work as hardware
When accelerator needs to carry out DFT operation, data arbitration modules 6 are DFT data and the NCS data of last time operation from data buffer storage
Operation accumulator module 4 is written in module 2, and 4 operation of operation accumulator module obtains DFT operation result and updated NCS data and handle
The above results are stored to data cache module 2, and data arbitration modules 6 are passed updated NCS data by data transmission module 1 again
Return base band SoC system.
Interface configuration module 7 realizes configuration interface function, realize software to the register configuration of this hardware accelerator and
Query function.
As shown in Fig. 2, a kind of hardware-accelerated method of satellite navigation baseband signal track algorithm, is mainly summarised as following step
It is rapid:
1. the phase before hardware accelerator work, after the correlator operation of the various code phases of base band tracking module output
Dry integrated value has been stored in base band as energy value accumulation result, that is, NCS data after DFT data and the operation of last time DFT
DFT data and NCS data are stored in the initial address of base band SoC system by SoC system, software, are write by AHB from equipment interface
The interface configuration module 7 for entering this hardware accelerator is reconfigured other DFT operational parameters such as correlator number, DFT operation frequency point
Number, DFT operation sampling number and whether cumulative etc., finally configuration starting DFT operation；
2. access control module 3 decodes configuration register, DFT operation time sequence indication signal, DFT operation to be launched are generated
When, control signal is issued to data transmission module 1, data transmission module 1 is automatically by AHB host device interface from base band SoC system
System passes sequentially through burst transfer modes and copies DFT data and NCS data with dma mode, and is written firmly by data arbitration modules 6
Data cache module 2 inside part accelerator.After pending data has copied, access control module 3 is issued to operation accumulator module 4
Start the indication signal of DFT operation；
After 3. operation accumulator module 4 receives starting DFT operation indication signal, from the data buffer storage inside hardware accelerator
Module 2 reads DFT data, generates twiddle factor by the parameter of software configuration, and carry out DFT operation.It is interior to accelerate DFT operation
Portion realizes 4 frequency point parallel DFT arithmetic elements, can carry out the DFT operation result output of most 4 frequency points simultaneously；Operation adds up mould
Frequency point completes DFT operation to correlator to block 4 one by one one by one, and by obtaining updated NCS number to the cumulative of DFT operation result
According to；
4. after operation accumulator module 4 completes DFT operation and the NCS cumulative of all frequency point datas of all correlators, statistics
Module 5 starts to count DFT operation result and updated NCS data respectively, obtains statistical result.Statistical result includes energy
Peak value, energy peak location and average energy value, wherein energy peak is the maximum value of all frequency point energy values of all correlators, energy
Measuring peak position is that correlator is numbered and value of frequency point, average energy value are the average value of all frequency point energy values of all correlators.
Simultaneously according to software configuration, updated NCS data are automatically copied in base band SoC system by data transmission module 1；
5. being generated after statistical module 5 completes operation result statistics and NCS data are copied into base band SoC system
Hardware interrupts, software directly read operation result and carry out subsequent algorithm processing.Operation result includes base band SoC internal system
The statistical result and peak detection result that access control module 3 saves in NCS data and this hardware accelerator.
This hardware accelerator and method realize the DFT operation of signal trace algorithm by hardware accelerator form, use
AMBA AHB interface can be directly integrated in base band SoC system with IP modular form, easily transplanting multiplexing, and be suitble to extensive collection
It is realized at circuit；AHB host device interface takes out operational data from specified memory initial address automatically with dma mode, and by sudden
Hairdo transmission mode copies data cache module 2 to dma mode, reduces data-moving time and microprocessor intervention, improves
Performance；When single DFT operation, each correlator can carry out the DFT operation of N number of frequency point number parallel, greatly improve technical performance, together
When take into account performance and Area Balanced, wherein N is that natural number and N are greater than 2；Energy value after single DFT operation is counted, is united
Counting result includes energy peak, energy peak location and average energy value；It, can be to the energy value after DFT operation according to software configuration
It carries out cumulative and the energy value accumulation result after DFT operation is counted, such as count cumulative average energy value, find out 3 squares
The Peak value position of the accumulated energies value of shape window；After each DFT operation and NCS energy accumulation, when calculating statistical result,
Hardware logic, which is sent, to interrupt, and software directly reads operation result and carries out subsequent algorithm processing.
Generally speaking, operation time is reduced by measure following aspects:
Energy value operation after realizing the DFT operation and DFT operation of signal trace algorithm by hardware accelerator form,
It is automatic simultaneously to realize that DFT operation result is cumulative, and DFT operation result and DFT operation accumulation result are subjected to peak detection
And statistics, making the same operand calculating time is about the 1/200 of the software calculating time, additionally by hardware realization DFT operation knot
The statistics and peak detection of fruit more reduce the plenty of time；
Parallel to carry out DFT operation, single DFT operation can carry out the DFT operation of N number of frequency point number parallel, make DFT operation time
It will be for the 1/N of usual serial computing time；
In the data cache module 2 by DFT data from base band SoC system copy to this hardware accelerator, or will deposit
When being placed on the DFT operation result of this hardware accelerator data cache module 2 and copying base band SoC system to, pass through AHB main equipment
Interface is carried out data transmission with dma mode, and data copy average time will be to be reduced to the 1/5 of I/O access mode.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (9)
1. a kind of hardware accelerator of satellite navigation baseband signal track algorithm, it is characterised in that: including data transmission module
(1), data cache module (2), access control module (3), operation accumulator module (4) and statistical module (5), the operation are cumulative
Module (4) includes multiple operation summing elements, and the data cache module (2) passes through data transmission module (1) and base band SoC system
System be connected, the operation accumulator module (4) is connected with data cache module (2), the access control module (3) respectively with base band
SoC system, data transmission module (1), data cache module (2), operation accumulator module (4) are connected with statistical module (5), pass through
By in DFT data and the NCS data of last time operation write-in data cache module (2), data are written the data transmission module (1)
Access control module (3) generates starting DFT operation indication signal after the completion, and operation accumulator module (4) generates twiddle factor and leads to
Cross multiple operation summing elements to DFT data parallel carry out DFT operation, then by DFT operation result it is cumulative obtain it is new
NCS data are simultaneously updated the NCS data of last time operation, and statistical module (5) is according to DFT operation result and updated NCS
Data obtain statistical result, and updated NCS data are transmitted back to base band SoC system again by data transmission module (1)；
It further include data arbitration modules (6), the data cache module (2) transmits mould by data arbitration modules (6) and data
Block (1), access control module (3), operation accumulator module (4) are connected with statistical module (5), data arbitration modules (6) for pair
Operation and statistics front and back data transmission module (1) and the interface of data cache module (2) carry out arbitration selection.
2. a kind of hardware accelerator of satellite navigation baseband signal track algorithm according to claim 1, feature exist
In: it further include interface configuration module (7), the access control module (3) passes through interface configuration module (7) and base band SoC system
It is connected.
3. a kind of hardware accelerator of satellite navigation baseband signal track algorithm according to claim 1, feature exist
In: the data transmission module (1) is connected by AHB host device interface with base band SoC system.
4. a kind of hardware accelerator of satellite navigation baseband signal track algorithm according to claim 1, feature exist
In: the data cache module (2) includes DFT data cell and NCS data cell, and DFT data cell is for depositing the DFT
Operation result, NCS data cell is for depositing the NCS data.
5. a kind of hardware-accelerated method of satellite navigation baseband signal track algorithm, which comprises the following steps:
1) DFT data and the NCS data of last time operation are stored in advance in base band SoC system, and hardware accelerator is before operation
Execute the write-in of the NCS data of DFT data and last time operation；
2) after the completion of DFT data and the NCS data of last time operation are written, hardware accelerator is according to starting DFT operation instruction letter
Number start DFT operation；
3) hardware accelerator reads DFT data, and generates twiddle factor by the parameter of software configuration, cumulative by multiple operations
Unit carries out DFT operation parallel, then by obtaining updated NCS data to the cumulative of DFT operation result；
4) hardware accelerator statistics DFT operation result and updated NCS data, according to DFT operation result and updated
NCS data obtain statistical result, and updated NCS data are transferred in base band SoC system；
5) after completing operation result statistics and the transmission of NCS data, hardware accelerator stops operation and counts and generate in hardware
It is disconnected, updated NCS data are read after base band SoC system response hardware interrupts and carry out subsequent algorithm processing.
6. a kind of hardware-accelerated method of satellite navigation baseband signal track algorithm according to claim 5, feature exist
In: in the step 1), DFT data and last time operation is written by AHB host device interface with dma mode in hardware accelerator
NCS data.
7. a kind of hardware-accelerated method of satellite navigation baseband signal track algorithm according to claim 5, feature exist
In: in the step 3), the parameter of software configuration specifically includes correlator number, DFT operation frequency point number, DFT operation sampled point
It counts and whether adds up.
8. a kind of hardware-accelerated method of satellite navigation baseband signal track algorithm according to claim 5, feature exist
In: in the step 4), statistical result specifically includes energy peak, energy peak location and average energy value.
9. a kind of hardware-accelerated method of satellite navigation baseband signal track algorithm according to claim 5, feature exist
In: in the step 4), obtain after statistical result that there are in hardware accelerator statistical result.
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| CN103499823A (en) * | 2013-09-29 | 2014-01-08 | 北京星地恒通信息科技有限公司 | Two-dimensional parallel acquisition system in spread spectrum communication |
| CN103499824A (en) * | 2013-10-22 | 2014-01-08 | 武汉大学 | Open-loop GNSS (Global Navigation Satellite System) signal carrier tracking method and system |
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