CN106921374B - Switched capacitor ISFET signal read circuits and its control method - Google Patents
Switched capacitor ISFET signal read circuits and its control method Download PDFInfo
- Publication number
- CN106921374B CN106921374B CN201710084922.9A CN201710084922A CN106921374B CN 106921374 B CN106921374 B CN 106921374B CN 201710084922 A CN201710084922 A CN 201710084922A CN 106921374 B CN106921374 B CN 106921374B
- Authority
- CN
- China
- Prior art keywords
- switch
- signal read
- read circuits
- connect
- amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
Landscapes
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- General Health & Medical Sciences (AREA)
- Pathology (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Analytical Chemistry (AREA)
- Biochemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Physics & Mathematics (AREA)
- Immunology (AREA)
- Electrochemistry (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)
- Amplifiers (AREA)
Abstract
The present invention relates to a kind of switched capacitor ISFET (ion sensing fet) signal read circuits and its control methods.The signal read circuits include ion sensing fet, amplification module and time-sequence control module, and the amplification module includes at least three switches, two capacitances and an amplifier.For the present invention by improving tradition ISFET signal read circuits and proposing new control method, the portion in the chip that realizes carries out biochemical signals the function of low power amplification in piece；, can be more accurate to the acquisition of biochemical signals after signal amplification, the signal accuracy higher acquired；Simultaneously as having only used an operational amplifier in the signal read circuits structure of the present invention, and two operational amplifiers are at least needed in traditional " clamp circuit ", thus the circuit power consumption of the signal read circuits of present disclosure significantly reduces；Disclosure is particularly well suited to applied to high-throughput biochemical device.
Description
Technical field
This invention relates generally to a kind of semiconductor microelectronic fields, and more specifically it relates to a kind of switched capacitor
ISFET signal read circuits and its control method.
Background technology
In 1970, Dutch scientist Piet Bergveld proposed ion sensing fet (Ion
Sensitive Field Effect Transistor, ISFET) concept, also take the lead in producing related device and be used for Na+
Ion detection.Subsequent researcher is gradually by the detection of main application and H+ concentration namely liquid pH value.With standard technology
Maturation, as a semiconductor devices, with the maturation of standard technology, array system has been stepped into the making of ISFET chips naturally
The stage of work.And in 2004, the Mark J.Milgrew of Britain took the lead in successfully producing first ISFET array chip, and
Add part biological test.Its specific works is shown in document：“A large transistor-based sensor array
Chip fordirect extracellular imaging " M.J.Milgrew, M.O.Riehle and D.R.S.Cumming,
Sensorsand Actuators, B：Chemical, 111-112, (2005), the 347-353 pages.
2006, the Christofer Toumazou of Imperial College of Science and Technology proposed to detect single base nucleotide with ISFET
Thought, and the test result of single base is obtained, specific works are shown in document：“Protons and single nucleotide
polymorphism detection：A simple use for the Ion Sensitive Field Effect
Transistor " Sunil Purushothaman, Chris Toumazou, and Chung-Pei Ou, Sensorsand
Actuators, B：Chemical, 114, (2006), the 964-968 pages.It is ground in terms of with sequencing technologies and the making of ISFET arrays
The development studied carefully released a kind of semiconductor sequenator based on ISFET devices, the sequenator in Ion Torrent companies in 2011
Other than control system and liquid channel system, all sensing elements acquire signal circuit within a chip, therefore as
The poster that its company is publicized i.e. " chip is exactly sequenator ".
For the variation of pH value of solution or Portugal caused by single base polymerisation in biological respinse, such as gene sequencing DNA
The detection of grape sugar ion concentration, when sample size very little, signal is all extremely faint.And Measurement for Biotechnique is because of its high pass
The increase of the demand of amount, sample size can be highly difficult.In traditional ISFET reading circuits, the reaction signal that is generally initially obtained
Basic numerical value can reach more than half of supply voltage.Therefore variable quantity is captured on the basis of this generally rely on external circuit.
And external circuit because its environment itself limitation, micro variable quantity is often submerged in noise, therefore chip is to environmental condition
Extremely rely on.And require to accomplish this extreme experimental situation high expensive, and it is unfavorable for chip product making.But in view of class
Like the characteristics of sequencing technologies --- bio signal is mainly reflected on variable quantity, so best solution should be will be micro
Variable quantity signal, which is placed in chip, carries out signal amplification, and external equipment can detect subtleer in relatively blunt environment
Variation.
In traditional chip reading circuit, resistance and current source is often utilized to form a stabilizing potential poor then sharp
Resistance both ends potential is sent into ISFET source and drain both ends with unity gain amplifier so that ISFET device source-drain voltages keep permanent
It is fixed, also i.e. by ISFET devices both ends clamper, finally obtain signal voltage.Because of the reason of unity gain amplifier of clamper,
In fact there is no change change amount signal sizes for such method, and semaphore is very faint, is detrimental to signal acquisition.Cause
This, those skilled in the art need proposition one that can be amplified in piece, and signal read circuits with high accuracy are come accurately
Read ISFET device signals.
Invention content
In order to solve the problems, such as not high, the of the invention mesh of existing in the prior art interior signal read circuits amplification precision
Be to provide a kind of switched capacitor ISFET (Ion Sensitive Field Effect Transistor, the quick field effect of ion
Answer transistor) signal read circuits.
Switched capacitor ISFET signal read circuits include：
Ion sensing fet, the ion sensing fet includes drain electrode, source electrode and grid, wherein draining
Ground connection, source electrode are connected with stabling current input terminal；
Amplification module, the amplification module includes at least three switches, two capacitances and an amplifier, wherein first opens
It closes one end connection ion sensing fet source electrode other end and connects the first capacitance, first capacitance one end connects with first switch
Connect, the other end is connect with amplifier inverting input, and second switch one end is connect with amplifier inverting input, the other end with put
Big device output end connection, second capacitance one end are connect with amplifier inverting input, and the other end is connect with amplifier out, the
One end of the other end and the first capacitance of three switch one end and first switch connects, and the other end is connect with common mode electrical level, is amplified
Device normal phase input end is connect with common mode electrical level；
Time-sequence control module, the time-sequence control module are separately connected first switch, second switch and third switch to divide
The folding of three switches is not controlled.
Further, the signal read circuits may also include the 4th switch, and the 4th switch one end connects external power supply, separately
One end is connect with one end of first switch and the first capacitance.
Further, the signal read circuits may also include level-one source follower module, the follower module packet
Two transistors are included, wherein first crystal tube grid is connect with amplifier out, the first transistor drain electrode and second transistor
Source electrode connects, and second transistor grid is connect with bias current, second transistor grounded drain, signal read circuits output signal
End is connected with the first transistor drain electrode and second transistor source electrode.
Further, the switch in the signal read circuits is single PMOS (positive channel
Metal Oxide Semiconductor) pipe or cmos transmission gate (Complementary Metal Oxide
Semiconductor Transmission Gate)。
Further, the sequential control circuit in the signal read circuits is by field programmable gate array
(Field-Grogrammable Gate Array, FPGA) and data collecting card are constituted.
Further, the capacitance size in the signal read circuits is 400fF-1pF.
It is a further object to provide a kind of method of the control signal read circuits, controlling cycle T packets
Include following three subcycles：
(1) it is closed first switch, disconnects second switch and third switch；
(2) it is closed first switch and the second switch, disconnects third switch；
(3) first switch and the second switch is disconnected, third switch is closed after the interval of delta t time, and end in the subcycle
Separated third switch when preceding Δ t；
Wherein, 50ns≤Δ t≤200ns.
It is a further object of the present invention to provide another method for controlling the signal read circuits, controlling cycle K packets
Include following five subcycles：
(a) it is closed first switch, disconnects second switch, third switch and the 4th switch；
(b) it is closed first switch and the second switch, disconnects third switch and the 4th switch；
(c) first switch, second switch and the 4th switch are disconnected, third switch is closed after the interval of delta t time, and in the son
Separated third switch when Δ t before period cut-off；
(d) it is closed second switch and the 4th switch, disconnects first switch and the second switch；
(e) it is closed second switch and third switch, disconnects first switch and the 4th switch；
Wherein, 50ns≤Δ t≤200ns.
Signal read circuits and control method of the present invention compared with prior art the advantages of be：It is passed by improving
ISFET signal read circuits of the uniting control method new with proposition, the portion in the chip that realizes carry out low power in piece to biochemical signals
The function of amplification., can be more accurate to the acquisition of biochemical signals after signal amplification, the signal accuracy higher acquired.Simultaneously
Because having only used an operational amplifier in the signal read circuits structure of the present invention, and in traditional " clamp circuit " at least
Two operational amplifiers are needed, thus the circuit power consumption of the signal read circuits of present disclosure significantly reduces.Based on above excellent
Point, the signal read circuits and its control method of present disclosure are particularly suitable for application to high-throughput biochemical device, such as survey
Sequence instrument chip etc..
Description of the drawings
For the technology contents further illustrated the present invention, with reference to embodiments and attached drawing is described in detail as after, wherein：
Fig. 1 is basic structure of the ISFET devices under standard technology；
Fig. 2 is ISFET device classical signal reading circuits；
Fig. 3 is the circuit diagram of signal read circuits one embodiment of the present invention；
Fig. 4 is the circuit diagram of another embodiment of signal read circuits of the present invention；
Fig. 5 is the circuit diagram of another embodiment of signal read circuits of the present invention；
Fig. 6 is the circuit flow diagram of control signal read circuits method one embodiment of the present invention；
Fig. 7 is the switch folding condition of control signal read circuits method one embodiment of the present invention, amplified signal
With reading signal schematic representation；
Fig. 8 is the clock design diagram of control signal read circuits method one embodiment of the present invention；
Fig. 9 is related to solution ph is surveyed bent by the output signal of signal read circuits one embodiment of the present invention
Line.
Specific implementation mode
Understand to make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and joins
According to attached drawing, the present invention is described in further detail below.
Fig. 1 is making structure of the ISFET devices under standard technology.Wherein sensitive layer is the passivation of standard CMOS process
Layer, and passivation layer often uses silica and silicon nitride material.Top material is often silicon nitride (because of technological reason, Ke Nengwei
Silicon oxynitride).Generally, Si3N4Or SiNxOyIt is effective sensitive membrane, when device sensitivity, top device is placed in solution,
Solution makes its potential stablize in a particular value by specific reference electrode.Hydrogen ion in solution is made with passivation layer surface
With generation charge effect.Charge effect is coupled to top layer metallic layer by passivation layer, is finally transmitted to bottom transistor.Hydrogen from
Son number can be characterized by the electric signal in circuit, realize the function of chemical-sensitive.
Fig. 2 is for ISFET device classical signal reading circuits.It can be seen that 3 amplifiers are needed in reading circuit altogether, two electricity
Stream source.Two of which in the amplifier allows ISFET output signals to avoid channel length to the drain-source voltage of clamper ISFET
The influence of mudulation effect.
When sensing unit is started to work, electric current is perfused to ISFET in top current sources so that flows through the electricity of ISFET
It flows constant.Current-voltage correlation according to MOSFET in saturation region：
Linear zone
Saturation region
When we can know that electric current is constant, if being in saturation region, VGS-VTHIt answers constant；If being in linear zone,It answers constant.
If it is assumed herein that VDSIt is constant, make charge effect be coupled to metal layer, Ye Jihua according to previously mentioned chemical-sensitive
Learn sensitive so that the metal layer potential to suspend is changed, then VGS=VG-VSIn VGNecessarily change, and VTHNo
Become, therefore VSVariation must be followed, could make circuit constant current.
According to the output characteristic curve of MOSFET, in order to promote its chemical-sensitive ability, selection in this invention allows ISFET
It is operated in linear zone.Obtain ISFET source electrodes (S) output voltage
Wherein VGIt is VRefWith the coefficient result of sensitive interface.Chemical interface potential
R is gas constant in formula, meets pV=nRT, while R=kNA=8.314J/ (K*mol), F are Faraday constants,
α is sensitivity coefficient, usually one close to 1 value.In short, can finally obtain
VG∝ψ (5)
And then it obtainsFor a definite value, this value theoretical maximum is 59.2mV/pH.Know V according to (3) formulaSIt follows
VGVariation namely VSDirectly reflect the variation of chemical property.
The circuit diagram of Fig. 3 signal read circuits one embodiment of the present invention.The implementation of the signal read circuits
Example include：
Ion sensing fet (ISFET), amplification module and time-sequence control module, the amplification module include at least
Switch S1, S2 and S3, capacitance C1 and C2 and amplifier A；
Wherein the one end first switch S1 connection the ISFET source electrode other ends connect the first capacitance C1, first one end capacitance C1 with
The first switch S1 connection other ends are connect with amplifier A inverting inputs (-), and the one end second switch S2 and amplifier A reverse phases are defeated
Enter end (-) connection, the other end is connect with amplifier A output ends, and second one end capacitance C2 connects with amplifier A anti-phase inputs (-) end
Connect, the other end is connect with amplifier A output ends, third open S3 close one end connect with first switch S1 one end of the first capacitance C1 with
And first capacitance C1 one end connection, the other end connect with common mode electrical level Vcm, amplifier A normal phase input ends (+) and common mode electrical level
Connect Vcm.
It can be seen that compared to traditional reading circuit, of the invention main distinction is ISFET grounded drains.Drain electrode
The variable quantity for the output voltage that caused benefit is ISFET device source electrodes is grounded always with reference to ground, is similar to reference to ground
AC signal.The amplification of signal can be just changed to signal in piece in this way, without increasing circuit complexity.
In amplification module, input signal is charged by the first capacitance of closed pair C1 of first switch S1, after charging
First capacitance both ends potential difference is the difference that source voltage subtracts common mode electrical level；The charge release of C1, i.e., close on first capacitance
The pole plate of ISFET source electrodes discharges charge to common mode electrical level Vcm, and the charge close to output voltage terminal is discharged into the second capacitance C2,
Charge is identical as electric charge number on the first capacitance C1 of original on final C2 two-plates, changes the both ends C2 potential difference, namely change
Output voltage Vout.
Here, the switch can be cmos transmission gate.In further embodiments, switch can be single PMOS tube.
The capacitance size is between 400fF-1pF.
Fig. 4 is the circuit diagram of another embodiment of signal read circuits of the present invention.The signal read circuits
Embodiment further includes the 4th switch S4.
Fig. 5 is the circuit diagram of another embodiment of signal read circuits of the present invention.The signal read circuits
Embodiment further includes level-one source follower module, and the follower module includes transistor M1 and M2, wherein the first transistor
M1 grids are connect with amplifier A output ends, and the first transistor M1 drain electrodes are connect with second transistor M2 source electrodes, second transistor M2
Grid is connect with bias current Bias, second transistor M2 grounded drains, signal read circuits output signal end Vout and first
Transistor M1 drain electrodes are connected with second transistor M2 source electrodes.
By using a kind of following control method controls signal read circuits shown in Fig. 3, shown in fig. 6 open is obtained
Conjunction state, amplified signal and reading signal schematic representation,
The controlling cycle T of the control method includes following three subcycles：
(1) it is closed first switch S1, disconnects second switch S2 and third switch S3；
(2) it is closed first switch S1 and second switch S2, disconnects third switch S3；
(3) first switch S1 and second switch S2 is disconnected, third switch S3 is closed after the interval of delta t time, and in son week
Separated third switch when Δ t before phase cut-off；
Wherein, 50ns≤Δ t≤200ns.
Signal read circuits shown in Fig. 4 are controlled by using a kind of method of the control signal read circuits, are obtained
Following Fig. 6 circuits flow diagrams,
That is controlling cycle K includes following five subcycles：
(a) it is closed first switch, disconnects second switch, third switch and the 4th switch；
(b) it is closed first switch and the second switch, disconnects third switch and the 4th switch；
(c) first switch, second switch and the 4th switch are disconnected, third switch is closed after the interval of delta t time, and in the son
Separated third switch when Δ t before period cut-off；
(d) it is closed second switch and the 4th switch, disconnects first switch and the second switch；
(e) it is closed second switch and third switch, disconnects first switch and the 4th switch；
Wherein, 50ns≤Δ t≤200ns.
Subcycle a is that S1 is closed, and S2, S3 and S4 are all off, it is assumed that input voltage vin=1.3V ± 2mV.Subcycle b
It is also be closed switch S2, because amplifier void is short, empty disconnected reason, nodes X incoming transport always, so node at this time
Vout is also AC deposition, and circuit starts to charge to C1, and after the charging process of short time, C1 both end voltages are equal to Vin.Again
Into subcycle c, S1, S2 are simultaneously switched off, and be closed S3.After being closed S3, switching capacity needs to discharge, and pole plate electric discharge in left and right is logical
Road is not quite similar.The left pole plates of capacitance C1 discharge into ground, and right pole plate is with the connect ports amplifier A because can not discharge, therefore only
C2 capacitances can be discharged into.Namely at this time on C2 capacitances amount of charge should be same or similar with entrained amount of charge on preceding C1.
According to C1*Vin=C2*Vout, it is known that Vout=C1/C2*Vin.If C1/C2 sizes are 3-10, signal will be put
It is 3-10 times big.Last signal is exported by source level follower.Therefore subcycle a-c is really that a realization signal amplifies
Process.
Certainly, because the characteristics of switched capacitor amplifier --- amplification process also allows for what it was obtained by timing control
Biochemical signals are in fact and discontinuous.In order to ensure obtained discontinuous biochemical signals are normal, with regard to needs pair in circuit design
Chip itself is calibrated.Calibrating mode is controlled known calibration signal using switch after each amplified signal
It is applied to signal input, by input/output relation, whether verification amplifier works normally.Such design simultaneously, follow-up
Data processing when, a kind of data of label type can be formed, be convenient for data processing.When subcycle d, S4 be closed, circuit with
Calibration level charges to capacitance C1.It is then release charge again when subcycle e, realizes amplification.Calibration letter each time
Number amplification can whether correct to decision circuitry working condition, play an important role in the practical application of circuit.Therefore
Subcycle d-e is actually the process of circuit calibration.
In addition, capacitance more large charge storage capacity is stronger, the charging time needed is longer, it may be desirable to the period of bigger.Allusion quotation
The 300fF capacitances of type, about 1 μ s of charging time.According to the size of capacitance value in circuit provided by the invention, i.e. 400fF-
The charging pulse time is set greater than 2 μ s by 1pF.
Fig. 7 is the switch folding condition of control signal read circuits embodiment of the method, amplified signal described in Fig. 6 and reads letter
Number signal.Upper four signals are that the control signal of switch S1, S2, S3 and S4 (transmission gate) N pipes namely high level are led respectively in figure
Logical, low level disconnects.The input/output signal of corresponding on off state also has displaying simultaneously.Vin is input signal, and bottom Vout is
The output signal curve changed with clock.K in abscissa indicates controlling cycle where it, the control of subscript digital representation
The periodicity in period, following table letter indicate subcycle where it.Wherein it is noted that when switching closure for S3,
It needs deliberately to open the Δ t times with previous clock interval, avoids clock overlapping, mistake occur.
Fig. 8 is the clock design diagram of present invention control signal read circuits method one embodiment.
In this embodiment, it switchs as passgate structures.Therefore one high and one low two electricity are needed to the control of each switch
Flat to coordinate control, clock demonstrated in Figure 8 is 3 to 8 combinational logics.During one action, need to jump in total
Turn 5 times, is that input signal [D2, D1, D0] jumps to [1,0,0] from [0,0,0], the corresponding truth table of the combinational logic circuit is shown in
Table 1, on off state is shown in Table 2.
1 signal read circuits of table switch control combination logic corresponds to truth table
2 signal read circuits of table switch control combination logic corresponds on off state
Certainly, those skilled in the art can also edit design of other logics for control method clock by FPGA.
Fig. 9 is related to solution ph is surveyed bent by the output signal of signal read circuits one embodiment of the present invention
Line.Concentrated area in its center, minimum change 0.03pH, variable signal itself about 2mV (susceptibility 40mV/pH),
In inside by 3-10 times of amplification, then variation about 6-20mV is embodied in outside.It is generally being tested using 16 data collecting cards
Variable signal can successfully be detected under room environmental.And if using traditional non-amplified reading circuit mode, generally adopt
Truck precision is 3mV, can not be correctly obtained minimum change signal.
The embodiment of the present invention being described with reference to the drawings is exemplary, and is only used for explaining the present invention, and cannot be considered as
Limitation of the present invention.In order to avoid unnecessarily obscuring the embodiment, this part is to some techniques knowns, i.e.,
Technology that it would have been obvious for a person skilled in the art, is not described in detail.
Claims (5)
1. a kind of switched capacitor ISFET signal read circuits, which is characterized in that including：
Ion sensing fet, the ion sensing fet includes drain electrode, source electrode and grid, wherein drain electrode connects
Ground, source electrode are connected with stabling current input terminal；
Amplification module, the amplification module include at least three switches, two capacitances and an amplifier, wherein first switch one
End connection ion sensing fet source electrode, the other end connect the first capacitance, and first capacitance one end is connect with first switch, separately
One end is connect with amplifier inverting input, and second switch one end is connect with amplifier inverting input, the other end and amplifier
Output end connects, and second capacitance one end is connect with amplifier inverting input, and the other end is connect with amplifier out, and third is opened
It closes one end to connect with one end of the first switch other end and the first capacitance, the other end is connect with common mode electrical level, and amplifier positive is defeated
Enter end to connect with common mode electrical level；
Time-sequence control module, the time-sequence control module are separately connected first switch, second switch and third switch to control respectively
Make the folding of three switches；
Further include level-one source follower module, the follower module includes two transistors, wherein first crystal tube grid
It is connect with amplifier out, the first transistor source electrode is connected with second transistor drain electrode, second transistor grid and biased electrical
Stream connection, second transistor source electrode ground connection, signal read circuits output signal end and the first transistor source electrode and second transistor
Drain electrode is connected；
The sequential control circuit is made of field programmable gate array and data collecting card.
2. switched capacitor ISFET signal read circuits according to claim 1, which is characterized in that further include the 4th opening
It closes, the 4th switch one end connects external power supply, and the other end is connect with one end of first switch and the first capacitance.
3. switched capacitor ISFET signal read circuits according to claim 1, which is characterized in that the switch is single
A PMOS tube or cmos transmission gate.
4. a kind of method of switched capacitor ISFET signal read circuits described in control claim 1, which is characterized in that one
Controlling cycle T includes following three subcycles：
(1) it is closed first switch, disconnects second switch and third switch；
(2) it is closed first switch and the second switch, disconnects third switch；
(3) first switch and the second switch is disconnected, third switch, and the Δ t before the subcycle ends are closed after the interval of delta t time
When separated third switch；
Wherein, 50ns≤Δ t≤200ns.
5. a kind of method of switched capacitor ISFET signal read circuits described in control claim 1, which is characterized in that one
Controlling cycle K includes following five subcycles：
(a) it is closed first switch, disconnects second switch, third switch and the 4th switch；
(b) it is closed first switch and the second switch, disconnects third switch and the 4th switch；
(c) first switch, second switch and the 4th switch are disconnected, third switch is closed after the interval of delta t time, and in the subcycle
Separated third switch when Δ t before cut-off；
(d) it is closed second switch and the 4th switch, disconnects first switch and the second switch；
(e) it is closed second switch and third switch, disconnects first switch and the 4th switch；
Wherein, 50ns≤Δ t≤200ns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710084922.9A CN106921374B (en) | 2017-02-16 | 2017-02-16 | Switched capacitor ISFET signal read circuits and its control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710084922.9A CN106921374B (en) | 2017-02-16 | 2017-02-16 | Switched capacitor ISFET signal read circuits and its control method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106921374A CN106921374A (en) | 2017-07-04 |
| CN106921374B true CN106921374B (en) | 2018-07-31 |
Family
ID=59454061
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710084922.9A Active CN106921374B (en) | 2017-02-16 | 2017-02-16 | Switched capacitor ISFET signal read circuits and its control method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106921374B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108192802A (en) * | 2018-01-24 | 2018-06-22 | 中国科学院半导体研究所 | The amplification of ISFET arrays and reading circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2505998B1 (en) * | 2009-11-25 | 2017-01-04 | Idemitsu Kosan Co., Ltd. | Measuring method for degree of degradation of lubricating oil, and measuring device therefor, as well as lubricating oil monitoring system in machine and device |
| CN103392233B (en) * | 2010-06-30 | 2016-08-24 | 生命科技公司 | Array column integrator |
-
2017
- 2017-02-16 CN CN201710084922.9A patent/CN106921374B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN106921374A (en) | 2017-07-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105911126B (en) | Matched transistor pair circuit | |
| JP5890423B2 (en) | ISFET device | |
| Sawada et al. | Highly sensitive ion sensors using charge transfer technique | |
| TWI235236B (en) | Ion-sensitive circuit | |
| US7662341B2 (en) | Sensor arrangement and method for operating a sensor arrangement | |
| JP5509118B2 (en) | Signal processing circuit including ion sensitive field effect transistors and method for monitoring fluid properties | |
| Hu et al. | A 32$\times $32 ISFET chemical sensing array with integrated trapped charge and gain compensation | |
| Milgrew et al. | The fabrication of scalable multi-sensor arrays using standard CMOS technology [chemical sensors] | |
| CN104614404B (en) | Ion sensitive field effect transistor sensor and its reading circuit | |
| Matsuo et al. | Charge Transfer Type pH Sensor with Super High Sensitivity | |
| CN103472114B (en) | Multichannel ion sensitive field effect transistor (ISFET) sensor readout circuit with compensation function | |
| CN106921374B (en) | Switched capacitor ISFET signal read circuits and its control method | |
| Livi et al. | Sensor system including silicon nanowire ion sensitive FET arrays and CMOS readout | |
| CN103376284A (en) | Multi-parameter low-power-consumption current-mode ion sensitive field effect tube array sensor device | |
| Zeng et al. | Current-mode ISFET array with row-parallel ADCs for ultra-high speed ion imaging | |
| Rani et al. | ISFET pH sensor characterization: towards biosensor microchip application | |
| Miscourides et al. | A linear programmable-gate ISFET array operating in velocity saturation | |
| Tabrizi et al. | A High Dynamic Range Dual 8× 16 Capacitive Sensor Array for Life Science Applications | |
| Aslanzadeh et al. | A low-power voltage-clamped CMOS pH to frequency sensor | |
| US8872520B2 (en) | Sensor and measurement method | |
| Luo et al. | Improved pH Sensing Performance with Microarray ISFETs under Pulse AC Bias | |
| CN108192802A (en) | The amplification of ISFET arrays and reading circuit | |
| Sohbati et al. | A piecewise linear approximating ISFET readout | |
| Savadjiev | Design and fabrication of an ion sensitive field effect transistor and readout circuit using a commercial TSMC 65nm process | |
| Aslanzadeh et al. | A differential low-power voltage-clamped ISFET topology for biomedical applications |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |