CN106919452B - Multi-core heterogeneous system and management method of hardware resources thereof - Google Patents
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Abstract
The invention discloses a multi-core heterogeneous system and a management method of hardware resources thereof, wherein the management method of the hardware resources of the multi-core heterogeneous system comprises the following steps: the master checks the public hardware resources required by the operation of each system for registration; reading and managing common hardware resources; and receiving hardware resource demand information sent by a slave core of a certain system, and distributing the common hardware resources required by the operation of the system to the corresponding slave core according to the registration information corresponding to the system. The management method of the hardware resources of the multi-core heterogeneous system can dynamically allocate the common hardware resources required by various systems according to the configuration requirements of the system resources, ensure that the common hardware resources of the multi-core heterogeneous system can be more flexibly utilized, and avoid the waste of the hardware resources.
Description
Technical Field
The invention relates to the technical field of wireless communication, in particular to a multi-core heterogeneous system and a management method of hardware resources thereof.
Background
The current multi-core processing system mainly has two structures: one is SMP (symmetric Multi-Processing), and the other is AMP (Asymmetric Multi-Processing).
In the field of wireless communications, heterogeneous multi-core processing systems are common, for example, a baseband chip needs to process a baseband signal, the processing of the baseband signal includes protocol function layers such as L1 (physical layer), L2 (sublayers such as MAC, RLC, PDCP, etc.), L3 (such as RRC), and the like, and a special processor or accelerator is usually adopted for the baseband chip, and a general core is also used for management of a base station and functions of L2 and L3 of a wireless communication protocol, so the baseband chip may adopt a chip with an AMP architecture, a part of the cores complete functions of L1 (physical layer), and a part of the cores complete management of a base station and partial functions of L2 and L3 of the wireless communication protocol.
As a common communication device in the wireless communication field, a wireless base station includes a single-mode base station and a multi-mode (common modes of the base station include GSM, UMTS, CDMA, LTE _ FDD, LTE _ TDD, etc.) base station, however, in the prior art, a heterogeneous multi-core processing system is adopted for a baseband chip of the wireless base station in order to expand the capacity of the baseband chip, and the baseband chip of the existing wireless base station has fixed hardware resources (hardware resources include but are not limited to a network port queue, a counter, a shared memory, inter-core interrupt, etc.) for each mode, and the hardware resources cannot be shared, thereby causing waste of the hardware resources.
Disclosure of Invention
The invention mainly aims to provide a management method of hardware resources of a multi-core heterogeneous system, which can dynamically allocate resources required by various systems according to system resource allocation requirements and reduce the waste of hardware resources.
To achieve the above technical object, the present invention provides a method for managing hardware resources of a multi-core heterogeneous system, comprising the following steps:
the master checks the public hardware resources required by the operation of each system for registration;
receiving hardware resource demand information sent by a slave core in a certain system;
and distributing the common hardware resources required by the operation of the system to the corresponding slave cores according to the registration information corresponding to the system.
Further, the multi-core heterogeneous system is a multi-core heterogeneous system of a base station.
Further, after the step of receiving the hardware resource requirement information sent by the slave core of a certain system and allocating the common hardware resource required by the operation of the system to the corresponding slave core according to the registration information corresponding to the system, the method further includes:
monitoring the running state of each system;
and if the operation of a certain system is monitored to be abnormal, recovering all common hardware resources of the system.
Further, a common hardware resource required for data transmission between the master core and the slave core is reserved in the master core; arranging the rest common hardware resources in a mapping relation table form, wherein the mapping relation table comprises the type, the size and the position information of the common hardware resources.
Further, the step of receiving the hardware resource requirement information sent by the slave core of a certain system, and allocating the common hardware resource required by the operation of the system to the corresponding slave core according to the registration information corresponding to the system includes:
receiving hardware resource demand information sent from a core of a certain system, and inquiring position information corresponding to the common hardware resource required by the system according to the mapping relation table;
and sending the position information corresponding to the common hardware resource required by the system to the slave core corresponding to the system.
The invention also provides a multi-core heterogeneous system, which comprises a main core, a slave core and a common hardware resource, wherein the main core comprises:
the hardware resource registration module is used for registering and registering common hardware resources required by the operation of each system;
the hardware resource management module is used for reading and managing the common hardware resources;
and the hardware resource allocation module is used for receiving the hardware resource demand information sent by the slave core of a certain system and allocating the common hardware resource required by the operation of the system to the corresponding slave core according to the registration information corresponding to the system.
Further, the multi-core heterogeneous system is a multi-core heterogeneous system of a base station.
Further, the main core further comprises:
the system operation monitoring module is used for detecting the operation state of each system;
and the hardware resource recovery module is used for recovering all common hardware resources of a certain system if the operation of the system is monitored to be abnormal.
Further, the hardware resource management module comprises:
the hardware resource reservation unit is used for reserving common hardware resources required by data transmission between the master core and the slave core;
and the hardware resource list unit is used for arranging the rest common hardware resources in a mapping relation table form, and the mapping relation table comprises the types, the sizes and the position information of the common hardware resources.
Further, the hardware resource allocation module comprises:
the hardware resource query unit is used for receiving the hardware resource demand information sent from the slave core of a certain system and querying the position information corresponding to the public hardware resource required by the system according to the mapping relation table;
and the hardware resource transmission unit is used for transmitting the position information corresponding to the common hardware resource required by the system to the slave core corresponding to the system.
The invention provides a multi-core heterogeneous system and a management method of hardware resources thereof, wherein the management method of the hardware resources of the multi-core heterogeneous system comprises the following steps: the master checks the public hardware resources required by the operation of each system for registration; reading and managing common hardware resources; and receiving hardware resource demand information sent by a slave core of a certain system, and distributing the common hardware resources required by the operation of the system to the corresponding slave core according to the registration information corresponding to the system. The management method of the hardware resources of the multi-core heterogeneous system can dynamically allocate the common hardware resources required by various systems according to the configuration requirements of the system resources, ensure that the common hardware resources of the multi-core heterogeneous system can be more flexibly utilized, and avoid the waste of the hardware resources.
Drawings
Fig. 1 is a schematic flowchart of an embodiment of a method for managing hardware resources of a multi-core heterogeneous system according to the present invention;
FIG. 2 is a schematic flow chart of step S12 in FIG. 1;
FIG. 3 is a schematic flow chart of step S14 in FIG. 1;
fig. 4 is a schematic flowchart of a method for managing hardware resources of a multi-core heterogeneous system according to another embodiment of the present invention;
FIG. 5 is a schematic structural diagram of an embodiment of a main core of a multi-core heterogeneous system provided in the present invention;
FIG. 6 is a block diagram of a hardware resource management module of the primary core of FIG. 5;
FIG. 7 is a block diagram of a hardware resource allocation module of the primary core of FIG. 5;
FIG. 8 is a schematic structural diagram of another embodiment of a primary core of a multi-core heterogeneous system provided in the present invention;
fig. 9 is a schematic structural diagram of a multi-core heterogeneous system applied to a base station system according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of further refinement of the multi-core heterogeneous system of fig. 9.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
Fig. 1 is a schematic flow chart of an embodiment of a method for managing hardware resources of a multi-core heterogeneous system provided by the present invention, and please refer to fig. 1, where the method for managing hardware resources of a multi-core heterogeneous system includes the following steps:
step S10, the main core registers the public hardware resources required by the operation of each system;
the multi-core heterogeneous system comprises a main core and at least one slave core as the name implies, the number of the slave cores is not limited, the specific number depends on the requirement of a system, and the operating systems operated by the main core and the slave cores are different. The main core runs an operating system supporting multi-process scheduling, so that the hardware resource requirements of various systems can be conveniently registered and registered, and the secondary core runs a light-weight operating system or does not run the operating system, so that the requirements of high performance and low time delay of running of various systems can be conveniently met.
The master core creates a master process, and creates corresponding slave processes according to the system configured by the system, the system is of a single system or a multi-system, correspondingly, the number of the slave processes of the master core is one or more, the slave processes perform protocol processing between the slave cores and the master core corresponding to each system, and register the required hardware resources of each system.
Step S12, reading and managing common hardware resources;
the master process performs read management on the common hardware resources according to a certain rule, and the master process reserves a part of the hardware resources for the transmission of normal data (including request messages, response messages and the like) between the master core and the slave core so as to maintain the normal communication requirement between the master core and the slave core and reserve a part of the hardware resources for the operation of the slave core corresponding to each system.
Step S14, receiving the hardware resource requirement information sent by the slave core of a certain system, and allocating the hardware resource required by the operation of the system to the corresponding slave core according to the registration information corresponding to the system.
The method comprises the steps that a master process waits for hardware resource demand messages sent by slave cores of all modes, hardware resource demand information sent by the slave cores of a certain system is sent to the master core, the master core carries out protocol processing on the hardware resource demand information through the slave processes of the corresponding systems in the master core, the processed hardware resource demand information is sent to the master process, the master process obtains hardware resources required by the systems according to registration information corresponding to the systems in the slave processes of the corresponding systems, and the hardware resources required by operation of the systems are distributed to the corresponding slave cores.
Further, the multi-core heterogeneous system may be a multi-core heterogeneous system of a base station, for example, a multi-core heterogeneous baseband chip of a wireless base station, or a multi-core heterogeneous radio frequency chip of a wireless base station, and of course, the multi-core heterogeneous system is not limited thereto, and may also be a multi-core heterogeneous chip of other communication devices.
Further, referring to fig. 2, fig. 2 is a schematic flowchart of step S12 in fig. 1, and step S12 includes:
step S120, the main core reserves common hardware resources required by data transmission between the main core and the auxiliary core;
and step S122, arranging the rest common hardware resources in a mapping relation table form, wherein the mapping relation table comprises the types, sizes and position information of the common hardware resources.
In view of the above, the common hardware resources required for data transmission between the master core and the slave core need to be reserved first, and the remaining common hardware resources are arranged in a mapping relationship table form and used as common hardware resources, i.e., a resource pool, when the slave core operates corresponding to each system, where the mapping relationship table should include the type, size, and location (including an index or an address) of each hardware resource.
Further, referring to fig. 3, fig. 3 is a schematic flowchart of step S14 in fig. 1, and step S14 includes:
step S140, receiving hardware resource demand information sent from a core of a certain system, and inquiring position information corresponding to the hardware resource required by the system according to the mapping relation table;
step S142, sending the location information corresponding to the hardware resource required by the system to the slave core corresponding to the system.
The method comprises the steps that hardware resource demand information sent by a slave core of a certain system is sent to a master core, the master core carries out protocol processing on the hardware resource demand information through a slave process of a corresponding system in the master core, the processed hardware resource demand information is sent to the master process, the master process obtains the hardware resources required by the system according to registration information corresponding to the system in the slave process of the corresponding system, further, position information (including indexes or addresses) of the corresponding hardware resources can be found through the mapping relation table, then the position information is sent to the corresponding slave core after being processed through a protocol of the slave process, and the slave core can call public hardware resources according to the position information.
Fig. 4 is a flowchart illustrating a method for managing hardware resources of a multi-core heterogeneous system according to another embodiment of the present invention, referring to fig. 4, where the difference between the embodiment and the previous embodiment is: after step S14, the method further includes:
step S16, monitoring the running state of each system;
each system has a slave process in a master core and a slave core allocated to the system, wherein the slave process established in the master core is used for protocol processing corresponding to the system (for example, part L3 of a corresponding baseband chip), and the slave process in the slave core mainly refers to specific operation of the system (for example, parts L1 and L2 of a corresponding baseband chip).
And step S18, if the operation of a certain system is detected to be abnormal, recovering all common hardware resources of the system.
If the corresponding slave process in the master core and the slave process of the corresponding slave core are abnormal, all the slave processes of the slave core and the master core under the system to which the slave core belongs are suspended, all the hardware resources of the system are recycled to the resource pool, and then the system is reinitialized and the hardware resources required by the system are redistributed.
The present invention further provides a multi-core heterogeneous system, which includes a master core 100, a slave core (not shown), and common hardware resources (not shown, including but not limited to a network port queue, a counter, a shared memory, an inter-core interrupt, etc.), fig. 5 is a schematic structural diagram of an embodiment of the master core of the multi-core heterogeneous system provided in the present invention, please refer to fig. 5, where the master core 100 includes a hardware resource registration module 10, a hardware resource management module 12, and a hardware resource allocation module 14.
A hardware resource registration module 10, configured to register and register common hardware resources required by operation of each system;
the multi-core heterogeneous system comprises a main core and at least one slave core as the name implies, the number of the slave cores is not limited, the specific number depends on the requirement of a system, and the operating systems operated by the main core and the slave cores are different. The main core runs an operating system supporting multi-process scheduling, so that the hardware resource requirements of various systems can be conveniently registered and registered, and the secondary core runs a light-weight operating system or does not run the operating system, so that the requirements of high performance and low time delay of running of various systems can be conveniently met.
The master core creates a master process, and creates corresponding slave processes according to the system configured by the system, the system is of a single system or a multi-system, correspondingly, the number of the slave processes of the master core is one or more, the slave processes perform protocol processing between the slave cores and the master core corresponding to each system, and register the required hardware resources of each system.
The hardware resource management module 12 is used for reading and managing common hardware resources;
the master process performs read management on the common hardware resources according to a certain rule, and the master process reserves a part of the hardware resources for the transmission of normal data (including request messages, response messages and the like) between the master core and the slave core so as to maintain the normal communication requirement between the master core and the slave core and reserve a part of the hardware resources for the operation of the slave core corresponding to each system.
The hardware resource allocation module 14 is configured to receive hardware resource requirement information sent by a slave core of a certain system, and allocate a common hardware resource required by operation of the system to a corresponding slave core according to registration information corresponding to the system.
The method comprises the steps that a master process waits for hardware resource demand messages sent by slave cores of all modes, hardware resource demand information sent by the slave cores of a certain system is sent to the master core, the master core carries out protocol processing on the hardware resource demand information through the slave processes of the corresponding systems in the master core, the processed hardware resource demand information is sent to the master process, the master process obtains hardware resources required by the systems according to registration information corresponding to the systems in the slave processes of the corresponding systems, and the hardware resources required by operation of the systems are distributed to the corresponding slave cores.
Further, referring to fig. 6, fig. 6 is a schematic structural diagram of a hardware resource management module of the main core in fig. 5, where the hardware resource management module 12 includes a hardware resource reservation unit 120 and a hardware resource list unit 122:
a hardware resource reservation unit 120, configured to reserve a common hardware resource required for data transmission between the master core and the slave core;
and a hardware resource list unit 122, configured to arrange the remaining common hardware resources in a mapping relationship table, where the mapping relationship table includes the type, size, and location information of the common hardware resources.
In view of the above, the common hardware resources required for data transmission between the master core and the slave core need to be reserved first, and the remaining common hardware resources are arranged in a mapping relationship table form and used as common hardware resources, i.e., a resource pool, when the slave core operates corresponding to each system, where the mapping relationship table should include the type, size, and location (including an index or an address) of each hardware resource.
Further, referring to fig. 7, fig. 7 is a schematic structural diagram of a hardware resource allocation module of the primary core in fig. 5, where the hardware resource allocation module includes a hardware resource query unit 140 and a hardware resource delivery unit 142:
the hardware resource query sheet 140 is used for receiving the hardware resource demand information sent from the slave core of a certain system, and querying the position information corresponding to the hardware resource required by the system according to the mapping relation table;
the hardware resource delivery unit 142 is configured to send location information corresponding to the hardware resource required by the system to the slave core corresponding to the system.
The method comprises the steps that hardware resource demand information sent by a slave core of a certain system is sent to a master core, the master core carries out protocol processing on the hardware resource demand information through a slave process of a corresponding system in the master core, the processed hardware resource demand information is sent to the master process, the master process obtains the hardware resources required by the system according to registration information corresponding to the system in the slave process of the corresponding system, further, position information (including indexes or addresses) of the corresponding hardware resources can be found through the mapping relation table, then the position information is sent to the corresponding slave core after being processed through a protocol of the slave process, and the slave core can call public hardware resources according to the position information.
Fig. 8 is a schematic structural diagram of a main core of a multi-core heterogeneous system according to another embodiment of the present invention, please refer to fig. 8, which is different from the previous embodiment in that: the main core further includes a standard operation monitoring module 16 and a hardware resource recycling module 18:
the system operation monitoring module 16 detects the operation state of each system;
each system has a slave process in a master core and a slave core allocated to the system, wherein the slave process established in the master core is used for protocol processing corresponding to the system (for example, part L3 of a corresponding baseband chip), and the slave process in the slave core mainly refers to specific operation of the system (for example, parts L1 and L2 of a corresponding baseband chip).
And the hardware resource recycling module 18 is used for recycling all hardware resources of a certain system if the operation of the system is monitored to be abnormal.
If the corresponding slave process in the master core and the slave process of the corresponding slave core are abnormal, all the slave processes of the slave core and the master core under the system to which the slave core belongs are suspended, all the hardware resources of the system are recycled to the resource pool, and then the system is reinitialized and the hardware resources required by the system are redistributed.
Further, the multi-core heterogeneous system may be a multi-core heterogeneous system of a base station, for example, a multi-core heterogeneous baseband chip of a wireless base station, or a multi-core heterogeneous radio frequency chip of a wireless base station, and of course, the multi-core heterogeneous system is not limited thereto, and may also be a multi-core heterogeneous chip of other communication devices. The following description will be made for further details of the multi-core heterogeneous system in the embodiment of fig. 8 by taking a baseband chip of a base station as an example:
fig. 9 is a schematic structural diagram of a multi-core heterogeneous system applied to a base station system according to an embodiment of the present invention, fig. 10 is a schematic structural diagram of the multi-core heterogeneous system of fig. 9, please refer to fig. 9 and fig. 10, which are specifically described below by taking the multi-core heterogeneous system of the base station as an example, where the multi-core heterogeneous system adopts a main core of the multi-core heterogeneous system in the embodiment of fig. 8:
the SOC new generation baseband chip based on AMP has strong processing capability, each chip has N cores, in a multi-system site containing UMTS and GSM, under partial scenes, a single chip of the new generation baseband chip can simultaneously support two systems of UMTS and GSM under one base station, and in order to fully utilize the capability of hardware, each baseband chip is planned to run both the UMTS and GSM systems.
As shown in fig. 9, the master core runs on a linux multiprocess operating system, and creates three processes, one master process, a slave process 1 (mainly responsible for UMTS system protocol processing) corresponding to a UMTS system, and a slave process 2 (mainly responsible for GSM system protocol processing) corresponding to a GSM system; the slave core runs on a lightweight LWOS operating system, the slave core runs a lightweight task, the slave cores 1-M are used for deploying UMTS services according to resource requirements, and the slave cores M + 1-N are used for deploying GSM services.
As shown in fig. 10, a master process of a master core is split into a hardware resource allocation module (simply referred to as an allocation module in fig. 10) and a system operation monitoring module (simply referred to as a monitoring module in fig. 10), a slave process 1 of the master core is split into a UMTS base station service (L3) and a hardware resource registration module (simply referred to as registration in fig. 10) required by a UMTS system, a slave process 2 is split into a GSM base station service (L3) and a hardware resource registration module (simply referred to as registration in fig. 10) required by a UMTS system, the slave cores 1 to M are split into UMTS base station service (L1\ L2) modules, and the slave cores M +1 to N are split into UMTS base station service (L1\ L2) modules. The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the claims, and all equivalent structures or equivalent flow transformations that may be embodied in the present specification and drawings and applied directly or indirectly to other related arts are intended to be encompassed by the present invention.
Claims (8)
1. A management method for hardware resources of a multi-core heterogeneous system is characterized by comprising the following steps:
the method comprises the following steps that a main core loads common hardware resources required by the operation of each communication system;
the master core receives the hardware resource demand information sent by the slave core corresponding to a certain system,
distributing the common hardware resources required by the operation of the system to the corresponding slave cores according to the registration information corresponding to the system;
the method comprises the following steps that a common hardware resource required for data transmission between a master core and a slave core is reserved in the master core;
arranging the rest common hardware resources in a mapping relation table form, wherein the mapping relation table comprises the type, the size and the position information of the common hardware resources.
2. The method of claim 1, wherein the multi-core heterogeneous system is a multi-core heterogeneous system of a base station.
3. The method as claimed in claim 1, wherein after the step of receiving the hardware resource requirement information sent by the slave core of a certain system and allocating the common hardware resource required for the operation of the system to the corresponding slave core according to the registration information corresponding to the system, the method further comprises:
monitoring the running state of each system;
and if the operation of a certain system is monitored to be abnormal, recovering the common hardware resource corresponding to the system.
4. The method as claimed in claim 1, wherein the step of receiving the hardware resource requirement information of a certain standard sent from the core includes:
inquiring the position information corresponding to the common hardware resource required by the system according to the mapping relation table;
the step of allocating the common hardware resource required by the operation of the system to the corresponding slave core according to the registration information corresponding to the system comprises the following steps: and sending the position information corresponding to the common hardware resource required by the system to the slave core corresponding to the system.
5. A multi-core heterogeneous system comprising a master core, a slave core, and common hardware resources, wherein the master core comprises:
the hardware resource registration module is used for registering and registering common hardware resources required by the operation of each system;
the hardware resource management module is used for reading and managing the common hardware resources;
the hardware resource allocation module is used for receiving hardware resource demand information sent by a slave core of a certain system and allocating common hardware resources required by the operation of the system to corresponding slave cores according to registration information corresponding to the system;
wherein the hardware resource management module comprises:
the hardware resource reservation unit is used for reserving common hardware resources required by data transmission between the master core and the slave core;
and the hardware resource list unit is used for arranging the rest common hardware resources in a mapping relation table form, and the mapping relation table comprises the types, the sizes and the position information of the common hardware resources.
6. The multi-core heterogeneous system of claim 5, wherein the multi-core heterogeneous system is a multi-core heterogeneous system of a base station.
7. The multi-core heterogeneous system of claim 5, wherein the primary core further comprises:
the system operation monitoring module is used for detecting the operation state of each system;
and the hardware resource recovery module is used for recovering all common hardware resources of a certain system if the operation of the system is monitored to be abnormal.
8. The multi-core heterogeneous system of claim 5, wherein the hardware resource allocation module comprises:
the hardware resource query unit is used for receiving the hardware resource demand information sent from the slave core of a certain system and querying the position information corresponding to the public hardware resource required by the system according to the mapping relation table;
and the hardware resource transmission unit is used for transmitting the position information corresponding to the common hardware resource required by the system to the slave core corresponding to the system.
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| PCT/CN2016/107744 WO2017114061A1 (en) | 2015-12-28 | 2016-11-29 | Asymmetric multiprocessing system and method for managing hardware resource thereof |
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| CN110069287B (en) * | 2018-01-24 | 2022-04-15 | 合肥杰发科技有限公司 | Multi-system coexistence method and device and storage equipment |
| CN111427814B (en) * | 2020-03-05 | 2021-12-07 | 深圳震有科技股份有限公司 | Inter-core communication method based on AMP system, terminal and storage medium |
| CN111767148B (en) * | 2020-06-29 | 2022-03-01 | 中国电子科技集团公司第五十四研究所 | Embedded system resource management method based on multi-core DSP |
| CN112068955B (en) * | 2020-08-21 | 2023-10-27 | 北京科技大学 | Communication optimization method in heterogeneous multi-core platform processor and electronic equipment |
| CN112395242B (en) * | 2020-11-30 | 2024-01-30 | 重庆紫光华山智安科技有限公司 | Multi-chip control method, device, electronic equipment and computer readable storage medium |
| CN112559190B (en) * | 2020-12-23 | 2022-01-11 | 科东(广州)软件科技有限公司 | Resource allocation method, system, device, equipment and medium among heterogeneous systems |
| CN113778936A (en) * | 2021-08-17 | 2021-12-10 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Performance optimization method of domestic embedded DSP operating system |
| CN115952004B (en) * | 2023-02-17 | 2023-05-26 | 上海励驰半导体有限公司 | Resource allocation method, device, electronic equipment and storage medium |
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| WO2015116180A1 (en) * | 2014-01-31 | 2015-08-06 | Hewlett-Packard Development Company, L.P. | Functional unit promotion to management unit |
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| CN100570566C (en) * | 2007-12-13 | 2009-12-16 | 中兴通讯股份有限公司 | The method of coordinated scheduling and heterogeneous multi-core system between a kind of heterogeneous polynuclear |
| JP6171658B2 (en) * | 2013-07-19 | 2017-08-02 | 富士通株式会社 | Parallel processing optimization program, parallel processing optimization method, and information processing apparatus |
| CN104461716B (en) * | 2014-12-29 | 2018-06-15 | 迈普通信技术股份有限公司 | The access method and multi-core heterogeneous system of a kind of multi-core heterogeneous system |
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| CN101126990A (en) * | 2006-08-18 | 2008-02-20 | 英业达股份有限公司 | Multiple-core multi-CPU threading dispatch execution method based on hardware resource |
| CN102299938A (en) * | 2010-06-23 | 2011-12-28 | 中兴通讯股份有限公司 | Method and device for realizing multicore and multisystem unified platform |
| CN102438338A (en) * | 2011-12-14 | 2012-05-02 | 北京邮电大学 | Base station based on multicore general processor for broadband mobile communication system |
| WO2015116180A1 (en) * | 2014-01-31 | 2015-08-06 | Hewlett-Packard Development Company, L.P. | Functional unit promotion to management unit |
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