CN106919216A - A kind of unclonable circuit of physics based on Cascode current-mirror structures - Google Patents
A kind of unclonable circuit of physics based on Cascode current-mirror structures Download PDFInfo
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
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Abstract
The invention discloses a kind of unclonable circuit of the physics based on Cascode current-mirror structures, including PMOS current mirroring circuits and Cascode current mirroring circuits, the input of PMOS current mirroring circuits connects the input of Cascode current mirroring circuits by reference current source, the output end of Cascode current mirroring circuits as the unclonable circuit of the physics output end；Cascode current mirroring circuits include NMOS current lens arrays, by being addressed operation to NMOS current lens array address wires, a NMOS tube in NMOS current lens arrays are opened every time, make Cascode current mirroring circuit output currents；When the electric current of PMOS current mirroring circuits output is more than the electric current that Cascode current mirroring circuits are exported, the unclonable circuit output high level of physics, conversely, the unclonable circuit output low level of physics；Once after the completion of complete addressing operation, physics one low and high level disorder distribution of unclonable circuit output, be convertible into the voltage waveform of binary signal sequence.The chip area of product of the present invention is smaller, power consumption is relatively low.
Description
[technical field]
The present invention relates to information security field, more particularly to a kind of physics based on Cascode current-mirror structures can not gram
Grand circuit.
[background technology]
Physics unclonable function (Physical Unclonable Funtion:PUF refer to) by defeated to physical entity
Enter an excitation, the physical chemical differences certainly existed using it export a function for uncertain random response.
The method that PUF structures can realize PUF functions, has：1. output response is unpredictable, 2. prevent distorting, 3. unclonable, 4.
Robustness, 5. several important features such as light weight level characteristics, make its realize certification, password protection and hardware security protection etc. field have
Advantageous advantage.
PUF concepts are applied to entity authentication at first, and through development in a few years, it pacifies in the generation of such as key, gate control system etc.
The application in full field is also gradually being promoted.Modern times carry developing rapidly and popularizing for the intelligent artifact of personally identifiable information so that
Ensure that the information that these products are carried is not stolen particularly important easily.With the miniaturization of intelligent artifact, traditional causes portion
Divide device excessive or consume the more more ripe cipher code protection method of resource and be no longer applicable, the light weight level characteristics of exactly PUF, order
It has huge development potentiality in the equipment such as RFID, sensor network nodes.
According to the difference in the field for realizing PUF functions, there is analog circuit PUF to realize in the implementation method of electrical type PUF
Method and digital circuit PUF implementation methods.Analog circuit PUF realizes that technique becomes i.e. in the generation manufacture of Analogous Integrated Electronic Circuits
There is the fine error for being difficult prediction and eliminating, these fine differences in the different transistor parameter for causing to have same size in circuit
A uncertain characteristic random response with PUF is just can obtain by corresponding treatment；Digital circuit PUF is realized often
For producing key, its security performance is higher than analog circuit PUF, but its cost and requirement are also higher.
Due to the transistor sub-threshold voltage error that process deviation is caused when proposing to be manufactured using transistor in document [3],
Output response is waited until by the addressing operation to phase inverter array circuit, analog processing unit and an output ratio is eventually passed
The output with PUF characteristics is obtained compared with device to respond.The realization of this circuit introduces correcting circuit, though reduce the error code of circuit
Rate, makes the job stability of circuit increase, but considerably increases the power consumption and chip area of circuit simultaneously.Wherein,
The power consumption of circuit reaches 38 μ W, and circuit area is up to 35000 μm2。
Using single amplifier array to exporting what is responded due to what technological parameter deviation was produced in transistor in document [4]
Fine difference is amplified, and the NMOS tube in array uses the minimum dimension under 0.18 micron nominal CMOS technology, to increase work
The influence that skill makes a variation to transistor parameter so that the circuit response of output has unpredictable characteristic higher and unclonable spy
Property.But, because the circuit has used automatic zero adjustment comparator, bulky capacitor is introduced, cause circuit area to increase, and reduce
The operating rate of circuit.
A kind of PUF circuits based on Arbiter structures are proposed in document [5].Same data signal be make use of at two
To an identical destination, two signals for setting out together prolong different propagateds due to the different transmission that propagation path is produced
Late, the time for arriving at is incomplete same, the priority for then being reached according to signal by Arbiter structures, accordingly defeated
Go out the response of a logical zero or logical one.Such as one rising signals are propagated by upper and lower two paths respectively, if top
Path first travels to moderator, then output response is " 1 ", otherwise output response is " 0 ".So by a series of rising of input
Dropping signal, just can obtain a string corresponding binary sequences as response.Because the foundation of Arbiter needs the time, institute
So that the stability of the circuit can be caused not high.
The Butterfly PUF structures proposed in document [6] then make use of the stochastic regime of cross-coupled circuit to convert.Hand over
Fork termination power in positive feedback circle exist " 0 " and " 1 " two stable states, and one it is unstable and be easy to two stable states it
The characteristic of the intermediate state of one transformation.Two latch cross-couplings form a positive feedback loop, and extrinsic motivated letter is controlled first
Number circuit is set to play pendulum, then changing the pumping signal makes one of circuit from labile state into two stable states
Conversion, so as to obtain the binary digit of " 0 " or " 1 ".An array is constituted using cross-coupled circuit as multiple, most
A string of the output of binary sequence can be obtained eventually.Because the conversion of labile state is highly susceptible to one in cross-coupled circuit
The influence of the uncertain factor of a little circuits or device, so this transfer process is uncertain, therefore a string for finally giving
Binary sequence is also unique and uncertain.But the circuit equally exists the problem of stability to be calculated, it is necessary to pass through auxiliary
Method circuit improves its stability.
These PUF proposed in document above realize circuit, the problem that generally existing chip area is larger, power consumption is higher,
Circuit stability is also one problem to be solved, exist optimization on the one hand can but sacrifice on the other hand phenomenon (such as in order to
Improve stability and have to increase power consumption and chip area), these shortcomings limit PUF chips in reality to a certain extent
In application.
[content of the invention]
The technical problem to be solved in the present invention is to provide that a kind of chip area is smaller, power consumption is relatively low based on Cascode electricity
Flow the unclonable circuit of physics of mirror structure.
In order to solve the above-mentioned technical problem, the technical solution adopted by the present invention is that one kind is based on Cascode current-mirror structures
The unclonable circuit of physics, including PMOS current mirroring circuits and Cascode current mirroring circuits, the input of PMOS current mirroring circuits
End connects the input of Cascode current mirroring circuits, output end and the Cascode electricity of PMOS current mirroring circuits by reference current source
As the output end of the unclonable circuit of the physics after the output end connection of current mirror circuit；Cascode current mirroring circuits include
NMOS current lens arrays, by being addressed operation to NMOS current lens array address wires, open NMOS current lens arrays every time
In a NMOS tube, make Cascode current mirroring circuit output currents；When the electric current of PMOS current mirroring circuits output is more than
During the electric current of Cascode current mirroring circuits output, the unclonable circuit output high level of described physics, conversely, physics can not
Clone's circuit output low level；Once after the completion of complete addressing operation, the unclonable circuit output of described physics one is high
Low level disorder distribution, be convertible into the voltage waveform of binary signal sequence.
The above-described unclonable circuit of physics, PMOS current mirroring circuits include two PMOSs, two PMOSs
Source electrode connects power supply, and the grid of two PMOSs links together, and connects the drain electrode of the first PMOS；The drain electrode of the first PMOS is made
For the input of PMOS current mirroring circuits connects the input of Cascode current mirroring circuits, second by described reference current source
The drain electrode of PMOS terminates the output end of Cascode current mirroring circuits as the output of PMOS current mirroring circuits.
The above-described unclonable circuit of physics, NMOS current lens arrays include M root row address lines, N roots column address conductor,
M rows N row NMOS tube and NMOS tube quantity identical row switch and M row switch, the grid of NMOS current lens arrays whole NMOS tube
Extremely it is connected, connects additional control voltage；The source electrode of whole NMOS tubes is connected and is grounded；The drain electrode of each NMOS tube passes through corresponding row
Switch connects the input of every trade switch；The control of same row row switch terminates the column address conductor of the row, the control end of row switch
The row address line of the row is connect, the output end of all row switches is connected, used as the output end of NMOS current lens arrays.
The above-described unclonable circuit of physics, Cascode current mirroring circuits include the 3rd NMOS tube, the 4th NMOS
Pipe, the 5th NMOS tube and described NMOS current lens arrays, the drain electrode of the 3rd NMOS tube is used as the defeated of Cascode current mirroring circuits
Enter the input that end connects PMOS current mirroring circuits by described reference current source, source electrode connects the drain electrode of the 5th NMOS tube, the
The source ground of five NMOS tubes；The drain electrode of the 4th NMOS tube terminates PMOS current mirrors as the output of Cascode current mirroring circuits
The output end of circuit, source electrode connects the output end of NMOS current lens arrays；The grid of the 3rd NMOS tube connects the grid of the 4th NMOS tube,
And connect the drain electrode of the 3rd NMOS tube；The grid of the 5th NMOS tube connects the drain electrode of the 5th NMOS tube, and it is complete to connect NMOS current lens arrays
The grid of portion's NMOS tube.
The above-described unclonable circuit of physics, including output buffer, output buffer connect the physics not
Circuit output end can be cloned.
The above-described unclonable circuit of physics, debugging process is comprised the following steps：
601st, before the unclonable circuit work of physics, a NMOS tube work of the described NMOS current lens arrays of any selection
Make, the output current of Cascode current mirroring circuits is adjusted by the size for adjusting the 5th NMOS tube, make Cascode current mirrors electricity
The output current on road is substantially equal to the output current of PMOS current mirroring circuits；
602nd, the size of adjustment circuit transistor, makes the low level of the unclonable circuit output of physics and the high level of output
The ratio of appearance is 1：1.
Physics unclonable circuit product of the present invention based on Cascode current-mirror structures chip area is smaller, power consumption
It is relatively low.
[brief description of the drawings]
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description.
Fig. 1 is the system architecture diagram of the unclonable circuit of embodiment of the present invention physics.
Fig. 2 is the PMOS current mirroring circuit structure charts of the unclonable circuit of embodiment of the present invention physics.
Fig. 3 a are basic NMOS current mirroring circuits structure charts.
Fig. 3 b are embodiment of the present invention Cascode current mirroring circuit structure charts.
Fig. 4 a are embodiment of the present invention array element circuit structure diagrams.
Fig. 4 b are embodiment of the present invention NMOS current lens array circuit structure diagrams.
Fig. 5 is the unclonable circuit integrated circuit structure chart of embodiment of the present invention physics.
Fig. 6 is 0,1 distribution proportion figure of the unclonable circuit output ID sequences of embodiment of the present invention physics.
Fig. 7 is the unclonable circuit temperature of embodiment of the present invention physics and influence figure of the voltage change to the circuit bit error rate.
Fig. 8 is the intersymbol Hamming distance distribution map of the unclonable circuit output of embodiment of the present invention physics.
Fig. 9 is the power consumption diagram of the unclonable circuit of embodiment of the present invention physics.
Figure 10 is the overall domain of the unclonable circuit of embodiment of the present invention physics.
[specific embodiment]
The present invention based on Cascode current-mirror structures the unclonable circuit of physics, including PMOS current mirroring circuits and
Cascode current mirroring circuits, the power input termination power supply of PMOS current mirroring circuits, the input of PMOS current mirroring circuits passes through
Reference current source connects the input of Cascode current mirroring circuits, and both use same reference current as input.PMOS electric currents
The output end of mirror circuit be connected with the output end of Cascode current mirroring circuits after as the unclonable circuit of the physics output
End；Cascode current mirroring circuits include NMOS current lens arrays, by being addressed behaviour to NMOS current lens array address wires
Make, a NMOS tube in NMOS current lens arrays is opened every time, make Cascode current mirroring circuit output currents；When PMOS electricity
When the electric current of current mirror circuit output is more than the electric current that Cascode current mirroring circuits are exported, the unclonable circuit of described physics is defeated
Go out high level, conversely, the unclonable circuit output low level of physics；Once after the completion of complete addressing operation, described physics
One voltage waveform of low and high level disorder distribution of unclonable circuit output, is convertible into corresponding binary signal sequence
Row.
Wherein, PMOS current mirroring circuits include two PMOSs, and the source electrode of two PMOSs connects power supply, the first PMOS
Grid links together with the grid of the second PMOS, and connects the drain electrode of the first PMOS；The drain electrode of the first PMOS is used as defeated
Enter the input that end connects Cascode current mirroring circuits by reference current source, the drain electrode of the second PMOS is used as PMOS current mirrors
The output end of the output termination Cascode current mirroring circuits of circuit.
NMOS current lens arrays include M root row address lines, N roots column address conductor, M rows N row NMOS tube and NMOS tube quantity phase
Same row switch and M row switch, the grid of NMOS current lens arrays whole NMOS tubes is connected, connects additional control voltage；All
The source electrode of NMOS tube is connected and is grounded；The drain electrode of each NMOS tube connects the input that the every trade is switched by corresponding row switch；
The control of same row row switch terminates the column address conductor of the row, and the control of row switch terminates the row address line of the row, and all rows are opened
The output end of pass is connected, used as the output end of NMOS current lens arrays.
Cascode current mirroring circuits include the 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube and described NMOS electric currents
Lens array, the drain electrode of the 3rd NMOS tube connects PMOS electric currents as the input of Cascode current mirroring circuits by reference current source
The input of mirror circuit, source electrode connects the drain electrode of the 5th NMOS tube, the source ground of the 5th NMOS tube；The drain electrode of the 4th NMOS tube is made
It is the output end of the output termination PMOS current mirroring circuits of Cascode current mirroring circuits, source electrode connects the defeated of NMOS current lens arrays
Go out end；The grid of the 3rd NMOS tube connects the grid of the 4th NMOS tube, and connects the drain electrode of the 3rd NMOS tube；The grid of the 5th NMOS tube
The drain electrode of the 5th NMOS tube is connect, and connects the grid of NMOS current lens arrays whole NMOS tube.
The embodiment of the present invention proposes that the super low-power consumption PUF with Cascode (cascade) current-mirror structure as core is realized
Circuit.By optimizing circuit structure, while circuit reliability, stability is ensured, circuit low-power consumption, low cost, small is realized
The target of area so that the PUF circuits can be widely used in real life.
The system architecture of the PUF circuits of the embodiment of the present invention is as shown in figure 1, by PMOS current mirroring circuits, Cascode electric currents
Mirror circuit is constituted, and wherein Cascode current mirroring circuits include a NMOS current lens array.PMOS current mirroring circuits with
Cascode current mirroring circuits use same reference current, and the image current of generation is respectively I1And I2, two mirrors in theory
The difference DELTA I=I of image current1-I2=0, but due to the presence of error, Δ I is not exclusively 0.As Δ I ＞ 0, output node electricity
Pressure will be raised to supply voltage；As Δ I ＜ 0, output node voltage will be pulled low to ground.When circuit works, NMOS
Current lens array address wire is addressed operation, often selects a NMOS tube all to obtain an image current I2, now Δ I
Value be unpredictable, according to the difference of Δ I, output node exports a corresponding voltage.In NMOS current lens arrays one
After the completion of secondary complete addressing operation, the output voltage that will be obtained is converted into the sequence of binary system i.e. a string 0 and 1 random distribution,
This sequence is using as the output of whole PUF circuits.
As shown in Fig. 2 PMOS current mirrors are by two PMOS M1And M2Composition, wherein M1It is M2Biasing, I are providedREFIt is base
Quasi- electric current.Assuming that PMOS M in circuit1And M2All it is operated in subthreshold region (0<VGS<VTH), due to M1And M2Size is larger can
Ignore channel-length modulation, in theory, when assuming that transistor M1And M2With other are complete in addition to breadth length ratio (W/L) is unequal
Exactly the same design parameter is (such as：Mobility [mu]p, unit area gate oxide capacitance Cox, threshold voltage VTHDeng) when, can obtainThe formula shows, to the current-mirror structure shown in Fig. 2, can be by setting PMOS M1And M2Width is long
The ratio of ratio, obtains and reference current IREFProportional image current I1.As (W/L)2=(W/L)1When, I1=IREF.And in reality
In the manufacture of border technique, due to the change such as temperature change present in manufacturing process is uneven, doping concentration is uneven so that even if
It is two transistors with identical layout design, its device parameters each other can all have subtle difference, that is, anticipate
Taste current differential Δ I=IREF-I1≠0.Because Δ I is relevant with process variation, so its symbol is also unpredictable.
As shown in figure 3, Fig. 3 a are a fundamental current mirror circuit structure being made up of two NMOS tubes, current mirror work
Principle is identical with above-mentioned PMOS current mirrors operation principle, is operated in the circuit formula of subthreshold region and the phase of PMOS current mirrors
Seemingly, correspondence NMOS tube carrier mobility is μn。MbiasIt is MmirBias voltage V is providedg, the I=I exported under ideal conditionsREF。
Fig. 3 b are the Cascode current mirroring circuit structures that the present invention is used, and the structure is improved on the basis of a is schemed.Circuit work
When making, reference current IREFFlow through M3And M5, respectively M4And M6Bias voltage, V are providedG1In M6Produce image current I2, switch
Key is closed, VGSo that I2It is able to by M4Output.Structure shown in Fig. 3 a is compared to, Fig. 3 b are due to M3And M4Presence, greatly
The output impedance of circuit structure is improve, and the raising of circuit output impedance reduces image current I2To Δ VG1Sensitiveness,
Even if occurring larger Δ V in circuitG1, image current I2Also output can relatively be stablized.
Fig. 4 illustrates NMOS current mirroring circuit structures.Fig. 4 a are an elementary cell of array, MkeyAs nmos switch
Pipe, can control M by control input signal keyMNThe output of the electric current I of upper generation.Fig. 4 b are the circuit structure of array, BL1~
BLNRepresent N bar column output lines, WL1~WLMM bar row output lines are represented, column address conductor and row address line (not shown) are distinguished
Respective column switch and row is controlled to switch on and turn off.All other NMOS in circuit in addition to row, column nmos switch pipe
Pipe source ground, grid are connected and connect bias voltage Vg, drain electrode be connected with respective column nmos switch pipe.Given array grid voltage Vg,
Only after the corresponding row switch of certain NMOS tube and row switch are opened simultaneously, the NMOS tube is selected, and is produced between its source and drain
Electric current as array output current.
Fig. 5 is the circuit structure of whole PUF circuits.Fig. 3 bCascode are replaced using NMOS current lens arrays shown in Fig. 4 b
M in current mirroring circuit in dotted line frame6With switch key, the size of all NMOS tubes is all NMOS tube under 65nm techniques in array
The minimum dimension that can be reached, two phase inverters provide buffering for circuit output.PMOS current mirroring circuits and Cascode current mirrors electricity
Road is input into same reference current, and PMOS current mirrors output image current is I1, Cascode current mirrors output image current is I2.
Before circuit work, the switching tube work of any selection array, by adjusting NMOS tube M5Size regulation array output electricity
Stream I2Value, make I1≈I2.After circuit is started working, by controlling the row, column address wire of NMOS arrays to NMOS current lens arrays
It is addressed, a NMOS tube in array is chosen every time, and Cascode current mirrors will all produce an output current I2, so that
A difference between current Δ I can be obtained.Circuit state from it is unstable switch to stabilization during, Δ I will be to output node
Node carries out charge or discharge.During charging, the voltage of output node node will be increased to Vdd；During electric discharge, output node node
Place's voltage will be pulled low to ground.After each charge or discharge, the voltage at node node is all by two bufferings of phase inverter
Circuit is exported.In this way, after the completion of to NMOS current lens arrays once complete continuous addressing operation, output node node
The output at place would is that a contact potential series for continuous low and high level position random distribution.By adjusting the 3rd NMOS tube, the
The ratio that the size of four NMOS tubes and the 5th NMOS tube can adjust low and high level appearance in contact potential series is 1：1.Wherein the 3rd
NMOS tube is identical with the size of the 4th NMOS tube to be converted to binary sequence the output voltage sequence, just can obtain a string of phases
The binary sequence of 0,1 random distribution answered, the sequence is the output ID sequences of PUF circuits.
The PUF circuits that the embodiment of the present invention is proposed are based on UMC 65nm techniques, under conditions of operating voltage is 1.2V, lead to
Monte-Carlo Simulation is crossed, obtaining the power consumption of the PUF circuits can reach 0.128 μ W, and energy consumption is 0.392PJ/bit, core circuit face
Product is 1400 μm2, with high reliability and low-power consumption, service behaviour is more excellent, and circuit arrangement feasibility is very high.
Fig. 6 is shown by the getable PUF output voltages sequence of Monte-Carlo Simulation work(of circuit design software Cadence
Row high-low voltage proportion distribution map, top half is voltage's distribiuting when circuit output is buffered without inverter circuit,
ShiShimonoseki part is that circuit output is distributed by the output voltage after inverter circuit buffering, and by the output voltage after phase inverter
High-low voltage distribution proportion is close to 1：1, the output 0,1 for belonging to ideal is distributed.
The embodiment of the present invention uses the smallest crystals pipe size that can be reached under UMC65nm techniques, the test knot of the bit error rate
Fruit is as shown in fig. 7, each ber curve represents an operating voltage for circuit.Reliability is under worst condition of work
94.14%, and under normal running conditions, the circuit bit error rate is less than 2.0%, represents the high reliability of the work of this PUF circuits.
The embodiment of the present invention uses a NMOS current lens array for M × N=16 × 16, exports the digit of ID sequences
It it is 256, its uniqueness is to carry out normalizing by simulating the Hamming distance of the output ID of PUF chip entities to one group of any two
Change treatment obtain, as a result as shown in figure 8, μ=0.4954, σ=0.0075 (wherein, the ideal values of mean μ be 0.5, standard deviation
The ideal values of σ represent the good uniqueness of the PUF circuit outputs of the embodiment of the present invention for result 0).
Fig. 9 is the power consumption analysis result of the embodiment of the present invention, using the power consumption of circuit average operating current characterization circuit, is led to
Cross the average power consumption as little as 0.128 μ W that emulation obtains circuit.Following table is its in embodiment of the present invention PUF circuits and bibliography
Its some PUF realizes the performance comparison of circuit, the performance of embodiment of the present invention PUF circuits in terms of uniqueness, reliability with text
The PUF circuits offered hardly differ, but in terms of power consumption, specific energy consumption in circuit in contrast to some other circuit have one compared with
Big raising, and the area of whole circuit chip there has also been and be greatly reduced.
Because the embodiment of the present invention is to carry out whole design and simulation work based on UMC65nm techniques, therefore in circuit layout
In it can be seen that circuit another advantage be circuit total area very little.It is used for the displacement of NMOS array address without addition
During the circuit of register, the total area of circuit is 1400 μm2Even if, after adding shift-register circuit, circuit it is total
Also only 2500 μm of bulk area2。
The contrast table of the embodiment of the present invention and prior art circuits performance：
Bibliography
[1] Zhang Zinan, Guo Yuanbo, " physics unclonable function summary ", computer application, 32 (11), 3115-3120,
2012.
[2]Pappu R.S,“Physical one-way functions”,Massachusetts Institute of
Technology,2001.
[3]S.Stanzione,D.Puntin,and G.Iannaccone,“CMOS Silicon Physical
Unclonable Functions Based on Intrinsic Process Variability”,IEEE Journal of
Solid-State Circuits(ISSC),vol.46,no.6,pp.1456-1463,2011.
[4]S.Lin,X.Zhao,B.Li,X.Pan,“An Ultra-low Power Common-Source-
Amplifier-Based Physical Unclonable Function”,IEEE Conference on Electron
Devices and Solid-State Circuits(EDSSC),pp.269-272,Singapore,2015.
[5]L.Lin,S.Srivathsa,D.K.Krishnappa,P.Shabadi and W.BurlesonLang,
“Design and validation of Arbiter-Based PUFs for Sub-45-nm Low-Power Security
Applications”,IEEE Transactions on Information Forensics and Security,vol.7,
no.4,pp.1394-1403,2012.
[6]S.S.Kumar,J.Guajardo,R.Maes,G.J.Schrijen and P.Tuyls,“The
butterfly PUF protecting IP on every FPGA”,IEEE International Workshop on
Hardware-Oriented Security and Trust(HOST),pp.67-70,2008.
[7]K.Lofstrom,W.R.Daasch,and D.Taylor,“IC identification circuit
using device mismatch,”IEEE International Solid-State Circuits Conference.
(ISSCC),pp.372-373,2000.
[8]M.Kalyanaraman and M.Orshansky,“Novel strong PUF based on
nonlinearity of MOSFET subthreshold operation,”IEEE Sym.on Hardware-Oriented
Security and Trust(HOST),pp.13-18,2013.
[9]S.K.Mathew,S.K.Satpathy,M.A.Anders,H.Kaul,S.K.Hsu,A.Agarwal,et al,
“A 0.19pJ/b PVT-Variation-Tolerant Hybrid Physically Unclonable Function
Circuit for 100%Stable Secure Key Generation in 22nm CMOS " IEEE International
Solid-State Circuits Conf.(ISSCC),pp.278-279,2014.
[10]Y.Cao,L.Zhang,C.H.Chang,S.S.Chen,“A Low-Power Hybrid RO PUF With
Improved Thermal Stability for Lightweight Applications”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(TCAD),pp.1143-1147,
2015.
[11]C.Bai,X.C.Zou,K.Dai,”A Novel Thyristor-Based Silicon Physical
Unclonable Function”IEEE Transactions on Very Large Scale Integration (VLSI) Systems,pp.290-300,2015。
Claims (6)
1. the unclonable circuit of a kind of physics based on Cascode current-mirror structures, it is characterised in that including PMOS current mirrors electricity
Road and Cascode current mirroring circuits, the input of PMOS current mirroring circuits connect Cascode current mirroring circuits by reference current source
Input, the output end of PMOS current mirroring circuits be connected with the output end of Cascode current mirroring circuits after as the physics
The output end of unclonable circuit；Cascode current mirroring circuits include NMOS current lens arrays, by NMOS current lens arrays
Address wire is addressed operation, and a NMOS tube in NMOS current lens arrays is opened every time, makes Cascode current mirroring circuits defeated
Go out electric current；When the electric current of PMOS current mirroring circuits output is more than the electric current that Cascode current mirroring circuits are exported, described physics
Unclonable circuit output high level, conversely, the unclonable circuit output low level of physics；Once complete addressing operation is completed
Afterwards, one low and high level disorder distribution of the unclonable circuit output of described physics, be convertible into binary signal sequence
Voltage waveform.
2. the unclonable circuit of physics according to claim 1, it is characterised in that PMOS current mirroring circuits include two
PMOS, the source electrode of two PMOSs connects power supply, and the grid of two PMOSs links together, and connects the leakage of the first PMOS
Pole；The drain electrode of the first PMOS connects Cascode electricity as the input of PMOS current mirroring circuits by described reference current source
The input of current mirror circuit, the drain electrode of the second PMOS is electric as the output termination Cascode current mirrors of PMOS current mirroring circuits
The output end on road.
3. the unclonable circuit of physics according to claim 1, it is characterised in that NMOS current lens arrays include M root rows
Address wire, N roots column address conductor, M rows N row NMOS tube and NMOS tube quantity identical row switch and M row switch, NMOS electric currents
The grid of lens array whole NMOS tube is connected, and connects additional control voltage；The source electrode of whole NMOS tubes is connected and is grounded；Each NMOS
The drain electrode of pipe connects the input that the every trade is switched by corresponding row switch；The control of same row row switch terminates the row ground of the row
Location line, the control of row switch terminates the row address line of the row, and the output end of all row switches is connected, used as NMOS current lens arrays
Output end.
4. the unclonable circuit of physics according to claim 3, it is characterised in that Cascode current mirroring circuits include the
Three NMOS tubes, the 4th NMOS tube, the 5th NMOS tube and described NMOS current lens arrays, the drain electrode conduct of the 3rd NMOS tube
The input of Cascode current mirroring circuits connects the input of PMOS current mirroring circuits by described reference current source, and source electrode connects
The drain electrode of the 5th NMOS tube, the source ground of the 5th NMOS tube；The drain electrode of the 4th NMOS tube is used as Cascode current mirroring circuits
The output end of output termination PMOS current mirroring circuits, source electrode connects the output end of NMOS current lens arrays；The grid of the 3rd NMOS tube
The grid of the 4th NMOS tube is connect, and connects the drain electrode of the 3rd NMOS tube；The grid of the 5th NMOS tube connects the drain electrode of the 5th NMOS tube, and
Connect the grid of NMOS current lens arrays whole NMOS tube.
5. the unclonable circuit of physics according to claim 1, it is characterised in that including output buffer, output is slow
Rush circuit and connect the unclonable circuit output end of the physics.
6. the unclonable circuit of physics according to claim 4, it is characterised in that debugging process is comprised the following steps：
601st, before the unclonable circuit work of physics, the NMOS tube work of the described NMOS current lens arrays of any selection,
The output current of Cascode current mirroring circuits is adjusted by the size for adjusting the 5th NMOS tube, makes Cascode current mirroring circuits
Output current is substantially equal to the output current of PMOS current mirroring circuits；
602nd, the size of adjustment circuit transistor, makes the low level of the unclonable circuit output of physics occur with the high level of output
Ratio be 1：1.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107766750A (en) * | 2017-11-22 | 2018-03-06 | 河海大学常州校区 | A kind of PUF circuits based on threshold voltage benchmark |
| CN111314058A (en) * | 2018-12-11 | 2020-06-19 | 华邦电子股份有限公司 | Physical unclonable function code generation method and providing device thereof |
| CN112506264A (en) * | 2019-09-13 | 2021-03-16 | 美国亚德诺半导体公司 | Current mirror arrangement with double-base current circulator |
| CN112886931A (en) * | 2021-01-28 | 2021-06-01 | 深圳市万微半导体有限公司 | Digital weighted current source circuit for eliminating offset error of operational amplifier |
| CN113359943A (en) * | 2021-07-22 | 2021-09-07 | 成都利普芯微电子有限公司 | Reference current regulating circuit and reference current generating circuit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102880840A (en) * | 2012-09-25 | 2013-01-16 | 宁波大学 | Current type physical unclonable function circuit for defending attack |
| US20150028847A1 (en) * | 2013-07-29 | 2015-01-29 | Nxp B.V. | Puf method using and circuit having an array of bipolar transistors |
| CN105676942A (en) * | 2016-03-08 | 2016-06-15 | 宁波大学 | Deviation signal producing circuit and multiport configurable PUF circuit |
| CN105760785A (en) * | 2016-01-24 | 2016-07-13 | 深圳大学 | Physical no-cloning chip circuit based on time domain differential current measurement |
| WO2016189070A1 (en) * | 2015-05-27 | 2016-12-01 | Nagravision S.A. | Method for generating a value inherent to an electronic circuit, electronic circuit generating this value and method for using such a value |
-
2017
- 2017-03-01 CN CN201710116797.5A patent/CN106919216A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102880840A (en) * | 2012-09-25 | 2013-01-16 | 宁波大学 | Current type physical unclonable function circuit for defending attack |
| US20150028847A1 (en) * | 2013-07-29 | 2015-01-29 | Nxp B.V. | Puf method using and circuit having an array of bipolar transistors |
| WO2016189070A1 (en) * | 2015-05-27 | 2016-12-01 | Nagravision S.A. | Method for generating a value inherent to an electronic circuit, electronic circuit generating this value and method for using such a value |
| CN105760785A (en) * | 2016-01-24 | 2016-07-13 | 深圳大学 | Physical no-cloning chip circuit based on time domain differential current measurement |
| CN105676942A (en) * | 2016-03-08 | 2016-06-15 | 宁波大学 | Deviation signal producing circuit and multiport configurable PUF circuit |
Non-Patent Citations (1)
| Title |
|---|
| SHIBANG LIN,DEJIAN LIANG,YUAN CAO,XIAOFANG PAN,XIAOJIN ZHAO: "A low power and compact physical unclonable function based on the cascode current mirrors", 《CIRCUITS AND SYSTEMS (APCCAS),2016 IEEE ASIA PACIFIC CONFERENCE ON》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107766750A (en) * | 2017-11-22 | 2018-03-06 | 河海大学常州校区 | A kind of PUF circuits based on threshold voltage benchmark |
| CN111314058A (en) * | 2018-12-11 | 2020-06-19 | 华邦电子股份有限公司 | Physical unclonable function code generation method and providing device thereof |
| CN112506264A (en) * | 2019-09-13 | 2021-03-16 | 美国亚德诺半导体公司 | Current mirror arrangement with double-base current circulator |
| CN112506264B (en) * | 2019-09-13 | 2022-10-04 | 美国亚德诺半导体公司 | Current mirror arrangement with double-base current circulator |
| CN112886931A (en) * | 2021-01-28 | 2021-06-01 | 深圳市万微半导体有限公司 | Digital weighted current source circuit for eliminating offset error of operational amplifier |
| CN113359943A (en) * | 2021-07-22 | 2021-09-07 | 成都利普芯微电子有限公司 | Reference current regulating circuit and reference current generating circuit |
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