CN106910779A - Thin film transistor (TFT), array base palte and preparation method thereof and display device - Google Patents
Thin film transistor (TFT), array base palte and preparation method thereof and display device Download PDFInfo
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- CN106910779A CN106910779A CN201710221676.7A CN201710221676A CN106910779A CN 106910779 A CN106910779 A CN 106910779A CN 201710221676 A CN201710221676 A CN 201710221676A CN 106910779 A CN106910779 A CN 106910779A
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- 239000010409 thin film Substances 0.000 title claims abstract description 65
- 238000002360 preparation method Methods 0.000 title claims abstract description 15
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- 239000011241 protective layer Substances 0.000 claims abstract description 61
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- 239000004065 semiconductor Substances 0.000 claims abstract description 48
- 238000000034 method Methods 0.000 claims description 47
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- 239000000377 silicon dioxide Substances 0.000 description 3
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses thin film transistor (TFT), array base palte and preparation method thereof and display device.The thin film transistor (TFT) includes：Substrate；Grid, the grid is set over the substrate；First insulating barrier, first insulating barrier covers the grid；Semiconductor layer, the semiconductor layer is arranged on side of first insulating barrier away from the grid；Source electrode and drain electrode, the source electrode and drain electrode are separately positioned on side of the semiconductor layer away from first insulating barrier；Second insulating barrier, second insulating barrier covers the source electrode and the drain electrode；And channel region protective layer, the channel region protective layer is arranged on side and with channel region corresponding region of second insulating barrier away from the source electrode and the drain electrode, and projection of the channel region protective layer on the channel region overlaps with the channel region.Thus, channel region protective layer can not receive external environment influence with protection device, while not influenceing the performance of device.
Description
Technical field
The present invention relates to electronic applications, in particular it relates to thin film transistor (TFT), array base palte and preparation method thereof and display dress
Put.
Background technology
In recent years, with the development of semiconductor devices, for large-sized display of the purposes such as outdoor display, meeting displaying
Device is also gradually popularized.Further to improve the performance of display device, oxide technique is widely used and prepares display dress
Put, for example, ITO (indium tin oxide) is used in thin film transistor (TFT) as channel material, so as to improve the resolution of display device
Rate.The resistance of display device is prepared to reduce simultaneously, wire is formed using Cu, using the low resistance of Cu, high conduction performance, carried
The electric property of display device high.
However, current thin film transistor (TFT), array base palte and preparation method thereof and display device, still have much room for improvement.
The content of the invention
The application is that the discovery of following facts is made based on inventor：
Inventor has found, in order to improve the performance of display device, it is common to use transparent conductive material (such as ITO, IGZO (indium
Gallium zinc oxide) etc.) and Cu materials.Due to the particularity of the material so that kinds of processes occurs not in process of producing product
It is good.For example, Cu grids are easy to fall off；When IGZO (indium gallium zinc oxide) is as channel material, the problems such as device stability is reduced.Hair
A person of good sense by further investigation and many experiments find, during this in large display device mainly due to preparing, Cu grids with
Substrate directly contact, because both adhesions are low, easily causes Cu grids easy to fall off；Simultaneously because not having in TFT regions
There is organic insulator, channel region is protected so that thin film transistor (TFT) is by after the process of subsequent technique, stability drops
It is low, influence device performance.
It is contemplated that alleviating at least to some extent or solving above-mentioned referring at least one in problem.
In one aspect of the invention, the present invention proposes a kind of thin film transistor (TFT).Embodiments in accordance with the present invention, this is thin
Film transistor includes：Substrate；Grid, the grid is set over the substrate；First insulating barrier, the first insulating barrier covering
The grid；Semiconductor layer, the semiconductor layer is arranged on side of first insulating barrier away from the grid；Source electrode and leakage
Pole, the source electrode and drain electrode are separately positioned on side of the semiconductor layer away from first insulating barrier；Second insulating barrier, institute
State the second insulating barrier the covering source electrode and the drain electrode；And channel region protective layer, the channel region protective layer is arranged on
Second insulating barrier away from the side and region corresponding with channel region of the source electrode and the drain electrode, protect by the channel region
Projection of the sheath on the channel region overlaps with the channel region.Thus, channel region protective layer can be with protection device not by outer
Portion's ambient influnence, while not influenceing the performance of device so that thin film transistor (TFT) stability is improved, device performance enhancing.
Embodiments in accordance with the present invention, the thin film transistor (TFT) is further included：Grid cushion, the grid cushion sets
Put between the grid and the substrate, the grid cushion includes transparent conductive material.Thus, it is possible to improve Cu grid
Pole and the adhesion of substrate, improve the stability of thin film transistor (TFT).
The material of embodiments in accordance with the present invention, the grid cushion and the channel region protective layer includes saturating respectively
Bright conductive material, the transparent conductive material includes at least one of ITO, IGZO, IZO, GZO and Graphene.Thus, it is possible to
Under conditions of display is not influenceed, the performance of device stability and device is further improved.
In another aspect of this invention, the present invention proposes a kind of array base palte.Embodiments in accordance with the present invention, the array
Substrate includes：Substrate；Grid cushion, the grid cushion is set over the substrate；Grid, the grid is arranged on institute
State on grid cushion；Public electrode, the public electrode sets the side having over the substrate with the grid；First
Insulating barrier, first insulating barrier covers the grid and the public electrode；Semiconductor layer, the semiconductor layer is arranged on
Side of first insulating barrier away from the grid；Source electrode and drain electrode, the source electrode and drain electrode are separately positioned on described partly to be led
Side of the body layer away from first insulating barrier；Second insulating barrier, second insulating barrier covers the source electrode and the leakage
Pole；And channel region protective layer, the channel region protective layer is arranged on second insulating barrier away from the source electrode and described
The side of drain electrode and region corresponding with channel region, projection of the channel region protective layer on the channel region and the raceway groove
Area overlaps；And pixel electrode, the pixel electrode is arranged on second insulating barrier away from the source electrode and the drain electrode
Side, the pixel electrode is electrically connected with the source electrode or the drain electrode.The array base palte have advantages below at least it
One：Grid cushion is provided between Cu grids and substrate, thus, the adhesion enhancing between Cu grids and substrate, Ke Yiti
The stability of array base palte high；Channel region protective layer can protect the thin film transistor (TFT) in array base palte not receive external environment condition shadow
Ring, and the channel region protective layer is not contacted with the other structures that the second insulating barrier is removed in thin film transistor (TFT), and then do not interfere with
The electric property of thin film transistor (TFT) and array base palte.Thus, it is possible to improve the performance of device.
Embodiments in accordance with the present invention, the public electrode and the grid cushion are formed and same layer by same material
Set.Thus, public electrode and grid cushion can carry out the synchronously preparation of same layer, do not increasing technique and do not changing device base
On the basis of this structure, it is possible to use existing process is prepared, device stability, enhancing device performance, reduces cost are improved.
Embodiments in accordance with the present invention, the pixel electrode and the channel region protective layer are formed and same by same material
Layer is set.Thus, pixel electrode and channel region protective layer can carry out the synchronously preparation of same layer, do not increasing technique and do not changing
On the basis of basic device structure, it is possible to use existing process is prepared, device stability, enhancing device performance, drop are improved
Low cost.
In still another aspect of the invention, the present invention proposes a kind of display device.Embodiments in accordance with the present invention, the display
Device includes foregoing array base palte.Thus, the display device has the whole that previously described array base palte has
Feature and advantage, will not be repeated here.
In still another aspect of the invention, the present invention proposes a kind of method for preparing thin film transistor (TFT).The method includes：Carry
For substrate；Grid is formed over the substrate；In the grid the first insulating barrier is formed away from the side of the substrate；Described
First insulating barrier forms semiconductor layer away from the side of the grid；In the semiconductor layer away from the first insulating barrier side
Deposition forms source electrode and drain electrode；In the source electrode and drain electrode the second insulating barrier is formed away from the side of the semiconductor layer；
Second insulating barrier is away from the side of the source electrode and the drain electrode and region corresponding with channel region forms channel region guarantor
Sheath, projection of the channel region protective layer on the channel region overlaps with the channel region.Thus, it is possible to easily obtain
Previously described thin film transistor (TFT).
Embodiments in accordance with the present invention, the method is further included：Grid are formed between the grid and the substrate
Pole cushion.Grid cushion is formed, it is possible thereby to the adhesion between Reinforced Cu and substrate, improves stability.
In still another aspect of the invention, the present invention proposes a kind of method for preparing foregoing array base palte.The party
Method includes：Substrate is provided；Grid cushion and public electrode are formed over the substrate；In the grid cushion away from institute
The side for stating substrate forms grid；The first insulating barrier is formed, first insulating barrier covers the grid and the common electrical
Pole；In first insulating barrier semiconductor layer is formed away from the side of the grid；In the semiconductor layer away from described first
Insulating barrier side deposits to form source electrode and drain electrode；Thus, it is possible to easily obtain previously described array base palte.
Embodiments in accordance with the present invention, form second exhausted in the source electrode and drain electrode away from the side of the semiconductor layer
Edge layer；In second insulating barrier channel region protective layer and pixel electricity are formed away from the side of the source electrode and the drain electrode
Pole.The channel region protective layer for being formed, can with protection device not receive external environment influence, and the channel region protective layer not with film
The other structures contact of the second insulating barrier is removed in transistor, and then does not interfere with the electricity of thin film transistor (TFT) and array base palte
Performance is such that it is able to the further performance for improving array base palte.
Embodiments in accordance with the present invention, the public electrode and the grid cushion are set and synchronous preparation with layer；
Thus, it is possible to easy and public electrode and grid cushion are synchronously obtained with layer.
Embodiments in accordance with the present invention, the pixel electrode and the channel region protective layer are set and synchronous system with layer
It is standby.Thus, it is possible to easy and pixel electrode and channel region protective layer are synchronously obtained with layer.
Brief description of the drawings
Of the invention above-mentioned and/or additional aspect and advantage will become from description of the accompanying drawings below to embodiment is combined
Substantially and be readily appreciated that, wherein：
Fig. 1 shows the structural representation of thin film transistor (TFT) according to an embodiment of the invention；
Fig. 2 shows the structural representation of thin film transistor (TFT) in accordance with another embodiment of the present invention；
Fig. 3 shows the structural representation of the thin film transistor (TFT) according to another embodiment of the invention；
Fig. 4 shows the structural representation of array base palte according to an embodiment of the invention；
Fig. 5 shows the structural representation of display device according to an embodiment of the invention；
Fig. 6 shows the schematic flow sheet of the method for preparing thin film transistor (TFT) according to an embodiment of the invention；And
Fig. 7 shows the schematic flow sheet of the method for preparing array base palte according to an embodiment of the invention.
Description of reference numerals：
100：Substrate；200：Grid；300：First insulating barrier；400：Semiconductor layer；510：Source electrode；520：Drain electrode；600：
Second insulating barrier；700：Channel region protective layer；800：Grid cushion；810：Public electrode；900：Pixel electrode；1000：Battle array
Row substrate.
Specific embodiment
Embodiments of the invention are described below in detail, the example of the embodiment is shown in the drawings, wherein from start to finish
Same or similar label represents same or similar element or the element with same or like function.Below with reference to attached
It is exemplary to scheme the embodiment of description, is only used for explaining the present invention, and is not considered as limiting the invention.
In the description of the invention, term " on ", the orientation of the instruction such as D score or position relationship be based on shown in the drawings
Orientation or position relationship, are for only for ease of the description present invention rather than requiring that the present invention must be with specific azimuth configuration and behaviour
Make, therefore be not considered as limiting the invention.
In one aspect of the invention, the present invention proposes a kind of thin film transistor (TFT).Embodiments in accordance with the present invention, reference
Fig. 1, the thin film transistor (TFT) includes：Substrate 100, grid 200, the first insulating barrier 300, semiconductor layer 400, source electrode 510, drain electrode
520th, the second insulating barrier 600, channel region protective layer 700.Wherein, grid 200 is set on the substrate 100, and the first insulating barrier 300 covers
Lid grid 200, semiconductor layer 400 is arranged on 520 points of side of first insulating barrier 300 away from grid 200, source electrode 510 and drain electrode
Side of the semiconductor layer 400 away from the first insulating barrier 300, the covering source electrode 510 of the second insulating barrier 600 and drain electrode are not arranged on
520, channel region protective layer 700 is arranged on the second insulating barrier 600 away from source electrode 510 and the side of drain electrode 520, channel region protection
700 projection over the channel region of layer overlaps with channel region.Thus, channel region protective layer 700 can not receive external rings with protection device
Border is influenceed, while not influenceing the performance of device so that thin film transistor (TFT) stability is improved, device performance enhancing.
It should be noted that in the present invention, the projection over the channel region of channel region protective layer 700 overlaps with channel region,
Both the projection over the channel region of channel region protective layer 700 is included, situation about being completely superposed with channel region is also protected including channel region
700 projection on channel region direction of layer, more than the situation (referring to Fig. 2) of channel region.In other words, channel region protective layer 700
In the projection along vertical direction, as long as channel region can be completely covered.Also, in the present invention, channel region protective layer
700 not with the thin film transistor (TFT) in, remove the second insulating barrier 600 beyond form touch.Thus, it is possible to avoid brilliant to the film
The performance of body pipe is adversely affected.Also, it should be noted that in the present invention, source electrode 510, drain electrode 520 and channel region are protected
The isostructural concrete shape of sheath 700, thickness are not particularly limited, and those skilled in the art can be carried out according to actual conditions
Regulation.For example, with reference to Fig. 2, the first insulating barrier 300 can have homogeneous thickness in various location, be produced into save
This, reduces precision controlling, improve production efficiency.And because the first insulating barrier 300 covers substrate 100 and grid 200, because
This, is being provided with the position of grid 200, and the first insulating barrier 300 forms the structure for raising up.
Embodiments in accordance with the present invention, form insulating barrier, semiconductor layer and the isostructural specific material of substrate not by spy
Do not limit, those skilled in the art can be selected according to actual conditions.It is for instance possible to use the transparent material such as glass, PET
Substrate 100 is formed, as long as the material has certain mechanical strength, can be provided to constitute the other structures of the thin film transistor (TFT)
Enough supports.The material of the first insulating barrier 300 and the second insulating barrier 600 can for Si oxide, nitrogen silicide,
Al2O3Deng at least one of insulating materials such as metal oxide and resin, for example, can be SiNx、SiO2Or organic tree
Fat.Semiconductor layer 400 can be what oxide semiconductor material was formed, for example, according to a particular embodiment of the invention, Ke Yiwei
The transparent conductive materials such as IGZO, ITZO.Thus, prepared for the array base palte in display device when using the thin film transistor (TFT)
When, first, above-mentioned transparent conductive material can cause that the thin film transistor (TFT) in array base palte also has preferable light transmittance, and then
The aperture opening ratio of the display device can be improved.Additionally, above-mentioned transparent conductive material has larger carrier mobility, therefore have
Beneficial to the device performance for improving the thin film transistor (TFT).The transparent conductive materials such as IGZO, ITZO when semiconductor layer 400 is prepared, no
It is the preparation for being capable of achieving semiconductor layer 400 to need complicated laser annealing technique, beneficial to reduction production cost, and is applied to
Produce large-sized display device.
Embodiments in accordance with the present invention are of the invention specific in order to further improve the performance of the thin film transistor (TFT)
Embodiment, grid 200 can be formed by Cu.Thus, it is possible to using the resistance characteristic of Cu, reduce the device of the thin film transistor (TFT)
Part resistance.It will be appreciated to those of skill in the art that source electrode 510 and drain electrode 520 can also be formed by Cu.In order to improve Cu
The adhesion of the grid 200 of formation, source electrode 510 or drain electrode 520 and other structures, can also grid 200, source electrode 510 or
Before being drain electrode 520, buffer layer structure is set up.For example, according to a particular embodiment of the invention, with reference to Fig. 3, the thin film transistor (TFT)
Can further include：Grid cushion 800.Grid cushion 800 is arranged between grid 200 and substrate 100.According to
Specific embodiment of the invention, grid cushion 800 can be formed by transparent conductive material.Inventor it was unexpectedly observed that
Grid cushion 800 is formed using transparent conductive material, with conventional Cu cushioning layer materials (such as Al, Mo metal or alloy) phase
Than the grid cushion 800 that transparent conductive material is formed can effectively improve grid on the premise of the electric property for not damaging device
Combination between pole 200 and substrate 100.Also, grid cushion 800 is formed using transparent conductive material, is conducive to improving
The light transmittance of the thin film transistor (TFT), and then the display performance using the display device of the thin film transistor (TFT) can be improved.According to this
The specific embodiment of invention, formed the transparent conductive material of grid cushion 800 can include ITO, IGZO, IZO, GZO and
At least one of Graphene.Thus, it is possible to improve the adhesion of Cu and substrate 100, the stability of thin film transistor (TFT) is improved.
Embodiments in accordance with the present invention, the material of channel region protective layer can include transparent conductive material.Electrically conducting transparent material
Material can include at least one of ITO, IGZO, IZO, GZO and Graphene.Thus, it is possible under conditions of display is not influenceed,
Further improve the performance of device stability and device.Inventor protects it was unexpectedly observed that preparing channel region using above-mentioned material
Layer, can play a protective role first；Secondly, transparent material does not influence display performance during for display device；Finally, the material
Material can be used for forming electrode, be conducive to, using existing production procedure, realizing the setting of electrode, beneficial to reduction production cost.
In another aspect of this invention, the present invention proposes a kind of array base palte.Embodiments in accordance with the present invention, with reference to figure
4, the array base palte includes：Substrate 100, grid cushion 800, public electrode 810, grid 200, the first insulating barrier 300, partly lead
Body layer 400, source electrode 510, the 520, second insulating barrier 600 of drain electrode, channel region protective layer 700, pixel electrode 900.Grid cushion
800 are set on the substrate 100, and grid 200 is arranged on grid cushion 800, and public electrode 810 is set to be had on the substrate 100
There is a side with grid 200, the first insulating barrier 300 covering grid 200 and public electrode 810, semiconductor layer 400 are arranged on the
One insulating barrier 300 is away from the side of grid 200, and it is exhausted away from first that source electrode 510 and drain electrode 520 are separately positioned on semiconductor layer 400
The side of edge layer 300, the covering source electrode 510 of the second insulating barrier 600 and drain electrode 520, it is exhausted that channel region protective layer 700 is arranged on second
Edge layer 600 away from source electrode 510 and drain electrode 520 side and region corresponding with channel region, channel region protective layer 700 not with remove
Form touch beyond second insulating barrier 600, pixel electrode 900 is arranged on the second insulating barrier 600 away from source electrode 510 and drain electrode
520 side, pixel electrode 900 is connected with source electrode 510 or drain electrode 520.The array base palte has at least one of advantages below：
Grid cushion 800 is provided between Cu and substrate 100, thus, the adhesion enhancing between Cu and substrate 100 can be improved
The stability of array base palte；Channel region protective layer 700 can protect the thin film transistor (TFT) in array base palte not receive external environment condition shadow
Ring, and the channel region protective layer 700 do not contact with the other structures that the second insulating barrier 600 is removed in thin film transistor (TFT), enter without
The electric property of thin film transistor (TFT) and array base palte can be influenceed.Thus, it is possible to improve the performance of device.
It will be appreciated to those of skill in the art that in the array base palte, grid cushion 800, grid 200, first
Insulating barrier 300, semiconductor layer 400, source electrode 510, the 520, second insulating barrier 600 of drain electrode and channel region protective layer 700 constitute thin
Film transistor, for realizing being controlled the voltage in different pixels site.In the array base palte 1000, multiple can be included
The thin film transistor (TFT) of array arrangement.Embodiments in accordance with the present invention, the thin film transistor (TFT) in the array base palte 1000, can have
With previously described thin film transistor (TFT) identical feature and advantage, will not be repeated here.
Embodiments in accordance with the present invention, public electrode 810 and grid cushion 800 are formed by same material and set with layer
Put.Thus, public electrode 810 and grid cushion 800 can carry out the synchronously preparation of same layer, not increase technique and non-changer
On the basis of part basic structure, it is possible to use existing process is prepared, improve device stability, enhancing device performance, reduce
Cost.According to a particular embodiment of the invention, the public electrode 810 and grid cushion 800 for synchronously being set with layer are using saturating
Bright conductive material.The particular type of transparent conductive material is not particularly limited, if can be used in forming public electrode 810, and
For the action material of cushion can be played.For example, according to a particular embodiment of the invention, the transparent conductive material can be with
Including at least one of ITO, IGZO, IZO, GZO and Graphene.Thus, be conducive to improving the light transmittance of the array base palte,
And then the display performance of the display device for using the array base palte can be improved.
Embodiments in accordance with the present invention, pixel electrode 900 and channel region protective layer 700 are formed and same layer by same material
Set.Thus, pixel electrode 900 and channel region protective layer can carry out the synchronously preparation of same layer, do not increasing technique and do not changing
Become basic device structure on the basis of, it is possible to use existing process is prepared, improve device stability, enhancing device performance,
Reduces cost.According to a particular embodiment of the invention, the pixel electrode 900 and channel region protective layer for synchronously being set with layer are adopted
With transparent conductive material, the transparent conductive material can include at least one ITO, IGZO, IZO, GZO and Graphene.By
This, is conducive to improving the light transmittance of the array base palte, and then can improve the display using the display device of the array base palte
Energy.
In still another aspect of the invention, the present invention proposes a kind of display device.Embodiments in accordance with the present invention, with reference to figure
5, the display device includes previously described array base palte 1000.Thus, the display device has previously described array base palte
The 100 whole features and advantage having, will not be repeated here.
In still another aspect of the invention, the present invention proposes a kind of method for preparing foregoing thin film transistor (TFT).Ginseng
Examining Fig. 6 the method includes：
S100：Substrate is provided
Embodiments in accordance with the present invention, in this step, there is provided substrate.The specific material for forming the structure of substrate is unrestricted
System, specifically, substrate can be formed using transparent materials such as glass, PET, as long as the material has certain mechanical strength, can
Enough supports are provided with to be constituted the other structures of the thin film transistor (TFT).
S200：Form grid
Embodiments in accordance with the present invention, in this step, form grid on substrate.Grid can be formed by Cu.
Thus, it is possible to using the resistance characteristic of Cu, reduce the device resistance of the thin film transistor (TFT).
Embodiments in accordance with the present invention, for the adhesion between Reinforced Cu grid and substrate, improve thin film transistor (TFT)
Stability, the method can further include：Grid cushion is formed between grid and substrate.It is possible thereby to Reinforced Cu
Adhesion between substrate, improves thin film transistor (TFT) stability.
It should be noted that in this step, the specific method and parameter for forming grid cushion are not particularly limited,
As long as above-mentioned grid cushion can be formed.It is for instance possible to use deposition or the method for vacuum evaporation, prepare grid buffering
Layer.
S300：Form the first insulating barrier
Embodiments in accordance with the present invention, in this step, the first insulating barrier are formed in grid away from the side of substrate.Formed
First insulating layer material can be formed at least one of Si oxide, nitrogen silicide and resin, for example, can be SiNx、
SiO2Or organic resin.Stability is high while above-mentioned material has insulation function.The specific of the first insulating barrier is formed simultaneously
Method is not particularly limited, as long as above-mentioned first insulating barrier can be formed.For example, can be by inorganic material or painting
The mode of cloth organic resin forms the first insulating barrier.
S400：Form semiconductor layer
Embodiments in accordance with the present invention, in this step, semiconductor layer are formed in the first insulating barrier away from the side of grid.
Semiconductor layer can be what oxide semiconductor material was formed, for example, according to a particular embodiment of the invention, can for IGZO,
The transparent conductive materials such as ITZO.Above-mentioned transparent conductive material has preferable light transmittance, and then can improve the display device
Aperture opening ratio.Above-mentioned transparent conductive material has larger carrier mobility simultaneously, is conducive to improving the device of the thin film transistor (TFT)
Part performance.The transparent conductive materials such as IGZO, ITZO are when semiconductor layer is prepared, it is not necessary to which complicated laser annealing technique can be real
The preparation of existing semiconductor layer, beneficial to reduction production cost, and is applied to the large-sized display device of production.
S500：Deposition forms source electrode and drain electrode
Embodiments in accordance with the present invention, in this step, the source of being formed are deposited in semiconductor layer away from the first insulating barrier side
Pole and drain electrode.It will be appreciated to those of skill in the art that source electrode and drain electrode can be formed by Cu, it is possible to use the low electricity of Cu
Resistance characteristic, reduces the device resistance of the thin film transistor (TFT).It will be appreciated to those of skill in the art that in order to strengthen source electrode, leakage
Pole and the combination of the first insulating barrier, can set buffer layer structure before source electrode, drain electrode is formed.
S600：Form the second insulating barrier
Embodiments in accordance with the present invention, in this step, the are formed in source electrode and drain electrode away from the side of semiconductor layer
Two insulating barriers.The material for forming the second insulating barrier can be formed at least one of Si oxide, nitrogen silicide and resin, example
Such as, can be SiNx、SiO2Or organic resin.Stability is high while above-mentioned material has insulating properties.Second is formed simultaneously
The specific method of insulating barrier is not particularly limited, as long as above-mentioned second insulating barrier can be formed.For example, tool of the invention
Body embodiment, the forming method and condition of the second insulating barrier can be identical with the method and condition for forming the first insulating barrier,
Thus, it is possible to realize the preparation of the first insulating barrier and the second insulating barrier using identical equipment, and then be conducive to saving equipment
Cost.
S700：Form channel region protective layer
Embodiments in accordance with the present invention, in this step, the second insulating barrier away from the side of source electrode and drain electrode and with
The corresponding region of channel region forms channel region protective layer.Thus, it is possible to easily obtain previously described thin film transistor (TFT).Institute's shape
Into channel region protective layer, can with protection device not receive external environment influence, and the channel region protective layer not with thin film transistor (TFT)
The middle other structures contact for removing the second insulating barrier, so do not interfere with the electric property of thin film transistor (TFT) and array base palte from
And can further improve the performance of array base palte.Position, shape on channel region protective layer and form material, before
Through being described in detail, will not be repeated here.
In still another aspect of the invention, the present invention proposes a kind of method for preparing foregoing array base palte.With reference to
Fig. 7, the method includes：
S100：Substrate is provided
Embodiments in accordance with the present invention, in the step, there is provided substrate concrete structure, type, before have been carried out
Detailed description, will not be repeated here.
S10：Form grid cushion and public electrode
Embodiments in accordance with the present invention, in this step, form grid cushion and public electrode on substrate.By
This, public electrode and grid cushion can carry out same layer and synchronously prepare, and do not increasing technique and do not changing basic device structure
On the basis of, it is possible to use existing process is prepared, and improves device stability, enhancing device performance, reduces cost.According to this
The specific embodiment of invention, the grid cushion synchronously set with layer and public electrode use transparent conductive material, and this is transparent
Conductive material can include at least one of ITO, IGZO, IZO, GZO and Graphene.Thus, be conducive to improving the array base
The light transmittance of plate, and then the display performance using the display device of the array base palte can be improved.
S200：Form grid
In embodiments in accordance with the present invention, the step and the previously described method for preparing thin film transistor (TFT), grid is formed
The step of there is identical feature and advantage, will not be repeated here.
S300：Form the first insulating barrier
In embodiments in accordance with the present invention, the step and the previously described method for preparing thin film transistor (TFT), first is formed
The step of insulating barrier, has identical feature and advantage, will not be repeated here.
S400：Form semiconductor layer
In embodiments in accordance with the present invention, the step and the previously described method for preparing thin film transistor (TFT), formation is partly led
The step of body layer, has identical feature and advantage, will not be repeated here.
S500：Deposition forms source electrode and drain electrode
In embodiments in accordance with the present invention, the step and the previously described method for preparing thin film transistor (TFT), source electrode is formed
And the step of drain electrode has identical feature and advantage, will not be repeated here.
S600：Form the second insulating barrier
In embodiments in accordance with the present invention, the step and the previously described method for preparing thin film transistor (TFT), second is formed
The step of insulating barrier, has identical feature and advantage, will not be repeated here.
S20：Form channel region protective layer and pixel electrode
Embodiments in accordance with the present invention, in this step, the second insulating barrier away from the side of source electrode and drain electrode and with
The corresponding region of channel region forms channel region protective layer and pixel electrode.The channel region protective layer for being formed, can be with protector
Part does not receive external environment influence, and the channel region protective layer does not remove the other structures of the second insulating barrier and connect with thin film transistor (TFT)
Touch, and then do not interfere with the electric property of thin film transistor (TFT) and array base palte, such that it is able to further improve array base palte
Performance.Pixel electrode and channel region protective layer can carry out same layer and synchronously prepare, and do not increasing technique and do not changing device base
On the basis of this structure, it is possible to use existing process is prepared, device stability, enhancing device performance, reduces cost are improved.
According to a particular embodiment of the invention, the pixel electrode and channel region protective layer for synchronously being set with layer use electrically conducting transparent material
Material, the transparent conductive material can include at least one ITO, IGZO, IZO, GZO and Graphene.Thus, be conducive to improving
The light transmittance of the array base palte, and then the display performance using the display device of the array base palte can be improved.
In the description of this specification, the description of reference term " one embodiment ", " another embodiment " etc. means knot
Specific features, structure, material or the feature for closing embodiment description are contained at least one embodiment of the invention.At this
In specification, the schematic representation to above-mentioned term is necessarily directed to identical embodiment or example.And, the tool of description
Body characteristicses, structure, material or feature can in an appropriate manner be combined in any one or more embodiments or example.This
Outward, in the case of not conflicting, those skilled in the art by the different embodiments described in this specification or can show
The feature of example and different embodiments or example is combined and combines.
Although embodiments of the invention have been shown and described above, it is to be understood that above-described embodiment is example
Property, it is impossible to limitation of the present invention is interpreted as, one of ordinary skill in the art within the scope of the invention can be to above-mentioned
Embodiment is changed, changes, replacing and modification.
Claims (10)
1. a kind of thin film transistor (TFT), it is characterised in that including：
Substrate；
Grid, the grid is set over the substrate；
First insulating barrier, first insulating barrier covers the grid；
Semiconductor layer, the semiconductor layer is arranged on side of first insulating barrier away from the grid；
Source electrode and drain electrode, the source electrode and drain electrode are separately positioned on side of the semiconductor layer away from first insulating barrier；
Second insulating barrier, second insulating barrier covers the source electrode and the drain electrode；And
Channel region protective layer, the channel region protective layer is arranged on second insulating barrier away from the source electrode and the drain electrode
Side and region corresponding with channel region, projection of the channel region protective layer on the channel region and the channel region weight
Close.
2. thin film transistor (TFT) according to claim 1, it is characterised in that further include：Grid cushion, the grid
Cushion is arranged between the grid and the substrate, and the grid cushion includes transparent conductive material.
3. thin film transistor (TFT) according to claim 2, it is characterised in that the grid cushion and the channel region are protected
The material of sheath includes transparent conductive material respectively, and the transparent conductive material includes ITO, IGZO, IZO, GZO and Graphene
At least one of.
4. a kind of array base palte, it is characterised in that including：
Substrate；
Grid cushion, the grid cushion is set over the substrate；
Grid, the grid is arranged on the grid cushion；
Public electrode, the public electrode sets the side having over the substrate with the grid；
First insulating barrier, first insulating barrier covers the grid and the public electrode；
Semiconductor layer, the semiconductor layer is arranged on side of first insulating barrier away from the grid；
Source electrode and drain electrode, the source electrode and drain electrode are separately positioned on side of the semiconductor layer away from first insulating barrier；
Second insulating barrier, second insulating barrier covers the source electrode and the drain electrode；And
Channel region protective layer, the channel region protective layer is arranged on second insulating barrier away from the source electrode and the drain electrode
Side and region corresponding with channel region, projection of the channel region protective layer on the channel region and the channel region weight
Close；And
Pixel electrode, the pixel electrode is arranged on second insulating barrier away from the source electrode and the side of the drain electrode,
The pixel electrode is electrically connected with the source electrode or the drain electrode.
5. array base palte according to claim 4, it is characterised in that the public electrode and the grid cushion by
Same material is formed and set with layer；
Optionally, the pixel electrode and the channel region protective layer are formed by same material and set with layer.
6. a kind of display device, it is characterised in that including the array base palte described in claim 4 or 5.
7. a kind of method for preparing thin film transistor (TFT), it is characterised in that including：
Substrate is provided；
Grid is formed over the substrate；
In the grid the first insulating barrier is formed away from the side of the substrate；
In first insulating barrier semiconductor layer is formed away from the side of the grid；
Deposit to form source electrode and drain electrode away from the first insulating barrier side in the semiconductor layer；
In the source electrode and drain electrode the second insulating barrier is formed away from the side of the semiconductor layer；
In second insulating barrier away from the side of the source electrode and the drain electrode and region corresponding with channel region formation ditch
Road area protective layer, projection of the channel region protective layer on the channel region overlaps with the channel region.
8. method according to claim 7, it is characterised in that further include：
Grid cushion is formed between the grid and the substrate.
9. a kind of method of the array base palte prepared described in claim 4 or 5, it is characterised in that including：
Substrate is provided；
Grid cushion and public electrode are formed over the substrate；
In the grid cushion grid is formed away from the side of the substrate；
The first insulating barrier is formed, first insulating barrier covers the grid and the public electrode；
In first insulating barrier semiconductor layer is formed away from the side of the grid；
Deposit to form source electrode and drain electrode away from the first insulating barrier side in the semiconductor layer；
In the source electrode and drain electrode the second insulating barrier is formed away from the side of the semiconductor layer；
In second insulating barrier channel region protective layer and pixel electricity are formed away from the side of the source electrode and the drain electrode
Pole.
10. method according to claim 9, it is characterised in that the public electrode and the same layer of grid cushion
Set and synchronous preparation；
Optionally, the pixel electrode and the channel region protective layer are set and synchronous preparation with layer.
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