CN106876412A - A kind of array base palte and preparation method - Google Patents
A kind of array base palte and preparation method Download PDFInfo
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- CN106876412A CN106876412A CN201710153697.XA CN201710153697A CN106876412A CN 106876412 A CN106876412 A CN 106876412A CN 201710153697 A CN201710153697 A CN 201710153697A CN 106876412 A CN106876412 A CN 106876412A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 25
- 239000010408 film Substances 0.000 claims abstract description 316
- 239000010409 thin film Substances 0.000 claims abstract description 257
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 230000004888 barrier function Effects 0.000 claims description 115
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 59
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 37
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 37
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 26
- 238000002161 passivation Methods 0.000 claims description 22
- 238000003475 lamination Methods 0.000 claims description 17
- 239000000377 silicon dioxide Substances 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 12
- 239000013078 crystal Substances 0.000 claims description 11
- 238000005984 hydrogenation reaction Methods 0.000 claims description 9
- 239000004973 liquid crystal related substance Substances 0.000 claims description 7
- 229910003978 SiClx Inorganic materials 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 claims 1
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 10
- 150000004706 metal oxides Chemical class 0.000 abstract description 10
- 229920005591 polysilicon Polymers 0.000 abstract description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 11
- 230000000694 effects Effects 0.000 description 9
- 239000001257 hydrogen Substances 0.000 description 9
- 229910052739 hydrogen Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 230000008901 benefit Effects 0.000 description 6
- 238000005401 electroluminescence Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 229910010272 inorganic material Inorganic materials 0.000 description 3
- 239000011147 inorganic material Substances 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- -1 hydrogen ions Chemical class 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The embodiment of the invention discloses a kind of array base palte with and preparation method thereof, the array base palte includes：Multiple first film transistors and multiple second thin film transistor (TFT)s；First film transistor and second thin film transistor (TFT) are formed at the top of underlay substrate；The active layer of first film transistor is low temperature polycrystalline silicon, and the active layer of second thin film transistor (TFT) is oxide semiconductor；First film transistor is located at the periphery circuit region of array base palte, and the second thin film transistor (TFT) is located at the viewing area of the array base palte；The grid of the grid of first film transistor and the second thin film transistor (TFT) is located at different layers, and the source-drain electrode of the source-drain electrode of first film transistor and the second thin film transistor (TFT) is located at same layer.The present invention is solved when forming metal oxide thin-film transistor and low-temperature polysilicon film transistor simultaneously in display panel, and the incompatible problem of each film layer of two types thin film transistor (TFT) improves the electric property and stability of display panel.
Description
Technical field
The present embodiments relate to display technology field, more particularly to a kind of array base palte and preparation method.
Background technology
Active layer material of the metal oxide thin-film transistor using metal oxide semiconductor layer as thin film transistor (TFT), by
There is the optical characteristics such as carrier mobility is high, depositing temperature is low and transparency is high in it, the display panel as main flow drives
Dynamic technology.Low-temperature polysilicon film transistor switching speed is high, and for example thin film circuit can be made thinner smaller, power consumption more low
Deng.
In the prior art, low-temperature polysilicon film transistor, the pixel-driving circuit of viewing area are used in periphery circuit region
With metal oxide thin-film transistor, the problems such as improve device homogeneity difference and leakage current.
But due to current manufacture craft, while metal oxide thin-film transistor is made, make low temperature many
Polycrystal silicon film transistor, causes two kinds of thin film transistor (TFT)s incompatible due to respective optimal thicknesses of layers, therefore cannot realize same
When ensure that each film layer of metal oxide thin-film transistor and low-temperature polysilicon film transistor is in optimum thickness, it is difficult to send out
Shoot optimal performance.
The content of the invention
In view of this, the embodiment of the present invention provides a kind of array base palte and preparation method, in solution display panel simultaneously
When forming metal oxide thin-film transistor and low-temperature polysilicon film transistor, each film layer of two types thin film transistor (TFT) is not simultaneous
The problem of appearance, improves the electric property and stability of display panel.
In a first aspect, a kind of array base palte is the embodiment of the invention provides, including：Multiple first film transistors and multiple
Second thin film transistor (TFT)；The first film transistor and second thin film transistor (TFT) are formed at the top of underlay substrate；Institute
The active layer of first film transistor is stated for low temperature polycrystalline silicon, the active layer of second thin film transistor (TFT) is partly led for oxide
Body；The first film transistor is located at the periphery circuit region of the array base palte, and second thin film transistor (TFT) is located at described
The viewing area of array base palte；
The grid of the grid of the first film transistor and second thin film transistor (TFT) is located at different layers, and described the
The source-drain electrode of the source-drain electrode of one thin film transistor (TFT) and second thin film transistor (TFT) is located at same layer.
Second aspect, the embodiment of the present invention additionally provides a kind of display panel, including the array base palte described in first aspect.
The third aspect, the embodiment of the present invention additionally provides a kind of preparation method of array base palte, including：In underlay substrate
Top forms multiple first film transistors and multiple second thin film transistor (TFT)s；
Wherein, the active layer of the first film transistor be low temperature polycrystalline silicon, second thin film transistor (TFT) it is active
Layer is oxide semiconductor；The first film transistor is located at the periphery circuit region of the array base palte, second film
Transistor is located at the viewing area of the array base palte；
The grid of the grid of the first film transistor and second thin film transistor (TFT) is located at different layers, and described the
The source-drain electrode of the grid of one thin film transistor (TFT) and second thin film transistor (TFT) is located at same layer.
The embodiment of the present invention by providing a kind of array base palte and preparation method thereof, by by the grid of first film transistor
The grid of pole and the second thin film transistor (TFT) is located at different layers, while source-drain electrode is located at same layer, it is ensured that the first film crystal
The thickness of each film layer of pipe and the second thin film transistor (TFT) is in each optimal scope, gives full play to first film transistor and the
The optimal effect in array base palte of two thin film transistor (TFT)s, improves the electric property and stability of display panel.
Brief description of the drawings
It is of the invention by reading the detailed description made to non-limiting example made with reference to the following drawings explanation
Other features, objects and advantages will become apparent.
Fig. 1 is a kind of cross-sectional view of array base palte provided in an embodiment of the present invention；
Fig. 2 is the cross-sectional view of another array base palte provided in an embodiment of the present invention；
Fig. 3 is the cross-sectional view of another array base palte provided in an embodiment of the present invention；
Fig. 4 is the cross-sectional view of another array base palte provided in an embodiment of the present invention；
Fig. 5 is the cross-sectional view of another array base palte provided in an embodiment of the present invention；
Fig. 6 is the cross-sectional view of another array base palte provided in an embodiment of the present invention；
Fig. 7 is the cross-sectional view of another array base palte provided in an embodiment of the present invention；
Fig. 8 is the cross-sectional view of another array base palte provided in an embodiment of the present invention；
Fig. 9 is a kind of cross-sectional view of display panel provided in an embodiment of the present invention；
Figure 10 is a kind of flow chart of the preparation method of array base palte provided in an embodiment of the present invention.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention, rather than limitation of the invention.It also should be noted that, in order to just
Part rather than entire infrastructure related to the present invention is illustrate only in description, accompanying drawing.
The invention provides a kind of array base palte, including underlay substrate, multiple first film transistors and multiple second are thin
Film transistor；First film transistor and the second thin film transistor (TFT) are formed at the top of underlay substrate；First film transistor
Active layer is low temperature polycrystalline silicon, and the active layer of the second thin film transistor (TFT) is oxide semiconductor；First film transistor is located at battle array
The periphery circuit region of row substrate, the second thin film transistor (TFT) is located at the viewing area of the array base palte.In the present invention, the first film is brilliant
The grid of the grid of body pipe and the second thin film transistor (TFT) is located at different layers, and the source-drain electrode of first film transistor and second thin
The source-drain electrode of film transistor is located at same layer, it is ensured that the thickness of each film layer of first film transistor and the second thin film transistor (TFT)
Degree solves first film transistor in the prior art and the second thin film transistor (TFT) in array base palte in each optimal scope
In the optimal incompatible problem of thicknesses of layers, give full play to first film transistor and the second thin film transistor (TFT) in array base palte
Optimal effect.
Above is core concept of the invention, below in conjunction with the accompanying drawing in the embodiment of the present invention, to the embodiment of the present invention
In technical scheme be clearly and completely described.Based on the embodiment in the present invention, those of ordinary skill in the art are not having
Make under the premise of creative work, the every other embodiment for being obtained belongs to the scope of protection of the invention.
Fig. 1 is a kind of cross-sectional view of array base palte provided in an embodiment of the present invention.Array base palte includes substrate
Substrate 10, multiple first film transistors 30 and multiple second thin film transistor (TFT)s 50, exemplarily only show one first in Fig. 1
Thin film transistor (TFT) 30 and second thin film transistor (TFT) 50.The thin film transistor (TFT) 50 of first film transistor 30 and second is both formed in
The top of underlay substrate 10；The active layer 31 of first film transistor 30 is low temperature polycrystalline silicon, and second thin film transistor (TFT) 50 has
Active layer 52 is oxide semiconductor；First film transistor 30 is located at the periphery circuit region A of array base palte, the second thin film transistor (TFT)
The 50 viewing area B for being located at array base palte.The active layer 31 of first film transistor 30 is low temperature polycrystalline silicon, such film crystal
Pipe electron mobility is higher, and it is high to meet display device periphery circuit region electron mobility, switching speed requirement high.Second film
The active layer 52 of transistor 50 is oxide semiconductor, and carrier mobility is higher, can meet display device viewing area for
Device stability demand high, it is low to visible transparent, technological temperature and can large-area manufacturing the advantages of, sull is brilliant
Body pipe is applied to the viewing area of array base palte, can effectively improve picture element density, aperture opening ratio and the brightness of viewing area, while also
Can by improve oxide thin film transistor stability improve display panel display quality, it is to avoid occur damaged picture or
The problems such as brightness irregularities.It should be noted that first film transistor 30 can be nmos pass transistor in the embodiment of the present invention
Or PMOS transistor, the second thin film transistor (TFT) 50 can also be nmos pass transistor or PMOS transistor, and the embodiment of the present invention is to
The channel type of one thin film transistor (TFT) 30 and the second thin film transistor (TFT) 50 is not limited.
Referring to Fig. 1, the grid 51 of the thin film transistor (TFT) 50 of grid 32 and second of first film transistor 30 is located at different layers,
And the source-drain electrode 53 of the thin film transistor (TFT) 50 of source-drain electrode 33 and second of first film transistor 30 is located at same layer.Fig. 1 examples
The setting first film transistor 30 of property uses top gate structure, the second thin film transistor (TFT) 50 to use bottom grating structure.Referring to Fig. 1, lining
Cushion 11, the active layer 31 of first film transistor 30, the first insulating barrier 12, the first film are disposed with substrate 10
The grid 32 of transistor 30, the second insulating barrier 13, the grid 51 of the second thin film transistor (TFT) 50, the 3rd insulating barrier 14, the second film
The active layer 52 of transistor 50, the source electrode of the thin film transistor (TFT) 50 of source-drain electrode 33 and second of first film transistor 30 and leakage
Pole 53.
The distance between the active layer 31 of first film transistor 30 and the grid 32 of first film transistor 30 can be with roots
Adjusted according to the characteristics of first film transistor 30 according to related practitioner and be set to optimal thickness.Second thin film transistor (TFT) 50
The thin film transistor (TFT) 50 of grid 51 and second active layer 52 between the thickness of the 3rd insulating barrier 14 equally can be according to
The performance requirement of two thin film transistor (TFT)s 50, is arranged to optimal thickness.Such structure setting, both ensure that the first film crystal
The demand of thicker insulating barrier is needed between the grid 32 of pipe 30 and the source-drain electrode metal of first film transistor 30, is met again
The relatively thin demand of insulating barrier between the active layer 52 of the thin film transistor (TFT) 50 of grid 51 and second of the second thin film transistor (TFT) 50,
Ensure that the thickness of each film layer of the thin film transistor (TFT) 50 of first film transistor 30 and second can be at each optimal scope,
The optimal effect in array base palte of the thin film transistor (TFT) 50 of first film transistor 30 and second is given full play to, is not received each other
Influence.
Optionally, the insulating barrier 12 of cushion 11 and first can be inorganic material, for example can be silica and silicon nitride,
Or can also be the lamination of silica and silicon nitride.It will be understood by those skilled in the art that the material of cushion 11 include but
It is not limited to above example.Wherein, about cushion 11 thickness selection, related practitioner can according to the need for product from
The specific thickness of row adjustment cushion 11.
Alternatively, reference picture 1, the 3rd insulating barrier 14 includes silicon nitride layer 140 and silicon oxide layer 141 that lamination is set；Its
Middle silicon oxide layer 141 is contacted with the active layer 52 of the second thin film transistor (TFT) 50.Due in a certain temperature conditions, silicon nitride layer
141 hydrogen molecule can be activated, active if the active layer 52 of the second thin film transistor (TFT) 50 is directly contacted with silicon nitride layer 141
Layer 52 easily by the hydrogen molecule hydrogenation in silicon nitride layer 141, influences the electric property of active layer 52.Therefore, the embodiment of the present invention
The active layer 52 for setting the thin film transistor (TFT) 50 of silicon oxide layer 141 and second is contacted, rather than silicon nitride layer 140 directly and active layer
52 contacts, can avoid influence of the silicon nitride layer 141 higher of hydrogen content in manufacturing process to the electric property of active layer 52.
Alternatively, reference picture 1, the source-drain electrode of the thin film transistor (TFT) 50 of active layer 52 and second of the second thin film transistor (TFT) 50
Etching barrier layer 15 is provided between 53；Etching barrier layer 15 is provided with via 16, the source-drain electrode of the second thin film transistor (TFT) 50
53 are connected by via 16 with the active layer 52 of the second thin film transistor (TFT) 50.
Another array base palte of the embodiment of the present invention shown in reference picture 2, the active layer 52 of the second thin film transistor (TFT) 50
On be provided with etching barrier layer 15；The subregion of the source-drain electrode 53 of the second thin film transistor (TFT) 50 and the second thin film transistor (TFT) 50
The directly contact of active layer 52.
It should be noted that being provided with the active layer 52 of the second thin film transistor (TFT) of array base palte 50 shown in Fig. 1 and Fig. 2
When etching barrier layer 15 can avoid etching from forming the source-drain electrode 53 of the second thin film transistor (TFT) 50, etching liquid is brilliant to the second film
The influence of the active layer 52 of body pipe 50.
Alternatively, the material of the etching barrier layer 15 in above-mentioned technical proposal includes silica.Due to etching barrier layer 15
Directly the active layer 52 with the second thin film transistor (TFT) 50 is contacted, therefore can choose oxygen in the material selection of etching barrier layer 15
SiClx is the inorganic material of representative.
Optionally, array base palte provided in an embodiment of the present invention can also include multiple capacitance structures.Reference picture 3, this hair
The array base palte that bright embodiment is provided can also include multiple capacitance structures 40.Wherein, the first electrode 41 of capacitance structure 40 with
The grid 31 of first film transistor 30 is set with layer, the grid of the thin film transistor (TFT) 50 of second electrode 42 and second of capacitance structure 40
Pole 51 is set with layer.The first electrode 41 of capacitance structure 40 sets with the grid 31 of first film transistor 30 with layer in the present embodiment
Put, the grid 51 of the thin film transistor (TFT) 50 of second electrode 42 and second of capacitance structure 40 is set with layer, that is, making film crystal
While pipe, capacitance structure 40 is made, reached simplification of flowsheet, the effect of reduces cost.
On the basis of the various embodiments described above, for example, see Fig. 4, optionally, the source-drain electrode of first film transistor 30
33 and second thin film transistor (TFT) 50 source-drain electrode 53 on be provided with protection passivation layer 17.
Alternatively, the material of protection passivation layer 17 includes silica.Protection passivation layer 17 can be one layer or laminated construction.
For example protection passivation layer 17 can also include silicon nitride layer 171 and silicon oxide layer 170 that lamination is set；Wherein silicon oxide layer 170
Source-drain electrode 53 with the thin film transistor (TFT) 50 of source-drain electrode 33 and second of first film transistor 30 is contacted.It is blunt due to protecting
Change layer 17 close to the second thin film transistor (TFT) 50, the locus of active layer 52 of the second thin film transistor (TFT) of distance 50 is nearer, exemplary
Ground, in the case of the silicon nitride layer 171 and silicon oxide layer 170 that protection passivation layer 17 includes lamination setting, it is contemplated that the
The active layer 52 of two thin film transistor (TFT)s 50 is oxide semiconductor, and after being hydrogenated, electric property can change, therefore set herein
Silicon oxide layer 170 is put to be connect with the source-drain electrode 53 of the thin film transistor (TFT) 50 of source-drain electrode 33 and second of first film transistor 30
Touch.
Protection passivation layer 17 have excellent heat endurance, chemical stability, water resistance, insulating properties, thermal coefficient of expansion it is small,
Extremely strong with the adhesive force of organic film and difficult for drop-off the advantages of.It should be noted that array base palte provided in an embodiment of the present invention
Can apply in organic electroluminescence display panel, in can be applied in liquid crystal display panel etc..If the embodiment of the present invention is provided
Array base palte apply in organic electroluminescence display panel, optionally, the top of the protection passivation layer 17 of array base palte can be with
Organic planarization layer 18, anode 19, pixel confining layers 21, light emitting device layer 20 and negative electrode 22 are set.Organic electroluminescence display panel
When luminous, in the case where certain voltage drives, electronics and hole are injected into light emitting device layer 20 from negative electrode 22 and anode 19 respectively,
By meeting, being formed exciton and excite light emitting molecule, the latter sends visible ray by radiative relaxation.
If array base palte provided in an embodiment of the present invention is applied in liquid crystal display panel, referring to Fig. 5, array base palte 10
The top of passivation layer 17 is protected to be also provided with machine flatness layer 18 and pixel electrode 23.Then by array base palte 10 and coloured silk
Filling liquid crystal molecule is pressed, encapsulated between ilm substrate, forms display panel.Liquid crystal display panel using thin film transistor (TFT) as
Switching device, is to apply certain voltage drive signals between pixel electrode and public electrode, controls the orientation of liquid crystal molecule, is in
Reveal display image.
It should be noted that in the various embodiments described above, in each film layer of first film transistor and the second thin film transistor (TFT)
Each film layer can according to the actual requirements select suitable thickness range.In the embodiment of the present invention, each film of first film transistor
Each film layer in layer and the second thin film transistor (TFT) can be set according to following thickness range：
Alternatively, 140 thickness ranges of 14 silicon nitride layer are 50~400nm in the 3rd insulating barrier.
Alternatively, the thickness range of silicon oxide layer 141 is 30~200nm in the 3rd insulating barrier 14.
Alternatively, the thickness range of the active layer 52 of the second thin film transistor (TFT) 50 is 20~100nm.
Alternatively, the thickness of etching barrier layer 15 is 50~250nm.
Exemplarily, referring to Fig. 4, cushion 11 can be exemplarily silicon oxide layer, silicon nitride, silicon oxide stack, thickness
Degree is followed successively by 500nm, 120nm and 300nm.The thickness of the active layer 31 of first film transistor 30 can be 45nm, and first is thin
First insulating barrier 12 of film transistor 30 can be the lamination of silica and silicon nitride, and thickness is followed successively by 80nm and 40nm, first
The thickness of the grid of thin film transistor (TFT) 30 is 220nm, and the thickness of the first electrode 41 of capacitance structure 40 is 220nm, the second insulation
The thickness of 13 silicon nitride of layer is 100nm, the source and drain of the thin film transistor (TFT) 50 of source-drain electrode 33 and second of first film transistor 30
Electrode 53 can be metal laminated for Ti, Al, Ti, and thickness is respectively 70nm, 400nm and 50nm, protects the silica of passivation layer 17
The thickness of layer 170 is 100nm, and the thickness of silicon nitride layer 171 is 150nm, and the thickness of organic planarization layer 18 is 2 μm, and anode 19 shows
Example property ground is the lamination of ITO, Ag, ITO, and thickness is respectively 80nm, 150nm and 100nm.
It should be noted that except first film transistor 30 uses top gate structure, the second thin film transistor (TFT) 50 to use bottom
Outside grid structure, in other embodiments, the bottom grating structure and top gate structure of first film transistor and the second thin film transistor (TFT)
Setting can also carry out other combinations, such as first film transistor is bottom grating structure, and the second thin film transistor (TFT) is bottom gate
Structure；Or first film transistor is bottom grating structure, the second thin film transistor (TFT) is top gate structure；Or first film transistor
It is top gate structure, the second thin film transistor (TFT) is top gate structure.
Array base palte shown in Fig. 6, is bottom grating structure with first film transistor 30, and the second thin film transistor (TFT) 50 is bottom gate
Structure.Array base palte shown in Fig. 7, first film transistor 30 is bottom grating structure, and the second thin film transistor (TFT) 50 is top gate structure.
Array base palte shown in Fig. 8, first film transistor 30 is top gate structure, the top gate structure of the second thin film transistor (TFT) 50.
It should be noted that the top gate structure of the thin film transistor (TFT) 50 of first film transistor 30 and second and bottom grating structure
Choose different, the distance between two electrodes of capacitance structure 40 can be different.Those skilled in the art can be according to product
The actual demand of design is selected the structure type of the thin film transistor (TFT) 50 of first film transistor 30 and second.
The embodiment of the present invention also provides a kind of display panel.Fig. 9 is a kind of display panel provided in an embodiment of the present invention
Structural representation.As shown in figure 9, the display panel includes the total array base palte 100 of above-described embodiment.The present invention is implemented
The display panel that example is provided includes the array base palte in above-described embodiment, therefore display panel provided in an embodiment of the present invention also has
There is the beneficial effect described in above-described embodiment, here is omitted.It should be noted that provided in an embodiment of the present invention aobvious
Show that panel can be organic electroluminescence display panel, can also be liquid crystal display panel.Exemplarily, organic electroluminescence display panel can
Being any product or part with display function such as notebook computer, panel computer or display.
Based on same design invention, the embodiment of the present invention also provides a kind of preparation method of array base palte.The preparation method
Including：
Multiple first film transistors and multiple second thin film transistor (TFT)s are formed in the top of underlay substrate.Wherein, it is described
The active layer of first film transistor is low temperature polycrystalline silicon, and the active layer of second thin film transistor (TFT) is oxide semiconductor；
The first film transistor is located at the periphery circuit region of the array base palte, and second thin film transistor (TFT) is located at the array
The viewing area of substrate.
The grid of the grid of the first film transistor and second thin film transistor (TFT) is located at different layers, and described the
The source-drain electrode of the grid of one thin film transistor (TFT) and second thin film transistor (TFT) is located at same layer.
A kind of preparation method of array base palte provided in an embodiment of the present invention, multiple is formed by the top in underlay substrate
First film transistor and multiple second thin film transistor (TFT)s.The grid of the grid of first film transistor and the second thin film transistor (TFT)
Positioned at different layers, and the source-drain electrode of the source-drain electrode of first film transistor and the second thin film transistor (TFT) is located at same layer, can be with
Ensure that the thickness of each film layer of first film transistor and the second thin film transistor (TFT) is in each optimal scope, solve existing
First film transistor and the second thin film transistor (TFT) incompatible problem of optimal thicknesses of layers in array base palte in technology, fully
Play first film transistor and the optimal effect in array base palte of the second thin film transistor (TFT).
Alternatively, by taking the cross-sectional view of the array base palte shown in Fig. 3 as an example, one kind provided in an embodiment of the present invention
The preparation method of array base palte, multiple first film transistors and multiple second thin film transistor (TFT)s are formed in the top of underlay substrate
While, also include：
Form multiple capacitance structures 40；
Wherein, the first of the capacitance structure 40 is formed while grid 32 of the first film transistor 30 are formed
Electrode 41；The second electrode of the capacitance structure 40 is formed while grid 51 of second thin film transistor (TFT) 50 are formed
42。
The benefit for setting capacitance structure 40 is to be conducive to driving the guarantor of current potential in order to display panel is during luminous
Hold.And the first electrode 41 of capacitance structure 40 is set with the grid 32 of first film transistor 30 with layer in the present embodiment, electricity
Hold structure 40 the thin film transistor (TFT) 50 of second electrode 42 and second grid 51 with layer set, i.e., making thin film transistor (TFT) when
Wait, while having made capacitance structure 40, reached simplification of flowsheet, the effect of reduces cost.
By taking Fig. 3 as an example, Figure 10 is a kind of schematic flow sheet of the preparation method of array base palte provided in an embodiment of the present invention.
The method for forming multiple first film transistors 30 and multiple second thin film transistor (TFT)s 50 in the top of underlay substrate 10 includes：
Step 101, cushion is formed on underlay substrate.
Cushion 11 is formed on underlay substrate 10.Underlay substrate 10 can be exemplarily flexible substrate, and material is for example
Polyimides can be selected.Exemplarily, cushion 11 can be silica and silicon nitride, or can also be silica and nitrogen
The lamination of SiClx.
Step 102, above film layer where cushion formed first film transistor active layer.
In the place film layer of cushion 11, one layer of active layer is formed, first film transistor 30 is formed by patterning
Active layer 31.
The first insulating barrier is formed above film layer where step 103, the active layer in first film transistor.
The first insulating barrier 13 is formed above the place film layer of active layer 31 of first film transistor 30.Exemplarily,
One insulating barrier 13 is the lamination of one or more inorganic material.
Step 104, above film layer where the first insulating barrier formed first film transistor grid.
The grid of first film transistor 30 is formed above the place film layer of the first insulating barrier 13.
The second insulating barrier is formed above film layer where step 105, the grid in first film transistor.
The second insulating barrier 13 is formed above the place film layer of grid 32 of first film transistor 30.
Step 106, the grid for forming above film layer where the second insulating barrier the second thin film transistor (TFT).
The grid 51 of the second thin film transistor (TFT) 50 is formed above the place film layer of the second insulating barrier 13.
Step 107, the 3rd insulating barrier of formation above film layer where the grid of the second thin film transistor (TFT).
The 3rd insulating barrier 14 is formed above the place film layer of grid 51 of the second thin film transistor (TFT) 50.3rd insulating barrier 14 is
Second thin film transistor (TFT) 50 provides grid oxide layer.
Step 108, the active layer for forming above film layer where the 3rd insulating barrier the second thin film transistor (TFT).
The active layer 52 of the second thin film transistor (TFT) 50 is formed above the place film layer of the 3rd insulating barrier 14.
Step 109, above film layer where the active layer of the second thin film transistor (TFT) formed first film transistor source and drain
The source-drain electrode of electrode and the second thin film transistor (TFT).
The source and drain electricity of first film transistor 30 is formed above the place film layer of active layer 52 of the second thin film transistor (TFT) 50
The source-drain electrode 53 of the thin film transistor (TFT) 50 of pole 33 and second.The electrode material of source-drain electrode can be Ti and Al exemplarily
It is metal laminated.
Alternatively, the 3rd insulating barrier 14 includes silicon nitride layer 140 and silicon oxide layer 141 that lamination is set；
The 3rd insulating barrier 14 is formed above the place film layer of grid 51 of the second thin film transistor (TFT) 50 to be included：In the second film
The place film layer top of grid 51 of transistor 50 sequentially forms silicon nitride layer 140 and silicon oxide layer 141, so that in the 3rd insulating barrier
The silicon oxide layer 141 contacted with the active layer 52 of the second thin film transistor (TFT) 50.
Forming the order of the 3rd insulating barrier 14 is, is initially formed silicon nitride layer 140, re-forms silica 141.Form silica
After 141, hydrogenation treatment is carried out to first film transistor in a certain temperature conditions, i.e., under conditions of high temperature, the 3rd is exhausted
Hydrogen in the silicon nitride layer 140 of edge layer 14 is activated, in the active layer 31 of High temperature diffusion to first film transistor 30.Hydrogenate
After, the active layer 52 of the second thin film transistor (TFT) 50 is re-formed.The embodiment of the present invention sets the film of silicon oxide layer 141 and second
The active layer 52 of transistor 50 is contacted, and is directly contacted with active layer 52 rather than silicon nitride layer 140, and the first film can be avoided brilliant
After the hydrogen molecule of hydrogen content silicon nitride layer 140 higher can be activated in body pipe hydrogenation process, the hydrogen ions influence second of activation
The electric property of oxide semiconductor active layer 52 in thin film transistor (TFT) 50.
Alternatively, it is square in the place film layer of active layer 52 of the second thin film transistor (TFT) 50 before step 109 referring to Fig. 1
Into before the source electrode of the thin film transistor (TFT) 50 of source-drain electrode 33 and second of first film transistor 30 and drain electrode 53, also include：
Etching barrier layer 15 is formed on the active layer 52 of the second thin film transistor (TFT) 50, etching etching barrier layer 15 was formed
Hole, so that the source-drain electrode of the second thin film transistor (TFT) is connected by via with the active layer 52 of the second thin film transistor (TFT) 50.
It is alternatively, square in the place film layer of active layer 52 of the second thin film transistor (TFT) 50 before step 109 referring to Fig. 2
Into the first film transistor 30 source-drain electrode 33 and second thin film transistor (TFT) 50 source electrode and drain electrode 53 before,
Also include：
Etching barrier layer 15 is formed on the active layer 52 of second thin film transistor (TFT) 50, so that second film is brilliant
The directly contact of active layer 52 of subregion and second thin film transistor (TFT) 50 of the source electrode leakage and pole 53 of body pipe 50.
It should be noted that being provided with the active layer 52 of the second thin film transistor (TFT) of array base palte 50 shown in Fig. 3 and Fig. 4
The effect of etching barrier layer 15 is for protecting the active layer 52 of the second thin film transistor (TFT) 50, can avoid entering source and drain metal
During row etching, corrosion of the etching liquid to active layer.
Alternatively, the material of etching barrier layer 15 includes silica.Because etching barrier layer 15 is directly brilliant with the second film
The active layer 52 of body pipe 50 is contacted, therefore it is the inorganic of representative that can choose silica in the material selection of etching barrier layer 15
Material.
Alternatively, by taking Fig. 5 as an example, after step 109, the place film layer of active layer 52 of second thin film transistor (TFT) 50
Top forms the source-drain electrode 33 of the first film transistor 30 and the source-drain electrode 53 of second thin film transistor (TFT) 50
Afterwards, also include：
In the source-drain electrode 33 and the source-drain electrode of second thin film transistor (TFT) 50 of the first film transistor 30
53 tops form protection passivation layer 17.
Alternatively, the material of the protection passivation layer 17 includes silica.
Alternatively, the protection passivation layer 17 includes silicon nitride layer 171 and silicon oxide layer 170 that lamination is set；
In the source-drain electrode 33 and the source-drain electrode of second thin film transistor (TFT) 50 of the first film transistor 30
53 tops form protection passivation layer 17 to be included：
In the source-drain electrode 33 and the source-drain electrode of second thin film transistor (TFT) 50 of the first film transistor 30
53 tops sequentially form silicon nitride layer 171 and silicon oxide layer 170；The silicon oxide layer in wherein described protection passivation layer 17
170 connect with the source-drain electrode 33 of the first film transistor 30 and the source-drain electrode 53 of second thin film transistor (TFT) 50
Touch.
Protection passivation layer have excellent heat endurance, chemical stability, water resistance, insulating properties, thermal coefficient of expansion small and
The advantages of adhesive force of organic film is extremely strong and difficult for drop-off.It should be noted that exemplarily, in the top of protection passivation layer 17
It is organic planarization layer 18, anode 19, light emitting device layer 20, pixel confining layers 21 and negative electrode 22.
Alternatively, after step 107, before step 108, in the place film of grid 51 of second thin film transistor (TFT) 50
Layer top is formed after the 3rd insulating barrier 14, and second thin film transistor (TFT) 50 is formed above the place film layer of the 3rd insulating barrier 14
Active layer 52 before, also include：Hydrogenation treatment is carried out to first film transistor in a certain temperature conditions, i.e., in high temperature
Under conditions of, the hydrogen in the silicon nitride layer 140 of the 3rd insulating barrier 14 is activated, and High temperature diffusion has to first film transistor 30
In active layer 31.After hydrogenation is completed, the active layer 52 of the second thin film transistor (TFT) 50 is re-formed.The first film crystal after hydrogenation
The electric property of pipe 30 gets a promotion.The embodiment of the present invention sets the active layer of the thin film transistor (TFT) 50 of silicon oxide layer 141 and second
52 contacts, directly contact rather than silicon nitride layer 140 with active layer 52, can avoid hydrogen in first film transistor hydrogenation process
After the hydrogen molecule of content silicon nitride layer 140 higher can be activated, oxygen in second thin film transistor (TFT) of hydrogen ions influence 50 of activation
The electric property of compound semiconductor active layer 52.
Alternatively, hydrotreated temperature is more than 300 DEG C.The hydrogen of silicon nitride is activated, can be brilliant with diffusion couple the first film
Low temperature polycrystalline silicon in body pipe is hydrogenated.
Alternatively, due to metal oxide to the temperature environment more than 350 DEG C in, easily lose semi-conducting material intrinsic
Electrology characteristic, after the active layer 52 for forming second thin film transistor (TFT) 50 above the place film layer of the 3rd insulating barrier 14
Preparation method in making temperature be less than or equal to 350 DEG C.
Alternatively, the making temperature of the silicon nitride layer 141 in protection passivation layer 17 is less than or equal to 300 DEG C.Protection passivation layer
In the 17 making temperature of silicon nitride layer 141 be less than or equal to 300 DEG C, because in the temperature environment more than 300 DEG C, silicon nitride
Middle hydrogen can be activated, the metal oxide semiconductor layer in the second thin film transistor (TFT) that easily hydrogenation closes on protection passivation layer.
Alternatively, it is bottom grating structure, the second film with first film transistor 30 by taking the array base palte shown in Fig. 6 as an example
Transistor 50 is bottom grating structure.The preparation method of the array base palte shown in Fig. 6 includes：Cushion is formed on underlay substrate 60
61；The grid 32 of first film transistor is formed above the film layer of cushion 61；In the institute of grid 32 of first film transistor 30
The 4th insulating barrier 62 is formed above film layer；Having for first film transistor 30 is formed above the place film layer of the 4th insulating barrier 62
Active layer 31；The 5th insulating barrier 63 is formed above the place film layer of active layer 31 of first film transistor 30；In the 5th insulating barrier
63 places film layer top form the grid 51 of the second thin film transistor (TFT)；In the place film layer of grid 51 of the second thin film transistor (TFT) 50
It is square into the 6th insulating barrier 64；6th insulating barrier 64 includes silicon nitride layer 640 and silicon oxide layer 641 that lamination is set, wherein oxygen
SiClx layer 641 is contacted with the active layer 52 of the second thin film transistor (TFT) 50；Second is formed above the place film layer of the 6th insulating barrier 64
The active layer 52 of thin film transistor (TFT) 50；The first film crystal is formed above the place film layer of active layer 52 of the second thin film transistor (TFT)
The source-drain electrode 53 of the thin film transistor (TFT) of source-drain electrode 33 and second of pipe.Alternatively, in the active layer of the second thin film transistor (TFT)
52 places film layers tops formed the thin film transistor (TFT) of source-drain electrode 33 and second of first film transistors source-drain electrode 53 it
Before, form etching barrier layer 66 in the top of active layer 52 of the second thin film transistor (TFT).
Alternatively, by taking the array base palte shown in Fig. 7 as an example, first film transistor 30 is bottom grating structure, and the second film is brilliant
Body pipe 50 is top gate structure.The preparation method of the array base palte shown in Fig. 7 includes：Cushion 71 is formed on underlay substrate 70；
The grid 32 of first film transistor 30 is formed above the film layer of cushion 71；Where grid 32 in first film transistor 30
Film layer top forms four-line poem with seven characters to a line edge layer 72；The active of first film transistor 30 is formed above the place film layer of four-line poem with seven characters to a line edge layer 72
Layer 31；The 8th insulating barrier 73 is formed above the place film layer of active layer 31 of first film transistor 30, the 8th insulating barrier 73 is wrapped
The silicon nitride layer 730 and silicon oxide layer 731 of lamination setting are included, wherein silicon oxide layer 731 is active with the second thin film transistor (TFT) 50
Layer 52 is contacted；The active layer 51 of the second thin film transistor (TFT) 50 is formed above the place film layer of the 8th insulating barrier 73；In the second film
The place film layer top of the active layer 51 of transistor 50 forms the 9th insulating barrier 74, and the 9th insulating barrier 74 includes the oxygen that lamination is set
SiClx layer 740 and silicon nitride layer 741, wherein silicon oxide layer 740 are contacted with the active layer 52 of the second thin film transistor (TFT) 50；
The place film layer top of 9th insulating barrier 74 of two thin film transistor (TFT)s 50 forms the grid 52 of the second thin film transistor (TFT) 50；It is thin second
The place film layer top of grid 52 of film transistor 50 forms the tenth insulating barrier 75；Formed above the place film layer of the tenth insulating barrier 75
The source-drain electrode 53 of the thin film transistor (TFT) 50 of source-drain electrode 33 and second of first film transistor 30.
Alternatively, by taking the array base palte shown in Fig. 8 as an example, first film transistor 30 is top gate structure, and the second film is brilliant
Body pipe 50 is top gate structure.The preparation method of the array base palte shown in Fig. 8 includes：Cushion 81 is formed on underlay substrate 80；
The active layer 31 of first film transistor 30 is formed above the place film layer of cushion 81；In the active of first film transistor 30
The place film layer top of layer 31 forms the 11st insulating barrier 82；The first film is formed above the place film layer of the 11st insulating barrier 82 brilliant
The grid 32 of body pipe 30；The 12nd insulating barrier 83, the tenth are formed above the place film layer of grid 32 of first film transistor 30
Two insulating barriers 83 include silicon nitride layer 830 and silicon oxide layer 831 that lamination is set, and the wherein film of silicon oxide layer 831 and second is brilliant
The active layer 52 of body pipe 50 is contacted；The active layer of the second thin film transistor (TFT) 50 is formed above the place film layer of the 12nd insulating barrier 83
52；The 13rd insulating barrier 84, the 13rd insulating barrier are formed above the place film layer of the active layer 52 of the second thin film transistor (TFT) 50
84 silicon oxide layers 840 and silicon nitride layer 841 for including lamination setting, the wherein thin film transistor (TFT) 50 of silicon oxide layer 840 and second
Active layer 52 is contacted；The second thin film transistor (TFT) is formed above the place film layer of the 13rd insulating barrier 84 of the second thin film transistor (TFT) 50
50 grid 51；The 14th insulating barrier 85 is formed above the place film layer of grid 51 of the second thin film transistor (TFT) 50；The 14th
The place film layer top of insulating barrier 85 forms the source of the thin film transistor (TFT) 50 of source-drain electrode 33 and second of first film transistor 30
Drain electrode 53.
Array base palte shown in Fig. 6, Fig. 7 and Fig. 8, and unlike the array base palte shown in Fig. 6, the first film crystal
The selection of the top-gated and bottom gate of the thin film transistor (TFT) 50 of pipe 30 and second is different, and the thing followed is then, capacitance structure 40 with
And the parasitic capacitance of thin film transistor (TFT) has difference.Common ground is then, due to the film crystal of first film transistor 30 and second
The same layer of grid of pipe 50, source-drain electrode is also same layer, and the grid of the thin film transistor (TFT) 50 of first film transistor 30 and second is located at
Different layers, while source-drain electrode is located at same layer, it is ensured that each film of the thin film transistor (TFT) 50 of first film transistor 30 and second
The thickness of layer is in each optimal scope, can so give full play to the thin film transistor (TFT) of first film transistor 30 and second
50 optimal effects in array base palte, it is unaffected each other.It should be noted that the array shown in Fig. 6, Fig. 7 and Fig. 8
Exemplarily, first electrode 41 is set capacitance structure 40 in substrate with the grid 32 of first film transistor 30 with layer, electric capacity
The grid 51 of the thin film transistor (TFT) 50 of second electrode 42 and second of structure 40 is set with layer.Related practitioner can also be according to reality
Border needs other metal levels in two electrodes and array base palte by capacitance structure 40 to be made with layer, herein and is not construed as limiting.
By the metal level of two electrodes of capacitance structure 40 and array base palte with layer make be for Simplified flowsheet, it is cost-effective.As for
The metal level made with layer with electrode selection can the size of electric capacity according to needed for array base palte voluntarily select.When selection
From two electrodes of capacitance structure with the metal level that layer makes it is different when, the distance between two electrodes of capacitance structure can be caused
Difference, so as to influence the size of capacitance.
A kind of array base palte provided in an embodiment of the present invention and preparation method thereof, forms many by the top of underlay substrate
Individual first film transistor and multiple second thin film transistor (TFT)s.First film transistor is located at the periphery circuit region of array base palte,
Be used to provide clock signal for drive circuit, the wherein active layer of first film transistor is low temperature polycrystalline silicon, such thin
Film transistor electron mobility is higher, and it is high to meet display device periphery circuit region electron mobility, the fast requirement of electric property.The
Two thin film transistor (TFT)s are located at the viewing area of array base palte, for providing drive signal for viewing area.Second thin film transistor (TFT) has
Active layer is oxide semiconductor, with carrier mobility is higher, electric property homogeneity is good, can meet display device and show
Area's demand high for device stability, it is low to visible transparent, technological temperature and can large-area manufacturing the advantages of, by metal oxygen
Compound thin film transistor (TFT) is applied to the viewing area of array base palte, can effectively improve the picture element density of viewing area, aperture opening ratio and
Brightness, while the display quality of display panel can also be improved by improving the stability of metal oxide thin-film transistor, keeps away
Exempt from the problems such as damaged picture or brightness irregularities occur.During making, by the grid of first film transistor and second
The grid of thin film transistor (TFT) be located at different layers, and the grid of first film transistor and the second thin film transistor (TFT) source-drain electrode position
In same layer.Can ensure that the thickness of each film layer of first film transistor and the second thin film transistor (TFT) is in each optimal model
Enclose, solve first film transistor in the prior art and the second thin film transistor (TFT) optimal thicknesses of layers in array base palte not simultaneous
The problem of appearance, gives full play to first film transistor and the optimal effect in array base palte of the second thin film transistor (TFT).
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various obvious changes,
Readjust and substitute without departing from protection scope of the present invention.Therefore, although the present invention is carried out by above example
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
More other Equivalent embodiments can be included, and the scope of the present invention is determined by scope of the appended claims.
Claims (26)
1. a kind of array base palte, it is characterised in that including：
Underlay substrate；
Multiple first film transistors and multiple second thin film transistor (TFT)s；The first film transistor and second film are brilliant
Body pipe is formed at the top of the underlay substrate；The active layer of the first film transistor is low temperature polycrystalline silicon, described second
The active layer of thin film transistor (TFT) is oxide semiconductor；The first film transistor is located at the peripheral circuit of the array base palte
Area, second thin film transistor (TFT) is located at the viewing area of the array base palte；
The grid of the grid of the first film transistor and second thin film transistor (TFT) is located at different layers, and described first thin
The source-drain electrode of the source-drain electrode of film transistor and second thin film transistor (TFT) is located at same layer.
2. array base palte according to claim 1, it is characterised in that also include：
Multiple capacitance structures；
Wherein, the first electrode of the capacitance structure is set with the grid of the first film transistor with layer, the capacitive junctions
The second electrode of structure is set with the grid of second thin film transistor (TFT) with layer.
3. array base palte according to claim 1, it is characterised in that be disposed with the underlay substrate cushion,
The active layer of the first film transistor, the first insulating barrier, the grid of the first film transistor, the second insulating barrier, institute
State grid, the 3rd insulating barrier, the active layer of second thin film transistor (TFT), the first film crystal of the second thin film transistor (TFT)
The source-drain electrode of the source-drain electrode of pipe and second thin film transistor (TFT).
4. array base palte according to claim 3, it is characterised in that the 3rd insulating barrier includes the nitridation that lamination is set
Silicon layer and silicon oxide layer；The silicon oxide layer that wherein described 3rd insulating barrier includes connects with the active layer of second thin film transistor (TFT)
Touch.
5. array base palte according to claim 3, it is characterised in that the active layer of second thin film transistor (TFT) and described
Etching barrier layer is provided between the source-drain electrode of the second thin film transistor (TFT)；
The etching barrier layer is provided with via, and the source-drain electrode of second thin film transistor (TFT) is by the via and described the
The active layer connection of two thin film transistor (TFT)s.
6. array base palte according to claim 3, it is characterised in that set on the active layer of second thin film transistor (TFT)
There is etching barrier layer；
The subregion of the source-drain electrode of second thin film transistor (TFT) directly connects with the active layer of second thin film transistor (TFT)
Touch.
7. the array base palte according to claim 5 or 6, it is characterised in that the material of the etching barrier layer includes oxidation
Silicon.
8. array base palte according to claim 3, it is characterised in that the source-drain electrode of the first film transistor and
Protection passivation layer is provided with the source-drain electrode of second thin film transistor (TFT).
9. array base palte according to claim 8, it is characterised in that the material of the protection passivation layer includes silica.
10. array base palte according to claim 8, it is characterised in that the protection passivation layer includes the nitrogen that lamination is set
SiClx layer and silicon oxide layer；The source-drain electrode of wherein described silicon oxide layer and the first film transistor and described second thin
The source-drain electrode contact of film transistor.
11. array base paltes according to claim 4, it is characterised in that
The thickness range of silicon nitride layer described in 3rd insulating barrier is 50~400nm.
12. array base paltes according to claim 4, it is characterised in that
The thickness range of silicon oxide layer described in 3rd insulating barrier is 30~200nm.
13. array base palte according to claim 1, it is characterised in that
The thickness of the active layer of second thin film transistor (TFT) is 20~100nm.
14. array base palte according to claim 5 or 6, it is characterised in that
The thickness of the etching barrier layer is 50~250nm.
15. array base paltes according to claim 1, it is characterised in that
The first film transistor is bottom grating structure, and second thin film transistor (TFT) is bottom grating structure；Or it is described first thin
Film transistor is bottom grating structure, and second thin film transistor (TFT) is top gate structure；Or the first film transistor is top-gated
Structure, second thin film transistor (TFT) is top gate structure.
16. a kind of display panels, it is characterised in that including the array base palte any one of claim 1-15.
17. display panels according to claim 16, it is characterised in that the display panel includes organic light emitting display face
Plate or liquid crystal display panel.
A kind of 18. preparation methods of array base palte, it is characterised in that including：
Multiple first film transistors and multiple second thin film transistor (TFT)s are formed in the top of underlay substrate；
Wherein, the active layer of the first film transistor is low temperature polycrystalline silicon, and the active layer of second thin film transistor (TFT) is
Oxide semiconductor；The first film transistor is located at the periphery circuit region of the array base palte, second film crystal
Pipe is positioned at the viewing area of the array base palte；
The grid of the grid of the first film transistor and second thin film transistor (TFT) is located at different layers, and described first thin
The source-drain electrode of the grid of film transistor and second thin film transistor (TFT) is located at same layer.
19. preparation methods according to claim 18, it is characterised in that form multiple first in the top of underlay substrate thin
While film transistor and multiple second thin film transistor (TFT)s, also include：
Form multiple capacitance structures；
Wherein, the first electrode of the capacitance structure is formed while the grid of the first film transistor is formed；In shape
Into second thin film transistor (TFT) grid while form the second electrode of the capacitance structure；Forming the first film crystal
The source-drain electrode of second thin film transistor (TFT) is formed while the source-drain electrode of pipe.
20. preparation methods according to claim 18, it is characterised in that form multiple first in the top of underlay substrate thin
Film transistor and multiple second thin film transistor (TFT)s include：
Cushion is formed on the underlay substrate；
The active layer of the first film transistor is formed above film layer where the cushion；
The first insulating barrier is formed above film layer where the active layer of the first film transistor；
The grid of the first film transistor is formed above film layer where first insulating barrier；
The second insulating barrier is formed above film layer where the grid of the first film transistor；
The grid of second thin film transistor (TFT) is formed above film layer where second insulating barrier；
The 3rd insulating barrier is formed above film layer where the grid of second thin film transistor (TFT)；
The active layer of second thin film transistor (TFT) is formed above film layer where the 3rd insulating barrier；
The source-drain electrode of the first film transistor is formed above film layer where the active layer of second thin film transistor (TFT)
And the source-drain electrode of second thin film transistor (TFT).
21. preparation methods according to claim 20, it is characterised in that where the grid of second thin film transistor (TFT)
Film layer top is formed after the 3rd insulating barrier, and second thin film transistor (TFT) is formed above film layer where the 3rd insulating barrier
Active layer before, also include：
Carry out hydrogenation treatment.
22. preparation methods according to claim 21, it is characterised in that
The hydrotreated temperature is more than 300 DEG C.
23. preparation methods according to claim 20, it is characterised in that
Preparation method after the active layer that second thin film transistor (TFT) is formed above the film layer where the 3rd insulating barrier
In making temperature be less than or equal to 350 DEG C.
24. methods according to claim 18, it is characterised in that form multiple the first films in the top of underlay substrate brilliant
Body pipe and multiple second thin film transistor (TFT)s include：
The first film transistor is bottom grating structure, and second thin film transistor (TFT) is bottom grating structure；
Cushion is formed on the underlay substrate；
The grid of the first film transistor is formed above film layer described in the cushion；
The 4th insulating barrier is formed above film layer where the grid of the first film transistor；
The active layer of the first film transistor 30 is formed above film layer where the 4th insulating barrier；
The 5th insulating barrier is formed above film layer where the active layer of the first film transistor；
The grid of second thin film transistor (TFT) is formed above film layer where the 5th insulating barrier；
The 6th insulating barrier is formed above film layer where the grid of second thin film transistor (TFT)；
The active layer of second thin film transistor (TFT) is formed above film layer where the 6th insulating barrier；
The source-drain electrode of the first film transistor is formed above film layer where the active layer of second thin film transistor (TFT)
And the source-drain electrode of second thin film transistor (TFT).
25. methods according to claim 18, it is characterised in that form multiple the first films in the top of underlay substrate brilliant
Body pipe and multiple second thin film transistor (TFT)s include：
The first film transistor is bottom grating structure, and second thin film transistor (TFT) is top gate structure；
Cushion is formed on the underlay substrate；
The grid of the first film transistor is formed above film layer described in the cushion；
Four-line poem with seven characters to a line edge layer is formed above film layer where the grid of the first film transistor；
The active layer of the first film transistor 30 is formed above film layer where the four-line poem with seven characters to a line edge layer；
The 8th insulating barrier is formed above film layer where the active layer of the first film transistor；
The active layer of second thin film transistor (TFT) is formed above film layer where the 8th insulating barrier；
The 9th insulating barrier is formed above the place film layer of the active layer of second thin film transistor (TFT)；
The grid of second thin film transistor (TFT) is formed above film layer where the 9th insulating barrier of second thin film transistor (TFT)；
The tenth insulating barrier is formed above film layer where the grid of second thin film transistor (TFT)；
The source-drain electrode 33 and described of the first film transistor is formed above film layer where the tenth insulating barrier
The source-drain electrode of two thin film transistor (TFT)s.
26. methods according to claim 18, it is characterised in that form multiple the first films in the top of underlay substrate brilliant
Body pipe and multiple second thin film transistor (TFT)s include：
The first film transistor is top gate structure, and second thin film transistor (TFT) is top gate structure；
Cushion is formed on the underlay substrate；
The active layer of the first film transistor is formed above film layer where the cushion；
The 11st insulating barrier is formed above film layer where the active layer of the first film transistor；
The grid of the first film transistor is formed above film layer where the 11st insulating barrier；
The 12nd insulating barrier is formed above film layer where the grid of the first film transistor；
The active layer of second thin film transistor (TFT) is formed above film layer where the 12nd insulating barrier；
The 13rd insulating barrier is formed above the place film layer of the active layer of second thin film transistor (TFT)；
The grid of second thin film transistor (TFT) are formed above film layer where the 13rd insulating barrier of second thin film transistor (TFT)
Pole；
The 14th insulating barrier is formed above film layer where the grid of second thin film transistor (TFT)；
The source-drain electrode and described of the first film transistor is formed above film layer where the 14th insulating barrier
The source-drain electrode of two thin film transistor (TFT)s.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1278660A (en) * | 1999-06-04 | 2001-01-03 | 株式会社半导体能源研究所 | Photoelectric apparatus and electronic apparatus |
| US20060138416A1 (en) * | 2004-12-24 | 2006-06-29 | Park Yong I | Liquid crystal display device and method of fabricating the same |
| CN102135693A (en) * | 2010-01-21 | 2011-07-27 | 点晶科技股份有限公司 | Three-dimensional grid control type liquid crystal lens and manufacturing method thereof |
| CN106067466A (en) * | 2015-04-20 | 2016-11-02 | 乐金显示有限公司 | Thin film transistor base plate and manufacture method thereof |
-
2017
- 2017-03-15 CN CN201710153697.XA patent/CN106876412A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1278660A (en) * | 1999-06-04 | 2001-01-03 | 株式会社半导体能源研究所 | Photoelectric apparatus and electronic apparatus |
| US20060138416A1 (en) * | 2004-12-24 | 2006-06-29 | Park Yong I | Liquid crystal display device and method of fabricating the same |
| CN102135693A (en) * | 2010-01-21 | 2011-07-27 | 点晶科技股份有限公司 | Three-dimensional grid control type liquid crystal lens and manufacturing method thereof |
| CN106067466A (en) * | 2015-04-20 | 2016-11-02 | 乐金显示有限公司 | Thin film transistor base plate and manufacture method thereof |
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