CN106816416B - Semiconductor embedded hybrid packaging structure and manufacturing method thereof - Google Patents
Semiconductor embedded hybrid packaging structure and manufacturing method thereof Download PDFInfo
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- CN106816416B CN106816416B CN201510845904.9A CN201510845904A CN106816416B CN 106816416 B CN106816416 B CN 106816416B CN 201510845904 A CN201510845904 A CN 201510845904A CN 106816416 B CN106816416 B CN 106816416B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 72
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 36
- 239000005022 packaging material Substances 0.000 claims abstract description 36
- 238000009825 accumulation Methods 0.000 claims description 87
- 229910000679 solder Inorganic materials 0.000 claims description 35
- 239000000463 material Substances 0.000 claims description 33
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 24
- 229910052802 copper Inorganic materials 0.000 claims description 24
- 239000010949 copper Substances 0.000 claims description 24
- 239000002313 adhesive film Substances 0.000 claims description 19
- 239000003989 dielectric material Substances 0.000 claims description 17
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000010931 gold Substances 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 8
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- 239000004642 Polyimide Substances 0.000 claims description 6
- 239000003990 capacitor Substances 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- 239000004033 plastic Substances 0.000 claims description 5
- 230000008569 process Effects 0.000 abstract description 19
- 230000010354 integration Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 27
- 150000001875 compounds Chemical class 0.000 description 9
- 238000005530 etching Methods 0.000 description 8
- 238000007747 plating Methods 0.000 description 8
- 238000005538 encapsulation Methods 0.000 description 7
- 238000000465 moulding Methods 0.000 description 5
- 239000007888 film coating Substances 0.000 description 4
- 238000009501 film coating Methods 0.000 description 4
- 238000003475 lamination Methods 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses a semiconductor embedded hybrid packaging structure and a manufacturing method thereof, wherein the packaging structure comprises: the circuit board is provided with a first surface and a second surface which are oppositely arranged; an opening or cavity arranged in the circuit board and at least used for accommodating a Semiconductor chip (Bar Die) and a Semiconductor chip Package (Semiconductor Package); a semiconductor chip disposed in the opening or cavity; a semiconductor chip package disposed within the opening or cavity; the packaging material is at least used for covering the first surface of the circuit board and filling the space which is not occupied by the semiconductor chip and the semiconductor chip packaging body in the opening or the cavity; and a rewiring layer at least for electrically connecting the semiconductor chip, the semiconductor chip package and the wiring board. The semiconductor embedded hybrid packaging structure and the manufacturing method thereof adopt the technical scheme of circuit board embedding, can simplify the integration process flow of the semiconductor chip and the semiconductor chip packaging body, improve the integration quality and performance, and effectively reduce the integration area.
Description
Technical Field
The present invention relates to a circuit carrier package structure, and more particularly, to a semiconductor embedded hybrid package structure and a method for fabricating the same.
Background
In the prior art, the packaging of the semiconductor chip and the assembly of the semiconductor chip package are respectively completed by an electronic packaging factory and an electronic assembly factory, and the packaging of the semiconductor chip is firstly completed, and then the assembly of the semiconductor chip package is performed on the circuit board. The assembly of semiconductor chip packages on a wiring board is typically accomplished by a surface mount process.
Surface Mount Technology (SMT) is a circuit connecting technique in which a Surface-mounted device (SMC/SMD, or chip device in chinese) having no leads or short leads is mounted on a Surface of a Printed Circuit Board (PCB) or other substrate, and is soldered and assembled by a method such as reflow soldering or dip soldering. The surface mounting technology has high assembly density, small volume of electronic products and light weight, the volume and the weight of a patch element are only about 1/10 of the traditional plug-in element, and after the SMT is generally adopted, the volume of the electronic products is reduced by 40-60 percent, and the weight is reduced by 60-80 percent. The assembly of the semiconductor package device on the circuit board is usually accomplished by surface mounting engineering, in which the semiconductor package device and the circuit board are electrically interconnected by solder connections.
However, the semiconductor chip and the package between the semiconductor chip package and the circuit board in the prior art have the following disadvantages:
the butt joint standard and the process between the semiconductor chip/semiconductor chip packaging body and the circuit board are complex and tedious;
generally, a semiconductor chip is mounted/soldered on a printed circuit board after being converted into a semiconductor package device through a packaging process. In addition, in surface mounting, a semiconductor chip package and a circuit board are usually electrically interconnected through solder connection, the solder connection of the current surface mounting needs a larger pad-to-pad distance (pitch) of a semiconductor package device, for example, the pad-to-pad distance is 280 micrometers/400 micrometers, precision needs to be improved, and the solder connection needs to be controlled by a more complex solder reflow process;
in addition, the semiconductor chip package is assembled on the circuit board by surface mounting, and the semiconductor chip package occupies a larger surface area of the circuit board due to the increased area of the semiconductor chip package, which hinders the miniaturization development of the semiconductor package device.
Therefore, it is desirable to provide a new semiconductor embedded hybrid package structure and a method for fabricating the same to solve the above-mentioned problems.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a semiconductor embedded hybrid packaging structure and a manufacturing method thereof, which can effectively solve the problems of large distance between a bonding pad and a bonding pad of a semiconductor chip packaging body and miniaturization of the packaging structure.
In order to solve the above technical problem, a technical solution adopted by the present invention is to provide a semiconductor embedded hybrid package structure, wherein the package structure includes:
the circuit board is provided with a first surface and a second surface which are oppositely arranged;
an opening or cavity in the circuit board for accommodating at least the semiconductor chip and the semiconductor chip package;
a semiconductor chip disposed within the opening or cavity;
a semiconductor chip package disposed within the opening or cavity;
the packaging material is at least used for covering the first surface of the circuit board and filling the space which is not occupied by the semiconductor chip and the semiconductor chip packaging body in the opening or the cavity;
and a rewiring layer at least for electrically connecting the semiconductor chip, the semiconductor chip package and the wiring board.
In a preferred embodiment, a module alignment mark is disposed on the first surface of the circuit board, and a surface of the module alignment mark and the second surface of the circuit board correspond to the highest surface and the lowest surface of the circuit board, respectively.
In a preferred embodiment, a passive electronic element is further disposed in the opening or the cavity, and the passive electronic element includes any one or a combination of a capacitor, a resistor and an inductor.
In a preferred embodiment, the semiconductor chip package has at least one semiconductor bare chip therein and is a semiconductor chip package with a molding compound package.
Further, the semiconductor chip package includes conductive leads or wires electrically connected to the electrodes/pads of the semiconductor bare chip in the semiconductor chip package and extending outward from the semiconductor bare chip.
Further, the semiconductor chip package further includes an external electrode electrically connected to the semiconductor bare chip, the external electrode being exposed to air or covered with a film; the external electrode is made of a copper metal layer or a copper metal layer covered by a nickel/gold layer; the film is made of an accumulation layer dielectric material, including a plastic package material, a layer increasing material or polyimide.
Further, the encapsulation material also serves to fill the space inside the opening or cavity that is not occupied by passive electronic components.
In a preferred embodiment, the package structure further comprises a first accumulation layer at least covering the second surface of the circuit board, the packaging material, the semiconductor chip, and the semiconductor chip package; the first accumulation layer is a dielectric material layer and comprises an ABF build-up layer or a photosensitive dielectric layer.
Furthermore, the first accumulation layer is provided with blind holes above the electrode/bonding pad of the semiconductor chip, the external electrode of the semiconductor chip packaging body and the circuit layer of the circuit board; and the first redistribution layer on the first accumulation layer is electrically interconnected with the electrode/bonding pad of the semiconductor chip, the external electrode of the semiconductor chip packaging body and/or the circuit layer on the circuit board through the blind hole.
Further, a second rewiring layer is arranged on the packaging material on the first surface of the circuit board, and the second rewiring layer is at least electrically interconnected with the circuit layer on the circuit board, the semiconductor chip and/or the external electrode of the semiconductor chip packaging body through the conductive blind holes.
Further, the first rewiring layer and/or the second rewiring layer are/is covered with a second accumulation layer, a third rewiring layer electrically interconnected with the first rewiring layer and/or the second rewiring layer is formed on the second accumulation layer, and the second accumulation layer comprises an ABF build-up layer or a photosensitive dielectric layer.
Further, the packaging structure also comprises a solder mask at least covering the outermost circuit layer and an opening arranged in the solder mask; the wiring layer in the mask opening forms a pad for connecting an external element.
Further, the packaging structure further comprises a semiconductor packaging device and/or a passive electronic element above the mounting solder mask, wherein the passive electronic element comprises any one or combination of a capacitor element, a resistor element and an inductance element, and the semiconductor packaging device and/or the passive electronic element are electrically interconnected through the bonding pad and the third redistribution layer.
In another technical solution adopted by the present invention, a method for manufacturing a semiconductor embedded hybrid package structure is provided, the method comprising the steps of:
s1, providing a circuit board, wherein the circuit board is provided with a first surface and a second surface which are oppositely arranged, and the circuit board is provided with an opening or a cavity which is at least used for accommodating the semiconductor chip and the semiconductor chip packaging body;
s2, attaching an adhesive film on the second surface of the circuit board, placing the semiconductor chip and the semiconductor chip package into the opening or the cavity, and adhering and fixing the semiconductor chip and the semiconductor chip package with the adhesive film;
s3, applying packaging materials on at least the first surface of the circuit board and the opening or the cavity, enabling the first surface of the circuit board to be covered by the packaging materials, and enabling the opening or the cavity to be completely filled by the packaging materials, the semiconductor chip and the semiconductor chip packaging body;
s4, removing the adhesive film and turning over the circuit board;
s5, covering more than one accumulation layer on the second surface of the circuit board, the semiconductor chip packaging body and the packaging material surface coplanar with the second surface of the circuit board;
and S6, forming a rewiring layer at least for electrically connecting the semiconductor chip, the semiconductor chip package and the circuit board on the accumulation layer.
In another technical solution adopted by the present invention, the step S6 includes:
arranging blind holes on a first accumulation layer positioned above an electrode/bonding pad of a semiconductor chip, an external electrode of a semiconductor chip packaging body and a circuit layer of a circuit board, and forming a first rewiring layer which is electrically interconnected with the electrode/bonding pad of the semiconductor chip, the external electrode of the semiconductor chip packaging body and/or the circuit layer on the circuit board through the blind holes;
arranging a second rewiring layer on the packaging material on the first surface of the circuit board; the second redistribution layer is electrically interconnected with the circuit layer on the circuit board, the semiconductor chip, and/or the external electrode of the semiconductor chip package via the conductive blind via;
a second accumulation layer is formed on the first redistribution layer and/or the second redistribution layer, a conductive blind via is provided on the second accumulation layer, and a third redistribution layer electrically connecting the first redistribution layer and/or the second redistribution layer via the conductive blind via is formed.
Further, after the step S6, the method further includes:
forming a solder mask on the outermost circuit layer of the packaging structure, and opening the solder mask above the circuit layer to form a corresponding pad;
and mounting a semiconductor packaging device and/or a passive electronic element above the solder mask, wherein the semiconductor packaging device and/or the passive electronic element are electrically interconnected with the third redistribution layer through the bonding pad.
Compared with the prior art, the invention has at least the following advantages:
the semiconductor chip and the semiconductor packaging body are packaged and processed on the circuit board at the same time, so that the complex and fussy standard and process butt joint of the semiconductor chip and the semiconductor packaging body in the prior art are omitted, the circulation transfer of electronic manufacturing is reduced, manpower and material resources are saved, and the cost of electronic products can be further reduced;
the electrical connection of the semiconductor chip and the circuit board and the electrical connection of the semiconductor chip package and the circuit board do not need a soldering tin connection scheme, but adopt a simple copper Redistribution (RDL) scheme, so that the process is stable and the reliability is high;
the requirements for assembling more precise semiconductor chips and semiconductor chip packages can be met, for example, the pad/pad pitch of the semiconductor chip or semiconductor chip package can be reduced to below 150 micrometers/200 micrometers;
the embedded assembly of the semiconductor chip and the semiconductor chip packaging body enables the surface area of the circuit board to be fully released, the assembly area of a system can be greatly reduced, and the reduction ratio can exceed 50%.
Drawings
FIG. 1 is a schematic structural diagram of a semiconductor embedded hybrid package structure according to a preferred embodiment of the present invention;
fig. 1a to 1m are process step diagrams of a method for manufacturing a semiconductor embedded hybrid package structure in a preferred embodiment of the invention, wherein:
FIG. 1a is a schematic structural diagram of a circuit board according to a preferred embodiment of the present invention;
FIG. 1b is a schematic view of the mounting of a semiconductor chip and a semiconductor chip package in a preferred embodiment of the present invention;
FIG. 1c is a schematic diagram of a semiconductor chip package according to a preferred embodiment of the present invention;
FIG. 1d is a schematic view of a semiconductor chip and a semiconductor chip package after mounting in accordance with a preferred embodiment of the present invention;
FIG. 1e is a schematic diagram of a package structure including a packaging material according to a preferred embodiment of the present invention;
FIG. 1f is a schematic diagram of a flip-chip package structure of a circuit board including a packaging material according to a preferred embodiment of the present invention;
FIG. 1g is a schematic diagram of a package structure including a first accumulation layer according to a preferred embodiment of the present invention;
FIG. 1h is a schematic diagram of a package structure with blind vias on the first buildup layer and the packaging material in accordance with a preferred embodiment of the present invention;
FIG. 1i is a schematic diagram of a package structure including a first redistribution layer and a second redistribution layer in a preferred embodiment of the present invention;
FIG. 1j is a schematic diagram of a package structure including a second accumulation layer according to a preferred embodiment of the invention;
FIG. 1k is a diagram of a package structure including a third redistribution layer in accordance with a preferred embodiment of the present invention;
FIG. 1l is a schematic diagram of a package structure including a solder mask in accordance with a preferred embodiment of the present invention;
FIG. 1m is a schematic structural diagram of a semiconductor chip and a semiconductor chip package embedded in a package for completing surface mounting of a passive component according to a preferred embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a semiconductor embedded hybrid package structure according to another preferred embodiment of the present invention;
fig. 2a to 2l are process step diagrams of a method for manufacturing a semiconductor embedded hybrid package structure according to another preferred embodiment of the present invention, wherein:
FIG. 2a is a schematic structural diagram of a circuit board according to another preferred embodiment of the present invention;
FIG. 2b is a schematic view of the mounting of a semiconductor chip, a semiconductor chip package and passive electronic components in another preferred embodiment of the present invention;
FIG. 2c is a schematic diagram of a package structure of a semiconductor chip, a semiconductor chip package and a passive electronic component after being mounted according to another preferred embodiment of the present invention;
FIG. 2d is a schematic diagram of a package structure including an encapsulating material according to another preferred embodiment of the present invention;
FIG. 2e is a schematic diagram of a circuit board with an inverted packaging structure including packaging material according to another preferred embodiment of the present invention;
FIG. 2f is a schematic diagram of a package structure including a first accumulation layer according to another preferred embodiment of the present invention;
FIG. 2g is a schematic diagram of a package structure with blind vias on the first buildup layer and the package material according to another preferred embodiment of the present invention;
FIG. 2h is a schematic diagram of a package structure including a first redistribution layer and a second redistribution layer in accordance with another preferred embodiment of the present invention;
FIG. 2i is a schematic diagram of a package structure including a second accumulation layer according to another preferred embodiment of the present invention;
FIG. 2j is a diagram of a package structure including a third redistribution layer according to another preferred embodiment of the present invention;
FIG. 2k is a schematic diagram of a package structure including a solder mask in accordance with another preferred embodiment of the present invention;
fig. 2l is a schematic structural diagram of a semiconductor chip and a semiconductor chip package embedded package to complete surface mounting of a passive component in another preferred embodiment of the present invention.
The parts in the drawings are numbered as follows: 1-a wiring board, 11-a first surface, 12-a second surface, 13-a wiring layer, 2-an opening or cavity, 21-a first space, 22-a second space, 31-a semiconductor chip, 32-a semiconductor chip package, 321-a semiconductor bare chip, 322-a mold compound, 323-an internal conductive lead or wiring, 324-an external electrode, 4-a package compound, 5-a module alignment mark, 6-a rewiring layer, 61-a first rewiring layer, 62-a second rewiring layer, 63-a third rewiring layer, 7-a passive electronic component, 81-a first accumulation layer, 82-a second accumulation layer, 811, 812, 813-an opening, 10-a solder mask, 101-a semiconductor package device and/or a passive electronic component, 201-adhesive film.
Detailed Description
The following detailed description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, will make the advantages and features of the invention easier to understand by those skilled in the art, and thus will clearly and clearly define the scope of the invention.
In an embodiment of the present invention, referring to fig. 1, a semiconductor embedded hybrid package structure specifically includes:
a wiring board 1, namely a wiring carrier board for packaging a Semiconductor chip (Bare Die) and a Semiconductor chip Package (Semiconductor Package), having a first surface 11 and a second surface 12 which are oppositely arranged;
at least one opening or cavity 2 for receiving a semiconductor chip 31 and at least one semiconductor chip package 32, which are disposed in the circuit board 1;
a semiconductor chip 31 and a semiconductor chip package 32 disposed in the opening or cavity 2;
an encapsulation material 4 at least for covering the first surface 11 of the circuit board, the module alignment mark 5 and filling the opening or the space inside the cavity 2 not occupied by the semiconductor chip 31 and the semiconductor chip package 32;
and a rewiring layer 6 for electrically connecting at least the semiconductor chip 31, the semiconductor chip package 32, and the wiring board 1.
Referring to fig. 1a and 1b, a first surface 11, a second surface 12, and a region between the first surface 11 and the second surface 12 of the circuit board are respectively provided with a circuit layer 13, the module alignment mark 5 is disposed on the first surface of the circuit board 1, and the surface of the module alignment mark 5 and the second surface of the circuit board respectively correspond to the highest surface and the lowest surface of the circuit board. The module alignment mark 5 is used to realize precise semiconductor chip, semiconductor chip package arrangement and conductive circuit interconnection, and all or part of the marks can simultaneously become connecting circuits and provide conductive functions.
The highest surface and the lowest surface of the opening or the cavity 2 in the vertical direction are respectively the highest surface of the circuit board 1 or the surface of the module alignment mark 5 and the second surface 12 of the circuit board 1 or the lowest surface thereof, and the boundary of the opening or cavity 2 in the horizontal direction is the side wall of the opening or cavity 2 between the first surface 11 and the second surface 12 of the circuit board 1, and the opening or cavity 2 includes a first space 21 and a second space 22, wherein said first space 21 is distributed between the first surface 11 and the second surface 12 of said wiring board 1, the second space 22 is distributed between the first surface 11 of the circuit board 1 and the surface of the module alignment mark 5, and the side wall of the first space 21 is a continuous section of the circuit board 1 between the first surface 11 and the second surface 12 of the circuit board, while the second space 21 has no side wall.
Referring to fig. 1c, the semiconductor chip package 32 has at least one semiconductor bare chip 321 therein. The bare semiconductor wafer is a type of semiconductor device that is manufactured by etching, wiring, and the like on a semiconductor wafer and can realize a specific function. The bare semiconductor chip 321 is mold-packaged with the mold material 322 to obtain the semiconductor chip package 32. The semiconductor chip package 32 is disposed in the opening or cavity 2, the semiconductor chip package 32 includes a package inner conductive lead or wire 323 and an outer electrode 324 electrically connected to the electrode/pad of the semiconductor bare chip 321 in the semiconductor chip package and extending outward from the semiconductor bare chip 321, and the outer electrode 324 is electrically interconnected with the electrode/pad on the semiconductor bare chip 321 in the semiconductor chip package via the inner conductive lead or wire. The external electrode 324 of the semiconductor chip package may be a metallic copper layer or a metallic copper layer covered with a nickel/gold layer. The semiconductor chip package 32 may be a semiconductor chip package having a package structure of InFO, WLCSP, eWLB, FOWLP, FC-BGA, FC-CSP, WB-BGA, QFN, or the like.
Further, the external electrode 324 of the semiconductor chip package 32 in the present invention is exposed in the air or covered with a film; the external electrode 324 is a copper metal layer or a copper metal layer covered by a nickel/gold layer; the film is made of an accumulation layer dielectric material, and can be a plastic packaging material, a layer increasing material, or other accumulation layer dielectric materials such as Polyimide (Polyimide).
As in this embodiment, the package structure further includes a first accumulation layer 81 covering at least the second surface 12 of the wiring board 1, the encapsulating material 4, the semiconductor chip 31, and the semiconductor chip package 32; the first build-up layer 81 is a dielectric material layer, including an ABF build-up layer, a photosensitive dielectric layer, or other dielectric material layer.
As shown in fig. 1i, the first accumulation layer 81 has blind holes above the circuit layers of the semiconductor chip, the external electrode of the semiconductor chip package, and the circuit board; the first redistribution layer 61 is arranged on the first accumulation layer, and the first redistribution layer 61 on the first accumulation layer 81 is electrically interconnected with the semiconductor chip, the external electrode of the semiconductor chip package and the circuit layer on the circuit board through the blind hole. A second redistribution layer 62 is also provided on the encapsulation material 4 on the first surface 11 of the wiring board, the second redistribution layer 62 being electrically interconnected with the wiring layer on the wiring board, the semiconductor chip, and/or the semiconductor chip package external electrode 324 via the conductive blind via.
Further, as shown in fig. 1j and 1k, the first redistribution layer 61 and the second redistribution layer 62 are covered with a second accumulation layer 82, and the second accumulation layer 82 is formed with a third redistribution layer 63 electrically interconnected with the first redistribution layer and the second redistribution layer, respectively, wherein the second accumulation layer is an ABF build-up layer, a photosensitive dielectric layer, or other dielectric material layer.
In addition, the packaging structure further comprises a solder mask 10 at least covering the outermost circuit layer, an opening of the solder mask arranged above the outermost circuit layer, a pad formed in the opening, and other semiconductor packaging devices and/or passive electronic components 101 attached above the solder mask 10, wherein the passive electronic components include but are not limited to capacitors, resistors, inductors and the like, and the semiconductor packaging devices and/or passive electronic components 101 are electrically interconnected with the third redistribution layer through the pad. In this embodiment, the first accumulation layer and the second accumulation layer are both illustrated by using an ABF build-up layer as an example, and in other embodiments, the first accumulation layer and the second accumulation layer may be other dielectric material layers.
The above-described embodiment is only one preferred embodiment of the present invention, and it should be understood that in other embodiments, the first accumulation layer, the second accumulation layer, the first rewiring layer, the second rewiring layer, and the third rewiring layer may be selectively provided, such as only the first accumulation layer, the first rewiring layer, and the second rewiring layer; in addition, other interconnection layers for electrical connection may be further provided in addition to the accumulation layer and the redistribution layer, so long as other semiconductor package devices and/or package structures for electrically connecting the passive electronic element 101 with the semiconductor chip, the semiconductor chip package, or the circuit board are achieved, and all fall within the scope of the present invention.
The invention also provides a manufacturing method of the semiconductor embedded hybrid packaging structure, which comprises the following steps:
s1, providing a circuit board, wherein the circuit board is provided with a first surface and a second surface which are oppositely arranged, the circuit board is provided with at least one opening or cavity for accommodating a semiconductor chip and a semiconductor chip packaging body, and the periphery of the opening or cavity on the first surface of the circuit board is provided with a module alignment mark;
s2, attaching an adhesive film on the second surface of the circuit board, placing the semiconductor chip and the semiconductor chip package into the opening or the cavity, and adhering and fixing the semiconductor chip package and the adhesive film;
s3, applying packaging materials on at least the first surface of the circuit board, the module alignment mark and the opening or the cavity, so that the first surface of the circuit board and the module alignment mark are covered by the packaging materials, and the opening or the cavity is completely filled by the packaging materials, the semiconductor chip and the semiconductor chip package;
s4, removing the adhesive film and turning over the circuit board;
s5, covering more than one accumulation layer on the second surface of the circuit board, the semiconductor chip packaging body and the packaging material surface coplanar with the second surface of the circuit board;
and S6, forming a rewiring layer at least for electrically connecting the semiconductor chip, the semiconductor chip package and the circuit board on the accumulation layer.
Specifically, the following describes in detail a method for manufacturing a semiconductor embedded hybrid package structure according to a preferred embodiment of the present invention with reference to the accompanying drawings.
Referring to fig. 1a, a wiring board 1 is provided, which has a first surface 11 and a second surface 12 arranged oppositely, and the first surface 11, the second surface 12, and the area between the first surface 11 and the second surface 12 of the wiring board are respectively provided with a wiring layer 13. The wiring board 1 includes at least one opening or cavity 2 for receiving the semiconductor chip 31 and the semiconductor chip package 32. Preferably, the present embodiment includes a plurality of openings or cavities 2 for accommodating the semiconductor chip 31 and the semiconductor chip package 32, respectively.
The module alignment mark 5 is arranged on the first surface of the circuit board 1, and the surface of the module alignment mark 5 and the second surface of the circuit board respectively correspond to the highest surface and the lowest surface of the circuit board.
Referring to fig. 1b and 1d, an adhesive film 201 is attached to the second surface 12 of the wiring board 1, the semiconductor chip 31 and the semiconductor chip package 32 are placed in the opening or cavity 2 in an inverted state, and the external electrode of the semiconductor chip package 3 and the adhesive film 201 are adhered and fixed in the opening or cavity 2.
In the present embodiment, referring to fig. 1c, a schematic structural diagram of the semiconductor chip package 32 is shown, and at least one semiconductor bare chip 321 is disposed in the semiconductor chip package 32. The bare semiconductor wafer is a type of semiconductor device that is manufactured by etching, wiring, and the like on a semiconductor wafer and can realize a specific function. The bare semiconductor chip 321 is mold-packaged with the mold material 322 to obtain the semiconductor chip package 32. The semiconductor chip package 32 is disposed in the opening or cavity 2, the semiconductor chip package 32 includes a package inner conductive lead or wire 323 and an outer electrode 324 electrically connected to the electrode/pad of the semiconductor bare chip 321 in the semiconductor chip package and extending outward from the semiconductor bare chip 321, and the outer electrode 324 is electrically interconnected with the electrode/pad on the semiconductor bare chip 321 in the semiconductor chip package via the inner conductive lead or wire.
Referring to fig. 1e, a layer of packaging material 4 is formed on the first surface 11 of the circuit board, above the module alignment mark 5 and filling the space inside the opening or cavity 2 not occupied by the semiconductor chip 31 and the semiconductor chip package 32.
In this step, the encapsulating material 4 may also be subjected to a planarization process.
The encapsulating material 4 may be a Molding compound (Molding compound), epoxy/filler compound, or the like, which fills the opening or cavity 2 and covers the first surface 11 of the circuit board 1 as a flat stack layer.
Referring to fig. 1f, the adhesive film 201 is removed and the wiring board 1 is turned upside down.
Referring to fig. 1g, 1h and 1i, a first accumulation layer 81 covering at least the second surface 12 of the wiring board 1, the encapsulating material 4, the semiconductor chip 31 and the semiconductor chip package 32 is formed on the second surface 12 of the wiring board 1 after the inversion, and an opening 811 is formed by removing the first accumulation layer 81 above the electrode of the semiconductor chip 31 and the external electrode 32 of the semiconductor chip package 3, and the opening 811 is formed by means of laser drilling, photolithography and the like. Then, a first redistribution layer 61(RDL) is formed on the first accumulation layer 81 through the opening 811; likewise, the surface of the encapsulation material 4 on the first surface 11 of the circuit board 1 may also be formed by removing the corresponding encapsulation material to form an opening 812 using a laser opening process, and forming the second redistribution layer 62 on the encapsulation material through the opening 812. The method for forming the rewiring layer comprises a sequence of processes of metal film coating, dry film lamination, pattern exposure, development, copper plating, film removal and copper etching; or a sequence of processes including metal film coating, copper plating, dry film lamination, pattern exposure, development, copper etching and film removal.
Referring to fig. 1j, 1k, a second accumulation layer 82 is formed over the first rewiring layer 61 and the second rewiring layer 62, an opening 813 is formed on the second accumulation layer 82, a conductive blind via is provided on the second accumulation layer on the first surface of the wiring board, and a third rewiring layer 63 electrically interconnected with the first rewiring layer 61 and/or the second rewiring layer 62 via the conductive blind via is formed on the second accumulation layer 81 through the opening 813. In this embodiment, the third redistribution layers are respectively located on the upper and lower sides of the package structure.
Referring to fig. 1l, forming a solder mask 10 on the outermost circuit layer of the package structure, opening the solder mask above the outermost circuit layer, and performing a nickel-plating and gold-plating process on the surface of the copper electrode at the opening of the solder mask to deposit a nickel/gold layer and then form a pad;
finally, referring to fig. 1m, a semiconductor package device and/or passive electronic component 101 is mounted over the opening in the solder mask 10, the semiconductor package device and/or passive electronic component being electrically interconnected to the third redistribution layer through the pad.
In other preferred embodiments, the packaged object also relates to one or more passive electronic components 7 in addition to the semiconductor chip 31 and the semiconductor chip package 32. One typical package structure is shown in fig. 2, and the manufacturing method is shown in fig. 2 a-2 l, which is substantially the same as the aforementioned manufacturing method (fig. 1 a-1 m), and includes adding an opening or cavity 2 for accommodating the passive electronic element 7, and performing the package of the first redistribution layer 61 and the third redistribution layer 63 at the corresponding positions of the opening or cavity 2 where the passive electronic element 7 is located.
Specifically, in another embodiment of the present invention, referring to fig. 2, the semiconductor embedded hybrid package structure specifically includes:
a circuit board 1, namely a circuit carrier board for packaging a semiconductor chip (Bare Die), a semiconductor chip package (semiconductor package) and a passive electronic component 7, having a first surface 11 and a second surface 12 arranged oppositely;
at least one opening or cavity 2 for accommodating a semiconductor chip 31, at least one semiconductor chip package 32 and at least one passive electronic component 7, which are arranged in the circuit board 1;
a semiconductor chip 31, a semiconductor chip package 32 and a passive electronic element 7 disposed in the opening or cavity 2;
the packaging material 4 is at least used for covering the first surface 11 of the circuit board, the module alignment mark 5 and filling the space which is not occupied by the semiconductor chip 31, the semiconductor chip packaging body 32 and the passive electronic element 7 in the opening or the cavity 2;
and a rewiring layer 6 for electrically connecting at least the semiconductor chip 31, the semiconductor chip package 32, the passive electronic component 7, and the wiring board 1.
Referring to fig. 2a and 2b, a first surface 11, a second surface 12, and a region between the first surface 11 and the second surface 12 of the circuit board are respectively provided with a circuit layer 13, the module alignment mark 5 is disposed on the first surface of the circuit board 1, and the surface of the module alignment mark 5 and the second surface of the circuit board respectively correspond to the highest surface and the lowest surface of the circuit board. The module alignment mark 5 is used for realizing accurate semiconductor chip, semiconductor chip package, passive electronic component arrangement and conductive circuit interconnection, and all marks or part marks can simultaneously become connecting circuits and provide conductive functions.
The highest surface and the lowest surface of the opening or the cavity 2 in the vertical direction are respectively the highest surface of the circuit board 1 or the surface of the module alignment mark 5 and the second surface 12 of the circuit board 1 or the lowest surface thereof, and the boundary of the opening or cavity 2 in the horizontal direction is the side wall of the opening or cavity 2 between the first surface 11 and the second surface 12 of the circuit board 1, and the opening or cavity 2 includes a first space 21 and a second space 22, wherein said first space 21 is distributed between the first surface 11 and the second surface 12 of said wiring board 1, the second space 22 is distributed between the first surface 11 of the circuit board 1 and the surface of the module alignment mark 5, and the side wall of the first space 21 is a continuous section of the circuit board 1 between the first surface 11 and the second surface 12 of the circuit board, while the second space 21 has no side wall.
As in the previous embodiment, the semiconductor chip package 32 has at least one semiconductor die 321 therein. The bare semiconductor wafer is a type of semiconductor device that is manufactured by etching, wiring, and the like on a semiconductor wafer and can realize a specific function. The bare semiconductor chip 321 is mold-packaged with the mold material 322 to obtain the semiconductor chip package 32. The semiconductor chip package 32 is disposed in the opening or cavity 2, the semiconductor chip package 32 includes a package inner conductive lead or wire 323 and an outer electrode 324 electrically connected to the electrode/pad of the semiconductor bare chip 321 in the semiconductor chip package and extending outward from the semiconductor bare chip 321, and the outer electrode 324 is electrically interconnected with the electrode/pad on the semiconductor bare chip 321 in the semiconductor chip package via the inner conductive lead or wire. The external electrode 324 of the semiconductor chip package may be a metallic copper layer or a metallic copper layer covered with a nickel/gold layer. The semiconductor chip package 32 may be a semiconductor chip package having a package structure of InFO, WLCSP, eWLB, FOWLP, FC-BGA, FC-CSP, WB-BGA, QFN, or the like.
Unlike the embodiment shown in fig. 1, in this embodiment, in addition to the semiconductor chip 31 and the semiconductor chip package 32, part of the opening or the cavity 2 may be used to mount other passive electronic components 7, such as but not limited to capacitors, resistors, inductors, and the like, and the packaging material 4 is also used to fill the space inside the opening or the cavity not occupied by the passive electronic component 7.
Further, the external electrode 324 of the semiconductor chip package 32 in the present invention is exposed in the air or covered with a film; the external electrode 324 is a copper metal layer or a copper metal layer covered by a nickel/gold layer; the film is made of an accumulation layer dielectric material, and can be a plastic packaging material, a layer increasing material, or other accumulation layer dielectric materials such as Polyimide (Polyimide).
As in this embodiment, the package structure further includes a first accumulation layer 81 covering at least the second surface 12 of the wiring board 1, the encapsulating material 4, the semiconductor chip 31, the semiconductor chip package 32, and the passive electronic component 7; the first build-up layer 81 is a dielectric material layer, including an ABF build-up layer, a photosensitive dielectric layer, or other dielectric material layer.
As shown in fig. 2h, the first accumulation layer 81 has blind holes above the circuit layers of the semiconductor chip, the external electrode of the semiconductor chip package, the passive electronic element 7, and the circuit board; the first redistribution layer 61 is arranged on the first accumulation layer, and the first redistribution layer 61 on the first accumulation layer 81 is electrically interconnected with the semiconductor chip, the external electrode of the semiconductor chip package, the passive electronic element and the circuit layer on the circuit board through the blind hole. A second redistribution layer 62 is also provided on the encapsulation material 4 on the first surface 11 of the wiring board, the second redistribution layer 62 being electrically interconnected with the wiring layer on the wiring board, the semiconductor chip, and/or the semiconductor chip package external electrode 324 and/or the passive electronic component 7 via the conductive blind via.
Further, as shown in fig. 2i and 2j, the first redistribution layer 61 and the second redistribution layer 62 are covered with a second accumulation layer 82, and the second accumulation layer 82 is formed with a third redistribution layer 63 electrically interconnected with the first redistribution layer and the second redistribution layer, respectively, wherein the second accumulation layer is an ABF build-up layer, a photosensitive dielectric layer, or other dielectric material layer.
In addition, the packaging structure further comprises a solder mask 10 at least covering the outermost circuit layer, an opening of the solder mask arranged above the outermost circuit layer, a pad formed in the opening, and other semiconductor packaging devices and/or passive electronic components 101 attached above the solder mask 10, wherein the passive electronic components include but are not limited to capacitors, resistors, inductors and the like, and the semiconductor packaging devices and/or passive electronic components 101 are electrically interconnected with the third redistribution layer through the pad. In this embodiment, the first accumulation layer and the second accumulation layer are both illustrated by using an ABF build-up layer as an example, and in other embodiments, the first accumulation layer and the second accumulation layer may be other dielectric material layers.
The above-described embodiment is only one preferred embodiment of the present invention, and it should be understood that in other embodiments, the first accumulation layer, the second accumulation layer, the first rewiring layer, the second rewiring layer, and the third rewiring layer may be selectively provided, such as only the first accumulation layer, the first rewiring layer, and the second rewiring layer; in addition, other interconnection layers for electrical connection may be further provided in addition to the accumulation layer and the redistribution layer, so long as a package structure that can achieve electrical connection of other semiconductor package devices and/or the passive electronic element 101 with the semiconductor chip, the semiconductor chip package, the passive electronic element or the circuit board is within the protection scope of the present invention.
The invention also provides a manufacturing method of the semiconductor embedded hybrid packaging structure, which comprises the following steps:
s1, providing a circuit board, wherein the circuit board is provided with a first surface and a second surface which are oppositely arranged, the circuit board is provided with at least one opening or cavity for accommodating a semiconductor chip, a semiconductor chip packaging body and a passive electronic element, and the periphery of the opening or cavity on the first surface of the circuit board is provided with a module alignment mark;
s2, attaching an adhesive film on the second surface of the circuit board, placing the semiconductor chip, the semiconductor chip package and the passive electronic element into the opening or the cavity, and adhering and fixing the semiconductor chip package and the adhesive film;
s3, applying packaging materials on at least the first surface of the circuit board, the module alignment mark and the opening or the cavity, so that the first surface of the circuit board and the module alignment mark are covered by the packaging materials, and the opening or the cavity is completely filled by the packaging materials, the semiconductor chip package and the passive electronic element;
s4, removing the adhesive film and turning over the circuit board;
s5, covering more than one accumulation layer on the second surface of the circuit board, the semiconductor chip packaging body, the passive electronic element and the packaging material surface coplanar with the second surface of the circuit board;
and S6, forming a rewiring layer at least for electrically connecting the semiconductor chip, the semiconductor chip packaging body, the passive electronic element and the circuit board on the accumulation layer.
Specifically, the following describes in detail a method for manufacturing a semiconductor embedded hybrid package structure according to a preferred embodiment of the present invention with reference to the accompanying drawings.
Referring to fig. 2a, a wiring board 1 is provided, which has a first surface 11 and a second surface 12 arranged oppositely, and the first surface 11, the second surface 12, and the area between the first surface 11 and the second surface 12 of the wiring board are respectively provided with a wiring layer 13. The wiring board 1 includes at least one opening or cavity 2 for receiving the semiconductor chip 31, the semiconductor chip package 32 and the passive electronic component 7. Preferably, the present embodiment includes a plurality of openings or cavities 2 for accommodating the semiconductor chip 31, the semiconductor chip package 32 and the passive electronic component 7, respectively.
The module alignment mark 5 is arranged on the first surface of the circuit board 1, and the surface of the module alignment mark 5 and the second surface of the circuit board respectively correspond to the highest surface and the lowest surface of the circuit board.
Referring to fig. 2b and 2c, an adhesive film 201 is attached to the second surface 12 of the circuit board 1, the semiconductor chip 31, the semiconductor chip package 32 and the passive electronic component 7 are placed in the opening or cavity 2 in an inverted manner, and the external electrode of the semiconductor chip package 3 and the adhesive film 201 are adhered and fixed in the opening or cavity 2.
In this embodiment, the semiconductor chip package 32 has at least one semiconductor bare chip 321 therein, which is the same as the semiconductor chip package 32 shown in fig. 1c in the first embodiment. The bare semiconductor wafer is a type of semiconductor device that is manufactured by etching, wiring, and the like on a semiconductor wafer and can realize a specific function. The bare semiconductor chip 321 is mold-packaged with the mold material 322 to obtain the semiconductor chip package 32. The semiconductor chip package 32 is disposed in the opening or cavity 2, the semiconductor chip package 32 includes a package inner conductive lead or wire 323 and an outer electrode 324 electrically connected to an electrode/pad of the semiconductor die 321 in the semiconductor chip package and extending outward from the semiconductor die 321, and the outer electrode 324 is electrically interconnected with the electrode/pad on the semiconductor die 321 in the semiconductor chip package via the inner conductive lead or wire.
Referring to fig. 2d, a layer of packaging material 4 is molded on the first surface 11 of the circuit board, above the module alignment mark 5 and in the space filling the opening or cavity 2 not occupied by the semiconductor chip 31, the semiconductor chip package 32 and the passive electronic component 7.
In this step, the encapsulating material 4 may also be subjected to a planarization process.
The encapsulating material 4 may be a Molding compound (Molding compound), epoxy/filler compound, or the like, which fills the opening or cavity 2 and covers the first surface 11 of the circuit board 1 as a flat stack layer.
Referring to fig. 2e, the adhesive film 201 is removed and the wiring board 1 is turned upside down.
Referring to fig. 2f, 2g and 2h, a first accumulation layer 81 covering at least the second surface 12 of the wiring board 1, the encapsulating material 4, the semiconductor chip 31, the semiconductor chip package 32 and the passive electronic element 7 is formed on the second surface 12 of the wiring board 1 after the turning, an opening 811 is formed by removing the first accumulation layer 81 above the electrode of the semiconductor chip 31, the electrode of the semiconductor chip package 3 and the external electrode 32 of the passive electronic element 7, and the opening 811 is formed by means of laser drilling, photolithography and the like. Then, a first redistribution layer 61(RDL) is formed on the first accumulation layer 81 through the opening 811; likewise, the surface of the encapsulating material 4 on the first surface 11 of the wiring board 1 may also be formed with an opening 812 by removing the corresponding encapsulating material using a laser opening process, and forming the second redistribution layer 62 on the encapsulating material through the opening 812. The method for forming the rewiring layer comprises a sequence of processes of metal film coating, dry film lamination, pattern exposure, development, copper plating, film removal and copper etching; or a sequence of processes including metal film coating, copper plating, dry film lamination, pattern exposure, development, copper etching and film removal.
Referring to fig. 2i and 2j, a second accumulation layer 82 is formed over the first redistribution layer 61 and the second redistribution layer 62, an opening 813 is formed on the second accumulation layer 82, a conductive blind via is provided on the second accumulation layer on the first surface of the wiring board, and a third redistribution layer 63 electrically interconnected with the first redistribution layer 61 and/or the second redistribution layer 62 via the conductive blind via is formed on the second accumulation layer 81 through the opening 813. In this embodiment, the third redistribution layers are respectively located on the upper and lower sides of the package structure.
Referring to fig. 2k, forming a solder mask 10 on the outermost circuit layer of the package structure, opening the solder mask above the outermost circuit layer, and performing a nickel-plating and gold-plating process on the surface of the copper electrode at the opening of the solder mask to deposit a nickel/gold layer and then form a pad;
finally, referring to fig. 2l, a semiconductor package device and/or passive electronic component 101 is mounted over the opening in the solder mask 10, the semiconductor package device and/or passive electronic component being electrically interconnected to the third redistribution layer through the pad.
Compared with the prior art, the semiconductor embedded hybrid packaging structure and the manufacturing method thereof adopt the technical scheme of circuit board embedding, can simplify the integration process flow of the semiconductor chip and the semiconductor chip packaging body, improve the integration quality and performance, and effectively reduce the integration area, and specifically comprise the following steps:
the semiconductor chip and the semiconductor packaging body are packaged and processed on the circuit board at the same time, so that the complex and fussy standard and process butt joint of the semiconductor chip and the semiconductor packaging body in the prior art are omitted, the circulation transfer of electronic manufacturing is reduced, manpower and material resources are saved, and the cost of electronic products can be further reduced;
the electrical connection of the semiconductor chip and the circuit board and the electrical connection of the semiconductor chip package and the circuit board do not need a soldering tin connection scheme, but adopt a simple copper Redistribution (RDL) scheme, so that the process is stable and the reliability is high;
the requirements for assembling more precise semiconductor chips and semiconductor chip packages can be met, for example, the pad/pad pitch of the semiconductor chip or semiconductor chip package can be reduced to below 150 micrometers/200 micrometers;
the embedded assembly of the semiconductor chip and the semiconductor chip packaging body enables the surface area of the circuit board to be fully released, the assembly area of a system can be greatly reduced, and the reduction ratio can exceed 50%.
It should be understood that the above description is only an example of the present invention, and not intended to limit the scope of the present invention, and all equivalent structures or equivalent flow transformations that are made by the present specification and drawings, or applied directly or indirectly to other related technical fields, are included in the scope of the present invention.
Claims (11)
1. A semiconductor embedded hybrid package structure, the package structure comprising:
the circuit board is provided with a first surface and a second surface which are oppositely arranged;
an opening or cavity in the circuit board for accommodating at least the semiconductor chip and the semiconductor chip package;
a semiconductor chip disposed in the opening or cavity for at least receiving the semiconductor chip and the semiconductor chip package;
a semiconductor chip package disposed in the opening or cavity for at least receiving the semiconductor chip and the semiconductor chip package, the semiconductor chip package having at least one semiconductor bare chip and a semiconductor chip package with a plastic package material, the semiconductor chip package further comprising: a conductive lead or wire electrically connected to an electrode/pad of a semiconductor bare chip in a semiconductor chip package and extending outward from the semiconductor bare chip, and an external electrode electrically connected to the semiconductor bare chip; the external electrode is exposed in the air or covered by a film;
the packaging material is at least used for covering the first surface of the circuit board and filling the space which is not occupied by the semiconductor chip and the semiconductor chip packaging body in the opening or the cavity for accommodating the semiconductor chip and the semiconductor chip packaging body;
the first accumulation layer at least covers the second surface of the circuit board, the packaging material, the semiconductor chip and the semiconductor chip packaging body, the first accumulation layer is a dielectric material layer, and blind holes are formed in the first accumulation layer above the electrode/bonding pad of the semiconductor chip, the external electrode of the semiconductor chip packaging body and the circuit layer of the circuit board;
a rewiring layer at least for electrically connecting the semiconductor chip, the semiconductor chip package and the circuit board, the rewiring layer including a first rewiring layer and a second rewiring layer; and
a solder mask covering at least the outermost circuit layer and an opening provided in the solder mask, the circuit layer provided in the opening in the solder mask forming a pad to which an external component is connected;
the first accumulation layer is provided with a first rewiring layer, the first rewiring layer on the first accumulation layer is electrically interconnected with an electrode/bonding pad of a semiconductor chip, an external electrode of a semiconductor chip packaging body and/or a circuit layer on a circuit board through the blind hole, a second rewiring layer is further arranged on packaging materials on the first surface of the circuit board, the second rewiring layer is electrically interconnected with at least the circuit layer on the circuit board, the semiconductor chip and/or an external electrode of the semiconductor chip packaging body through the conductive blind hole, the first rewiring layer and/or the second rewiring layer are/is covered with a second accumulation layer, and a third rewiring layer electrically interconnected with the first rewiring layer and/or the second rewiring layer is/are formed on the second accumulation layer.
2. The semiconductor embedded hybrid package structure of claim 1, wherein: the first surface of circuit board is provided with the module alignment sign, the surface of module alignment sign and the second surface of circuit board correspond respectively the highest surface and the lowest surface of circuit board.
3. The semiconductor embedded hybrid package structure of claim 1, wherein: and a passive electronic element is arranged in the opening or the cavity at least used for accommodating the semiconductor chip and the semiconductor chip packaging body, and the passive electronic element comprises any one or combination of a capacitor, a resistor and an inductance element.
4. The semiconductor embedded hybrid package structure of claim 1, wherein: the external electrode is made of a copper metal layer or a copper metal layer covered by a nickel/gold layer; the film is made of an accumulation layer dielectric material, and the accumulation layer dielectric material comprises a plastic package material, a layer adding material or polyimide.
5. The semiconductor embedded hybrid package structure of claim 3, wherein: the packaging material is also used for filling the space which is not occupied by the passive electronic element in the opening or the cavity at least used for accommodating the semiconductor chip and the semiconductor chip packaging body.
6. The semiconductor embedded hybrid package structure of claim 1 or 3, wherein: the package structure further includes the first accumulation layer including an ABF build-up layer or a photosensitive dielectric layer.
7. The semiconductor embedded hybrid package structure of claim 1, wherein: the second accumulation layer includes an ABF build-up layer or a photosensitive dielectric layer.
8. The semiconductor embedded hybrid package structure of claim 1, wherein: the packaging structure further comprises a semiconductor packaging device and/or a passive electronic element above the mounting solder mask, wherein the passive electronic element comprises any one or combination of a plurality of capacitance elements, resistance elements and inductance elements, and the semiconductor packaging device and/or the passive electronic element are electrically interconnected through the bonding pad and the third redistribution layer.
9. The method of fabricating a semiconductor embedded hybrid package structure of any one of claims 1-8, wherein the method of fabricating comprises the steps of:
s1, providing a circuit board, wherein the circuit board is provided with a first surface and a second surface which are oppositely arranged, and the circuit board is provided with an opening or a cavity which is at least used for accommodating the semiconductor chip and the semiconductor chip packaging body;
s2, attaching an adhesive film on the second surface of the circuit board, placing the semiconductor chip and the semiconductor chip package into the opening or the cavity at least for accommodating the semiconductor chip and the semiconductor chip package, and adhering and fixing the semiconductor chip and the semiconductor chip package with the adhesive film;
s3, applying packaging materials on at least the first surface of the circuit board and the opening or cavity at least used for accommodating the semiconductor chip and the semiconductor chip package, so that the first surface of the circuit board is covered by the packaging materials, and the opening or cavity at least used for accommodating the semiconductor chip and the semiconductor chip package is completely filled by the packaging materials and the semiconductor chip package;
s4, removing the adhesive film and turning over the circuit board;
s5, covering more than one accumulation layer on the second surface of the circuit board, the semiconductor chip packaging body and the packaging material surface coplanar with the second surface of the circuit board;
and S6, forming a rewiring layer at least for electrically connecting the semiconductor chip, the semiconductor chip package and the circuit board on the accumulation layer.
10. The method for manufacturing the semiconductor embedded hybrid package structure of claim 9, wherein the step S6 comprises:
arranging blind holes on a first accumulation layer positioned above an electrode/bonding pad of a semiconductor chip, an external electrode of a semiconductor chip packaging body and a circuit layer of a circuit board, and forming a first rewiring layer which is electrically interconnected with the electrode/bonding pad of the semiconductor chip, the external electrode of the semiconductor chip packaging body and/or the circuit layer on the circuit board through the blind holes;
arranging a second rewiring layer on the packaging material on the first surface of the circuit board; the second redistribution layer is electrically interconnected with the circuit layer on the circuit board, the semiconductor chip, and/or the external electrode of the semiconductor chip package via the conductive blind via;
a second accumulation layer is formed on the first redistribution layer and/or the second redistribution layer, a conductive blind via is provided on the second accumulation layer, and a third redistribution layer electrically connecting the first redistribution layer and/or the second redistribution layer via the conductive blind via is formed.
11. The method for manufacturing a semiconductor embedded hybrid package structure according to claim 10, wherein the step S6 is further followed by:
forming a solder mask on the outermost circuit layer of the packaging structure, and opening the solder mask above the circuit layer to form a corresponding pad;
and mounting a semiconductor packaging device and/or a passive electronic element above the solder mask, wherein the semiconductor packaging device and/or the passive electronic element are electrically interconnected with the third redistribution layer through the bonding pad.
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| CN209045531U (en) * | 2017-09-15 | 2019-06-28 | Pep创新私人有限公司 | A kind of semiconductor chip package |
| CN108711570B (en) * | 2018-08-10 | 2024-03-29 | 浙江熔城半导体有限公司 | Multi-chip packaging structure of integrated chip packaging structure and manufacturing method thereof |
| CN109640521B (en) | 2018-11-20 | 2020-06-30 | 奥特斯科技(重庆)有限公司 | Method for manufacturing a component carrier with embedded clusters and component carrier |
| CN113161249A (en) * | 2021-03-31 | 2021-07-23 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
| TWI829396B (en) * | 2022-10-21 | 2024-01-11 | 欣興電子股份有限公司 | Circuit board structure and manufacturing method thereof |
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| JP3809053B2 (en) * | 2000-01-20 | 2006-08-16 | 新光電気工業株式会社 | Electronic component package |
| CN101859752A (en) * | 2009-04-06 | 2010-10-13 | 杨文焜 | Stack package structure and manufacture method thereof with chip embedded and silicon through hole crystal grain |
| CN102034768A (en) * | 2009-09-25 | 2011-04-27 | 杨文焜 | Embedded-dice-inside type substrate structure with redistribution layer covered on both side and method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3809053B2 (en) * | 2000-01-20 | 2006-08-16 | 新光電気工業株式会社 | Electronic component package |
| CN101859752A (en) * | 2009-04-06 | 2010-10-13 | 杨文焜 | Stack package structure and manufacture method thereof with chip embedded and silicon through hole crystal grain |
| CN102034768A (en) * | 2009-09-25 | 2011-04-27 | 杨文焜 | Embedded-dice-inside type substrate structure with redistribution layer covered on both side and method thereof |
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