CN106789100A - A kind of built-in network terminal - Google Patents
A kind of built-in network terminal Download PDFInfo
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- CN106789100A CN106789100A CN201611038063.1A CN201611038063A CN106789100A CN 106789100 A CN106789100 A CN 106789100A CN 201611038063 A CN201611038063 A CN 201611038063A CN 106789100 A CN106789100 A CN 106789100A
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- network
- module
- network terminal
- controller
- controller module
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/02—Details
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- Computer Networks & Wireless Communication (AREA)
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- Small-Scale Networks (AREA)
Abstract
The present invention relates to network terminal technical field, a kind of built-in network terminal is disclosed, the hardware of the network terminal includes main controller module, network controller module, power module, watchdog module;The software of the network terminal includes that house dog program, network interface card controller driver and the part of TCP/IP agreements three are constituted;The main controller module uses the MSP430F5438 chips of TI companies;The network controller module uses ENC28J60 chips, is communicated with master controller by SPI interfaces, while expanding a RJ45 interface to realize the connection with network;Power module ensure that the conversion of external stabilized power, system components is operated in normal voltage.Compared with prior art, low cost of the present invention, hardware is few, using C language developments, it is easy to transplanting and secondary development.
Description
Technical field
The present invention relates to network terminal technical field, more specifically, more particularly to a kind of built-in network terminal.
Background technology
Built-in network terminal refers to the network that the embedded system based on microcontroller is constituted with ethernet network interface
Terminal.On the one hand it be responsible for Ethernet carries out network service by ICP/IP protocol stack and PC, is on the other hand responsible for scene
The collection and treatment of analog quantity and switching value;Compared with based on serial ports, the network interface embedded system of CAN, based on
The embedded system netted very much has obvious advantage in data transmission bauds.
Fusion, life of the Embedded Ethernet Technology in people are continued to develop with the network communications technology and embedded system
Middle to play more and more important effect, following world will be a world for Network Information.Set for low profile edge
For standby, various data and information are transmitted by Internet, it is possible to use family is entered by Internet with any PC
Row network service and information sharing.Along with the increase of embedded device in next generation network, embedded ethernet technology will
Focus as research, realizes that the combination of ICP/IP protocol and embedded system is significant.Existing built-in network
Terminal still suffers from relatively costly, and hardware is more, is not easy to the defects such as transplanting and secondary development.
The content of the invention
It is an object of the invention to provide a kind of built-in network terminal, the hardware of the network terminal includes master controller
Module, network controller module, power module, watchdog module.The software of the network terminal is developed using C voices, including
House dog program, network interface card controller driver and the part of TCP/IP agreements three are constituted.
Further, main controller module using TI companies MSP430F5438 chips, realize TCP/IP agreements with
The write-in of bsp driver.Network controller module uses ENC28J60 chips, is led to by SPI interfaces and master controller
Letter;Expand a RJ45 interface to realize the connection with network simultaneously.Power module ensure that turning for external stabilized power
Change, system components is operated in normal voltage.Watchdog module mainly prevents program fleet and is absorbed in endless loop, compensate for master
The deficiency of the built-in house dog of controller, improves the stability of system.
Compared with prior art, low cost of the present invention, hardware is few, using C language developments, it is easy to transplanting and secondary development.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is system architecture diagram of the present invention.
Fig. 2 is system master controller module circuit diagram of the present invention.
Fig. 3 is system network card controller module circuit diagram of the present invention.
Fig. 4 is system power supply module circuit diagram of the present invention.
Fig. 5 is system watchdog circuit figure of the present invention.
Fig. 6 is software flow figure of the present invention.
Specific embodiment
The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, so that advantages and features of the invention energy
It is easier to be readily appreciated by one skilled in the art, apparent is clearly defined so as to be made to protection scope of the present invention.
Refering to system shown in Figure 1 structured flowchart, the present invention provides a kind of built-in network terminal, the network terminal it is hard
Part includes main controller module, network controller module, power module, watchdog module.
MSP430F5438 is the super low-power consumption processor that TI companies release, and has been internally integrated 256KB FLASH storages
Device, 16KB RAM, reduced instruction set computer (RISC), four Generalized Communication Interfaces and 12 analog-to-digital conversions etc..The processor has to be deposited
Storage space is big, and hardware resource is more, writes program simply, and the convenient advantage of debugging routine meets system and realizing TCP/IP agreements
While carry out the data transfer of network terminal system.
The 28 pin independence ethernet controllers that system is released from Microchip Technology companies
ENC28j60, the circuit structure that the chip improves ethernet circuit presence is complicated, the more defect of line, with number well
According to transfer function, design is enormously simplify while required function is provided.In addition, ENC28J60 compatibilities IEEE802.3
Agreement, while the built-in ethernet physical layer device of 10M/S(PHY)And media access controller(MAC), with master controller
The SPI interface maximum speed of connection, can be by Ethernet protocol reliably transceiving data bag up to 10M/S.
MSP430F5438 is communicated by SPI interfaces with ENC28J60, the SCK of MSP430F5438, MISO,
MOSI pins connect SCK, SI, SO pin of ENC28J60 respectively;P10.6 numerals I/O connects ENC28J60'sDraw
Pin.Master controller sends the register or reception/transmission buffering area for ordering and accessing ENC28j60 by SPI interfaces,
By SI pins be input into for the order of single-chip microcomputer and data in the rising edge of SCK by ENC28J60, in each trailing edge of SCK
The data that master controller will be transmitted to are sent out from SO pins, and SCK must keep low level in idle condition.It is the piece of SPI
Output pin is selected, when operation is performedPin keeps low level, and high level is returned after the completion of operation.
Because the operating voltage of MSP430F5438 is 2.2V ~ 3.6V, and the operating voltage 3.14V of ENC28J60 ~
3.45V.In order to ensure the normal work of system, LM596 regulators will give the 12V DC voltage-stabilizings of system power supply electricity
Source regulation is output as 5V, then 5V is converted into the 3.3V of suitable system by AS1117 low pressure difference linear voltage regulators.
The function of WatchDog Timer is to restart system after there is software issue and program fleet.
It is operationally to there is certain error although MSP430F45438 inside comes with house dog and reset circuit more, in order to carry
System reliability high uses external watchdog circuit.The system uses TPS3823 type voltage monitoring circuits, whenPin is
Activated during low level, internal WatchDog Timer can be by the positive and negative saltus step level of the P2.0 pins of MSP430F5438
Reset, if there is no level saltus step more than certain hour,Output low level is to system reset.
House dog program to be mainly be monitored system to be prevented from program fleet and being absorbed in endless loop, if more than 1.6s
Not to house dog counter O reset, then system reset.Selection crystal oscillator XT2 first is used as main system clock, son
The clock source of system clock and accessory system clock, it is 2 to set main system clock divider ratio, drives crystal oscillator and sets vibration model
It is 8 ~ 16M to enclose.Then P2.0 is set to digital I/O outputs, the comparing/capture register TA1CCTL0 of timer A is set
It is CCIE, the counting cycle is set to TA1CCR0=6000.The control register selection main system clock of last timer A as when
Zhong Yuan, continuous counter pattern.That main system clock is 6M in the case of upper electricity, enters after counting reaches 6000 and interrupts;
After variable timecount defined in interrupt routine, timeou variable often count 20 times there is saltus step in P2.0 output levels, make
Obtain LED to be flashed once per 40ms, it is ensured that reset before house dog counter overflow.
Network interface card controller driver realizes the driving of lower network interface and hardware function.Net is loaded in the host controller
The configuration information of the core of the card piece, in the input/output buffering area by the packet of transmission by specified format write-in chip and starts hair
Lose one's life order, while packet is converted into physical frame formats automatically transmitting on the physical channel.NIC driver is main by first
Beginningization is operated, read-write operation, the part of transceiving data package operation three composition.
Initialization operation:ENC28j60 needed to carry out Initialize installation, initialization function before data are sent and received
Enc28j60_initialize () is initialized to each register and is completed the configuration of correlation.Initialization operation is mainly wrapped
Include to receive and start setting of time, MAC registers and PHY registers etc. with transmission buffer, reception filter, crystal oscillator.
Read-write operation:(1)Read/write function mainly completes the communication of master controller and network interface card controller.Moved to when there are data
When sending buffering area, USCI starts data hair;If it is sky to send shift register, the data of buffering area enter, and
UCB2SIMO ends send data.In opposite clock edge, the data at UCB2SOMI ends are displaced to data receiver register;Word
When symbol data are received, data can move to data receiver buffering area UCXRXBUF from shift register is received, and receive interruption
Flag bit UCRXIFG puts 1, and the reception and transmission work of data are completed.(2)Read-write buffering by set loop buffer it is trivial come
Complete.The array that size is 2048 is defined, under a pointer PtrIn for pointing to next secondary data writing address and one point to
Pointer PtrOut for data read-out address.When buffering area is created, pointer PtrIn and PtrOut are initialised to buffering area
Starting point BUF-BEGIN, i.e. the first of array address space.After write-in data, two pointers are no longer point to same address, with
Two pointers of continuous write-in of data can be again directed to same address, judged by an indexed variable buffering area be it is full or
It is empty.
Transceiving data package operation:(1)Send packet:Register MAC automatically generates leading character and frame starting when sending
Delimiter, according to configuration generation filling and CRC fields;And other all frame fields are generated by master controller, and write them into
Buffer storage is with to be sent.In addition, ENC28J60 can add a bag control byte before packet to be sent.
(Two)Receive packet:MAC addresses are correctly configured, while filter deployment will be received to receive Ethernet data bag.Make
The packet not filtered out after receiving will write buffer circle, and any packet for not meeting filter condition will be lost
Abandon.When a packet is received and by its complete write-in buffer circle, EPKTCNT registers will be incremented by,
EIR.PKTIF will put 1, and produce an interruption, while hardware write pointer ERXWRPT is incremented by automatically.
More than send, reception process complete is MAC addresses and physical layer agreement, to realize embedded system with
The communication of too online miscellaneous equipment also needs to TCP/IP agreements.Due to the resource-constrained of single-chip microcomputer, so procotol is according to embedding
Enter formula application to cut;The area protocols such as ARP, ICMP, IP, UDP have been used in system, both ensure that single-chip microcomputer access with
Too net, in turn ensure that sufficiently small size of code.
(1)Internet
IP agreements are most crucial agreements in TCP/IP agreements, main verification IP headers and are realized between ICMP, UDP agreement
Multiplexing function.ARP agreements mainly complete the network address to the mapping of physical address;It is poor that ICMP agreements are responsible for transmission
Misrepresent deliberately text and other information for needing.
(2)Transport layer
UDP agreements are a kind of towards connectionless insecure agreement, realize the treatment to packet.The agreement judges its end
Whether correctly mouth and verification give corresponding port application with if correctly, incorrect, discard;To from application journey
The packet that sequence is received, IP layers of transmission is given after the source port number and destination slogan that set response.UDP protocol overheads compare
It is small, it is more suitable for applying in microcontroller embedded field than TCP agreement.
Connect PC machines and the network terminal respectively with cross spider first, data are sent to the network terminal by PC machines, find
Two lamps of network interface card controller are bright;The packet that receives read in buffer circle finds, explanation consistent with the data of PC machines transmission
NIC driver configuration is correct;Then it is correct in a program that the parameters, network end such as gateway, subnet mask, MAC addresses are set
After end is connected by Ethernet with PC machines, as a result shown come the IP addresses of test network terminal with PING orders at PC ends
Show correct, illustrate Ethernet successful connection.
Although being described in conjunction with the accompanying embodiments of the present invention, patent owner can be in appended claims
Within the scope of make various deformations or amendments, as long as no more than the protection domain described by claim of the invention, all should
Within protection scope of the present invention.
Claims (1)
1. a kind of built-in network terminal, including hardware and software, it is characterised in that:The hardware of the network terminal includes master control
Device module processed, network controller module, power module, watchdog module;The software of the network terminal is developed using C voices,
Constituted including house dog program, network interface card controller driver and the part of TCP/IP agreements three;The main controller module is used
The MSP430F5438 chips of TI companies;The network controller module use ENC28J60 chips, by SPI interfaces with
Master controller communicates, while expanding a RJ45 interface to realize the connection with network;Power module ensure that outside voltage stabilizing
The conversion of power supply, makes system components be operated in normal voltage.
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CN201611038063.1A CN106789100A (en) | 2016-11-23 | 2016-11-23 | A kind of built-in network terminal |
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CN201611038063.1A CN106789100A (en) | 2016-11-23 | 2016-11-23 | A kind of built-in network terminal |
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CN106789100A true CN106789100A (en) | 2017-05-31 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111061671A (en) * | 2019-12-13 | 2020-04-24 | 上海灵动微电子股份有限公司 | SPI transmission control method, sending equipment and receiving equipment |
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US20070027570A1 (en) * | 2005-08-01 | 2007-02-01 | Agie Sa | Method of operating a machine tool, a machine tool system and components thereof |
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US20120031499A1 (en) * | 2010-08-09 | 2012-02-09 | Sensus Usa Inc. | Method and Apparatus for Controlling Gas Flow via a Gas Shut-Off Valve Assembly |
CN202404483U (en) * | 2011-12-09 | 2012-08-29 | 杭州纳图科技有限公司 | Embedded network server equipment |
US8706172B2 (en) * | 2010-10-26 | 2014-04-22 | Miscrosoft Corporation | Energy efficient continuous sensing for communications devices |
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2016
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Patent Citations (5)
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US20070027570A1 (en) * | 2005-08-01 | 2007-02-01 | Agie Sa | Method of operating a machine tool, a machine tool system and components thereof |
CN202033883U (en) * | 2010-06-03 | 2011-11-09 | 北京奥特美克科技发展有限公司 | Hydrological water resource measurement and control terminal machine with two mutually spare channels |
US20120031499A1 (en) * | 2010-08-09 | 2012-02-09 | Sensus Usa Inc. | Method and Apparatus for Controlling Gas Flow via a Gas Shut-Off Valve Assembly |
US8706172B2 (en) * | 2010-10-26 | 2014-04-22 | Miscrosoft Corporation | Energy efficient continuous sensing for communications devices |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111061671A (en) * | 2019-12-13 | 2020-04-24 | 上海灵动微电子股份有限公司 | SPI transmission control method, sending equipment and receiving equipment |
CN111061671B (en) * | 2019-12-13 | 2021-08-17 | 上海灵动微电子股份有限公司 | SPI transmission control method, sending equipment and receiving equipment |
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Application publication date: 20170531 |