CN106776373B - Flash-memory-based cache system and method for mobile equipment - Google Patents
Flash-memory-based cache system and method for mobile equipment Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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Abstract
The invention discloses a flash-based cache system and method for mobile equipment. The device comprises a graph drawing unit, an SDRAM module, an FLASH CACHE module and a FLASH module, wherein the graph drawing unit requests data from a FLASH CACHE module; the FLASH CACHE module requests data from the SDRAM or FLASH module and returns the required data to the graphics rendering unit. The invention solves the problem of starting initialization of the mobile drawing equipment by using the SDRAM as the cache of the flash memory, achieves the purposes of starting and random access, realizes the starting requirement of the mobile human-computer interaction interface and the random access requirement of the mobile drawing equipment, and realizes algorithm control, a pipeline architecture and a prefetching strategy based on an FPGA hardware architecture.
Description
Technical Field
The invention belongs to the technical field of cache, and particularly relates to a flash-based cache system and method for mobile equipment.
Background
Flash Memory (Flash Memory) is a type of non-volatile Memory, i.e., power-off data is not lost. The speed of the flash memory is very limited, the operation speed and frequency of the flash memory are much lower than those of the memory, and the NAND type flash memory operates in a hard disk-like mode in a much slower efficiency than the direct access mode of the memory.
In 1984, Toshiba's inventor error Ooka Fuji first proposed the concept of flash memory. Unlike traditional computer memories, flash memory is characterized by being non-volatile (i.e., the stored data is not lost after the host is powered down), and its recording speed is very fast.
Intel is the first company in the world to produce and market flash memory. In 1988, a 256Kbit flash memory chip was introduced by the company. It is the same size as a shoe box and is embedded in a recorder. Hereafter, such flash memories of the invention are referred to as NOR flash memories. It combines EPROM (erasable programmable read-only memory) and EEPROM (electrically erasable programmable read-only memory) technologies and has an SRAM interface.
The second type of flash memory is referred to as NAND flash memory. It was developed by Hitachi in 1989 and is considered to be an ideal replacement for NOR flash. The NAND flash memory has a write cycle shorter than that of the NOR flash memory by 90%, and its save and erase processes are relatively fast. The NAND memory cell is only half of NOR, and the NAND obtains better performance in smaller memory space. In view of its excellent performance, NAND is often applied to memory cards such as CompactFlash, SmartMedia, SD, MMC, xD, and PC cards, USBticks, and the like.
SDRAM (synchronous Dynamic Random Access Memory) and synchronous Dynamic Random Access Memory, wherein the synchronization means that the Memory needs a synchronous clock during working, and the sending of internal commands and the transmission of data take the synchronous clock as a reference; dynamic means that the memory array needs to be refreshed continuously to ensure that data is not lost; random means that data are not stored linearly and sequentially, but data are read and written by freely appointing addresses. SDRAM is a power-down volatile memory device that has the advantage of being fast and random-access.
SDRAM has gone through five generations from the development to the present, respectively: the first generation SDR SDRAM, the second generation DDRSDRAM, the third generation DDR2SDRAM, the fourth generation DDR3SDRAM, the fifth generation DDR4 SDRAM.
The first generation SDRAM adopts a Single-Ended (Single-Ended) clock signal, and the second, third and fourth generation SDRAM adopt a differential clock signal capable of reducing interference as a synchronous clock because of its faster operating frequency.
The clock frequency of SDR SDRAM is the frequency of data storage, the first generation memory is named by the clock frequency, if pc100, pc133 indicates that the clock signal is 100 or 133MHz, and the data read-write speed is also 100 or 133 MHz. The second, third, fourth generation DDR (double Data rate) memory uses the Data read/write speed as the naming standard, and is preceded by a symbol indicating the number of DDR generations, where PC-DDR, PC2 is DDR2, and PC3 is DDR 3. If the PC2700 is the DDR333, the operating frequency is 333/2-166 MHz, and the bandwidth is 2.7G in 2700. The read-write frequency of DDR is from DDR200 to DDR400, DDR2 is from DDR2-400 to DDR2-800, DDR3 is from DDR3-800 to DDR 3-1600. A Cache (Cache) is a first-level memory that exists between a main memory and a processor, and is composed of a memory having a relatively small capacity but a much higher speed than the main memory. The scheduling and transfer of information between the cache memory and the main memory is automated by hardware. Mainly consists of three major parts: cache memory bank: storing the instruction and data block called by main memory. An address conversion section: a directory table is built to implement the translation of main memory addresses to cache addresses. Replacement of parts: when the buffer memory is full, the data block is replaced according to a certain strategy, and the address conversion part is modified.
The Chinese application publication patent CN102521178A discloses a reliable implementation mode for displaying human-computer interface images of an embedded system, which adopts a FLASH memory to store image drawing data, and utilizes a DMA and a hardware module to take out the data from the memory for operation and display. However, the high read latency of FLASH affects the rendering efficiency, resulting in a lower frame rate.
Disclosure of Invention
The invention aims to provide a flash-based cache system and method for mobile equipment, which solve the problem of starting initialization of mobile drawing equipment by using SDRAM (synchronous dynamic random access memory) as a cache of a flash memory.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention relates to a FLASH-based cache system for mobile equipment, which comprises a graph drawing unit, an SDRAM (synchronous dynamic random access memory) module, an FLASH CACHE module and a FLASH module, wherein the graph drawing unit requests data from a FLASH CACHE module; the FLASH CACHE module requests data from the SDRAM or FLASH module and returns the required data to the graphics rendering unit.
Further, the graphics rendering unit requests data from FLASH CACHE module through the AXI bus.
Further, the FLASH CACHE module requests data from the FLASH module through the SPI bus; the FLASHCACHE module includes a TAG RAM module.
Further, the FLASH CACHE module requests data from the SDRAM module over the AXI bus.
A mobile device-oriented flash-based caching method, comprising the processes of:
the SS1 graphics rendering unit begins requesting data from module FLASH CACHE;
the SS2 judges whether the FLASH CACHE module is miss, wherein the miss is whether the data is in the SDRAM module;
when the FLASH CACHE module has no miss, the segment of data is already in SDRAM, and the direct access SDRAM module retrieves the data;
when the FLASH CACHE module is miss, the address of the corresponding block in the flash is accessed, and then the block data is retrieved and written back to SDRAM
SS3 ends.
Further, the specific process that the SS1 graphic drawing unit starts to request data from the FLASH CACHE module is as follows:
when the graphics drawing unit requests data, firstly FLASH CACHE module compares TAG of corresponding address, TAG hit indicates that the data is already in SDRAM module, otherwise indicates that the data is not retrieved to SDRAM module, and needs to access FLASH module to retrieve data.
Further, in the step of SS2, after a data request miss, a block data of adjacent address is requested from the FLASH module, and the data is written back to the SDRAM, so that the delay time of next data reading is greatly reduced.
The invention has the following beneficial effects:
the invention utilizes SDRAM as the high-speed cache of the flash memory, solves the problem of starting initialization of the mobile drawing equipment, achieves the purposes of starting and random access, realizes the starting requirement of the mobile human-computer interaction interface and the random access requirement of the mobile drawing equipment, and realizes algorithm control, pipeline architecture and prefetching strategy based on FPGA hardware architecture.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a block diagram of a flash-based cache system for a mobile device according to the present invention;
FIG. 2 is a diagram of a flash-based cache system for a mobile device according to the present invention;
FIG. 3 is an overall flow chart of FLASH CACHE;
fig. 4 is a flowchart of a graphics rendering unit requesting data.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-4, the present invention is a flash-based cache system for mobile devices, which implements an algorithm, a pipeline architecture, and a prefetch strategy using a hardware architecture, and implements the hardware architecture in an FPGA; as shown in fig. 2, a graphics rendering unit, SDRAM module, FLASH CACHE module, and FLASH module, the graphics rendering unit requesting data from module FLASH CACHE; the FLASH CACHE module requests data from the SDRAM module or the FLASH module and returns the required data to the graphics-rendering unit.
As shown in fig. 4, the graphics-rendering unit generates a data request and sends FLASH CACHE the data address to the module. And the cache compares the corresponding TAG in the TAG RAM according to the address, and judges whether the cache is miss according to the TAG. Directly reading the data in the SDRAM module under the condition of not miss; and the miss requests the data in the FLASH module and writes the data back to the SDRAM module.
As shown in fig. 1, first, the graphics drawing unit requests FLASH CACHE data through the AXI bus, and FLASHCACHE determines miss according to the TAG corresponding to the address. When not miss, FLASH CACHE requests data from the SDRAM through the AXI bus and returns data to the graphics rendering unit through the AXI bus. In Miss, FLASH CACHE requests data from FLASH over the SPI bus and writes the data back to SDRAM over the AXI bus while returning the needed data to the graphics rendering unit.
The prefetching technique is to fetch out data that is likely to be used in advance, so as to facilitate subsequent use. The specific method is that when the Cache is not hit, when the data is fetched from the main memory and sent to the processor, the data (called a data block) in adjacent units of the main memory is fetched and sent to the Cache.
For the graphics rendering process, the texture data is stored continuously in FLASH. When certain data is requested, it is highly likely that neighboring data is requested during the rendering process.
For FLASH memory features, there is a long Latency (Latency) to request data at a certain address, and the Latency to request a single data is the same as the Latency to request a segment of data.
Due to the characteristics of the graph drawing system and the FLASH, the pre-fetching strategy of the invention is to request a larger block data (generally 4KB) adjacent to an address from the FLASH after a data request miss, and write the data back to the SDRAM with shorter delay time, so that the delay time of next data reading is greatly reduced.
A mobile device-oriented flash-based caching method, comprising the processes of:
as shown in figure 3 of the drawings,
the SS1 graphics rendering unit begins requesting data from module FLASH CACHE;
the SS2 judges whether the module FLASH CACHE is miss, wherein miss is whether the data is in the SDRAM module;
when the FLASH CACHE module has no miss, the segment of data is already in SDRAM, and the direct access SDRAM module retrieves the data;
when the FLASH CACHE module has miss, the address of the corresponding block in the flash is accessed, after which the block data is retrieved and written back to SDRAM.
SS3 ends.
As shown in fig. 4, the specific process of the SS1 graphic drawing unit starting to request data from the FLASH CACHE module is as follows:
when the graphics drawing unit requests data, firstly FLASH CACHE module compares TAG of corresponding address, TAG hit indicates that the data is already in SDRAM module, otherwise indicates that the data is not retrieved to SDRAM module, and needs to access FLASH module to retrieve data.
In the step of SS2, after a data request miss, a block data of adjacent address is requested to the FLASH module, and the data is written back to SDRAM, so that the delay time of next data reading is greatly reduced.
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The preferred embodiments of the invention disclosed above are intended to be illustrative only. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims (2)
1. A FLASH-based cache system for a mobile device, comprising a graphics rendering unit, an SDRAM module, an FLASH CACHE module, and a FLASH module, characterized in that:
the graphics rendering unit requesting data from the FLASH CACHE module;
the FLASH CACHE module requests data from SDRAM or FLASH module and returns the needed data to the graph drawing unit;
the graphics rendering unit generates a data request and sends the data address to the FLASH CACHE module; the CACHE compares the corresponding TAG in the TAG RAM according to the address, and judges whether the CACHE is miss according to the TAG; directly reading the data in the SDRAM module under the condition of not miss; the miss requests the data in the FLASH module and writes the data back to the SDRAM module;
the graph drawing unit requests FLASH CACHE for data through AXI bus, FLASH CACHE judges whether miss occurs according to TAG corresponding to the address; when miss does not occur, FLASH CACHE requests data from SDRAM through AXI bus and returns data to the graphics rendering unit through AXI bus; in Miss, FLASH CACHE requests data from FLASH through SPI bus and writes the data back to SDRAM through AXI bus and returns the needed data to the graphics drawing unit;
when a data request miss, a larger block data of the adjacent address is requested to the FLASH, and the data is written back to the SDRAM with shorter delay time.
2. The caching method of the mobile device-oriented flash-based cache system according to claim 1, comprising the steps of:
the SS1 graphics rendering unit begins requesting data from module FLASH CACHE;
the SS2 judges whether the FLASH CACHE module is miss, wherein the miss is whether the request data is in the SDRAM module;
when the FLASH CACHE module does not have a miss, the request data is already in the SDRAM and the direct access SDRAM module retrieves the data;
when the FLASH CACHE module is miss, the address of the corresponding block in the flash is accessed, and then the block data is retrieved and written back to SDRAM;
SS3 ends.
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