CN106775891A - A kind of technical method suitable for realizing IAP functions in OTPMemory - Google Patents

A kind of technical method suitable for realizing IAP functions in OTPMemory Download PDF

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Publication number
CN106775891A
CN106775891A CN201611247190.2A CN201611247190A CN106775891A CN 106775891 A CN106775891 A CN 106775891A CN 201611247190 A CN201611247190 A CN 201611247190A CN 106775891 A CN106775891 A CN 106775891A
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CN
China
Prior art keywords
otp
iap
burning
functions
iap functions
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Pending
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CN201611247190.2A
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Chinese (zh)
Inventor
汪正峰
刘伟
刘江
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Macrosilicon Technology Co Ltd
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Macrosilicon Technology Co Ltd
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Application filed by Macrosilicon Technology Co Ltd filed Critical Macrosilicon Technology Co Ltd
Priority to CN201611247190.2A priority Critical patent/CN106775891A/en
Publication of CN106775891A publication Critical patent/CN106775891A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/65—Updates
    • G06F8/66—Updates of program code stored in read-only memory [ROM]

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)

Abstract

The present invention relates to a kind of technical method suitable for realizing IAP functions in OTP Memory, integrate Pump Circuit/IAP control/OTP and write algorithm, realize OTP IAP functions, make OTP chips in burning program, data preserve very convenient, and reduce system cost.The invention is characterised in that：In the built-in Pump Circuit of chip internal, self-programming OTP burning control registers, IAP functions are realized；Self-defined communications protocol, by serial line interface（USB or UART）Burning instruction is issued, burning program is completed using the IAP functions of chip internal；IAP functions are utilized in the application, and burning needs the data of record；The region of recorded mistake is avoided with rational data structure by algorithm, the demand of repeatedly record is realized.

Description

A kind of technical method suitable for realizing IAP functions in OTPMemory
Technical field
It is in present invention can apply to area information storage more particularly to a kind of suitable for realizing IAP's in OTP Memory Technical method.
Background technology
At present, in MCU applications, using OTP Memory as the chip of program carrier in, OTP needs extra outside work Tool realizes burning program, and burning needs complicated high voltage control cable and parallel communication busses control system.If in the application Need persistence data message, it is necessary in system schema external EEPROM or Flash, number is preserved by external memory storage According to, system cost is higher, the space for taking surface-mounted integrated circuit is big.
The present invention integrates Pump Circuit/IAP control/OTP and writes algorithm, realizes OTP IAP functions, OTP chips is existed Burning program, data preserve very convenient, and reduce system cost.
The content of the invention
The present invention proposes a kind of technical method suitable for realizing IAP functions in OTP Memory, and the method is such reality Existing：
In the built-in Pump Circuit of chip internal, self-programming OTP burning control registers, IAP functions are realized；Self-defined communication Agreement, by serial line interface（USB or UART）Burning instruction is issued, burning program is completed using the IAP functions of chip internal； IAP functions are utilized in application program, burning needs the data of record；Avoid recorded by algorithm and rational data structure The region crossed, realizes the demand of repeatedly record.
Suitable for realizing IAP functions in OTP Memory, it is comprised the following steps the present invention：
S1：OTP chip internals are realized, from boosting, meeting burning high voltage requirements；
The voltage of offer several times higher than normal working voltage is needed during OTP burnings, generally 7.5V or so is of the invention in chip Internal built-in Pump Circuit, in the case of without external high pressure, chip internal realizes boosting certainly using Pump Circuit Function, to meet the high voltage requirements needed for OTP burnings；
S2：Built-in associated registers, realize IAP functions；
Meet the parallel Timing interfaces of OTP burnings, chip internal hardware is realized directly controlling OTP to burn by associated registers Record Timing, realizes IAP functions；
OTP IAP CTRL are the control cores for realizing IAP functions, realize that the switch of control Pump Circuit, control are internal Bus realizes OTP programmings and provides the interface function register for realizing IAP programmings；
Chip built-in ISP module, there is provided UART OR USB Driver, and by self-defined communications protocol, by chip Serial line interface（USB or UART）Burning instruction is issued, burning program is completed using the IAP functions of chip internal；
S3：Reasonable algorithm and data structure are set up, realizes that burning function is maximized；
The program that MCU is based on OTP burnings is run, and the part of the whole non-burning in OTP spaces can answered by application program burning With IAP functions are utilized in program, burning needs the data of record, and memory is needed after a power failure to realize preserving in the application Data message；
By algorithm and rational data structure, the region of recorded mistake is avoided, realize repeatedly record demand, solve OTP every Individual unit can only write the problem that cannot once repeat to write.
The present invention has the advantages and positive effects that：Integrate Pump Circuit/IAP control/OTP and write algorithm, realize OTP IAP functions, make OTP chips in burning program, and data preserve very convenient, and reduce system cost.
Brief description of the drawings
Fig. 1 is OTP Memory IAP invention realization principle block diagrams.
Fig. 2 is that the present invention program schemes with tradition OTP scheme comparisons.
Fig. 3 is present system application and tradition OTP system Comparison study figures.
Specific embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with chart and embodiment The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only used to explain the present invention, not For limiting the present invention.
The present invention realizes integrated boost circuit, self-programming control logic in OTP chips, realizes IAP functions.
Because the memory cell of OTP can only realize a data recording, so in actual applications, taking following algorithm reality Existing OTP data records number of times is maximized.
When OTP SIZE are 64K, IAP reality current data programmed orders：
S1：From last 1 Bytes addresses (0FFFFH) reading it is judged that whether being 0FFH（The region of code is crossed in the non-burnings of OTP Value）, address subtracts 1 successively, untill discovery is not for the data address of 0FF；
XX marks address location address in table, the address of the writeable data of IAP is the address+1；
Address 0 0 2 3 4 5 6 7 8 9 A B C D E F
0000H XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX
0010H XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX
…… XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX
…… XX XX XX XX XX XX XX FF FF FF FF FF FF FF FF FF
XXXH FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FFD0H FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FFE0H FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FFF0H FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
S2：S1 steps determine the first address of the writeable data of IAP, and the data YY to be write using IAP functional programmings, it is assumed that data Length is L Bytes；
S3：Termination flag ZZ is write in last 1 Bytes insertions（ZZ is not equal to 0FFH）；YY is the data of IAP write-ins, during ZZ is Only identify；
Address 0 1 2 3 4 5 6 7 8 9 A B C D E F
0000H XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX
0010H XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX
…… XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX
…… XX XX XX XX XX XX XX YY YY YY YY YY YY YY YY YY
XXXH YY YY YY YY YY YY YY YY ZZ FF FF FF FF FF FF FF
FFD0H FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FFE0H FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FFF0H FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
S4：If continuing to have data needs write-in, S1 steps are jumped to, now ZZ positions are final data address.
The data Flow that application program reads IAP write-ins is as follows：
S1：From last 1 Bytes addresses (0FFFFH) reading it is judged that whether being 0FFH, address subtracts 1 successively, until finding not For 0FF data address untill；
S2：If last numeral for being not equal to 0FFH is equal to ZZ, it indicates that the number of data bit user IAP write-ins above According to；
S3：Data before ZZ addresses are read according to custom data form and is parsed.
Can effectively realize replacing EEPROM or Flash Memory with OTP by above-mentioned Flow, and reduce OTP can only one Influence of the defect that secondary property is write to practical application.

Claims (4)

1. a kind of technical method suitable for realizing IAP functions in OTP Memory, it is characterised in that integrate Pump Circuit/IAP control/OTP write algorithm, realize OTP IAP functions.
2. according to claim 1, it is characterised in that OTP chip internals are realized, from boosting, meeting burning high voltage requirements； In the built-in Pump Circuit of chip internal, in the case of without external high pressure, chip internal is using Pump Circuit from fact Existing boost function, to meet the high voltage requirements needed for OTP burnings.
3. according to claim 2, it is characterised in that built-in associated registers, IAP functions are realized；Built-in self-programming OTP burns Record control register, realizes IAP functions；Self-defined communications protocol, by serial line interface（USB or UART）Burning instruction is issued, Burning program is completed using the IAP functions of chip internal；And IAP functions are utilized in the application, burning needs the number of record According to.
4. according to claim 3, it is characterised in that set up reasonable algorithm and data structure, the region for having recorded is avoided, Realize that burning function is maximized.
CN201611247190.2A 2016-12-29 2016-12-29 A kind of technical method suitable for realizing IAP functions in OTPMemory Pending CN106775891A (en)

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CN201611247190.2A CN106775891A (en) 2016-12-29 2016-12-29 A kind of technical method suitable for realizing IAP functions in OTPMemory

Applications Claiming Priority (1)

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CN201611247190.2A CN106775891A (en) 2016-12-29 2016-12-29 A kind of technical method suitable for realizing IAP functions in OTPMemory

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI699101B (en) * 2019-09-19 2020-07-11 英業達股份有限公司 System and method for online cascaded loading firmware based on boundary scan
TWI831312B (en) * 2022-07-29 2024-02-01 大陸商北京集創北方科技股份有限公司 Programming control circuits, one-time programmable memory devices, electronic chips and information processing devices

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101359509A (en) * 2008-09-02 2009-02-04 北京芯技佳易微电子科技有限公司 Disposable programmable memory circuit and programming and reading method thereof
CN102611974A (en) * 2012-03-09 2012-07-25 无锡纳讯微电子有限公司 MEMS (micro-electro mechanical system) microphone circuit, upper computer circuit and method for accessing into programming mode
CN105302570A (en) * 2015-11-17 2016-02-03 广州周立功单片机科技有限公司 Chip programming control method and system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101359509A (en) * 2008-09-02 2009-02-04 北京芯技佳易微电子科技有限公司 Disposable programmable memory circuit and programming and reading method thereof
CN102611974A (en) * 2012-03-09 2012-07-25 无锡纳讯微电子有限公司 MEMS (micro-electro mechanical system) microphone circuit, upper computer circuit and method for accessing into programming mode
CN105302570A (en) * 2015-11-17 2016-02-03 广州周立功单片机科技有限公司 Chip programming control method and system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
EVAN SCHULZ: ""Using low-cost OTP MCUs to simplify embedded apps"", 《HTTP://H5IP.CN/VNTX》 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI699101B (en) * 2019-09-19 2020-07-11 英業達股份有限公司 System and method for online cascaded loading firmware based on boundary scan
TWI831312B (en) * 2022-07-29 2024-02-01 大陸商北京集創北方科技股份有限公司 Programming control circuits, one-time programmable memory devices, electronic chips and information processing devices

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Application publication date: 20170531