CN106774625A - A kind of Parallel Implementation method of real-time phase noise hardware generator - Google Patents
A kind of Parallel Implementation method of real-time phase noise hardware generator Download PDFInfo
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Abstract
The invention discloses a kind of Parallel Implementation method of real-time phase noise hardware generator.Can realize that phase noise in real time, at a high speed, parallel is simulated on FPGA processor using the present invention.The present invention is primarily based on the FPGA high-speed parallel implementation methods of the uniform white noise of cellular automaton theory, gives the recurrence function relation of the computational methods of N roads initial vector and cellular automaton parallel generation algorithm needed for Parallel Implementation；Then, on the basis of real-time parallel generation white noise, parallel first order IIR filtering device group is designed, by setting the yield value at corner frequency, realizes that the noise for meeting power law spectral property is exported by filtering；Finally, the equivalents of phase noise are obtained by above-mentioned white noise, completion phase noise simulation is superimposed with useful signal.The present invention can under relatively low FPGA resource consumption, in real time, at high speed the generation cycle it is long, with the measured white noise of roomy, matter, and realize the controllable phase noise analog hardware generator of parameter on this basis.
Description
Technical field
The present invention relates to satellite communication system simulation, phase noise modeling technique field, and in particular to a kind of real-time phase
The Parallel Implementation method of noise hardware generator.
Background technology
Satellite communication system analogue technique on ground due to that can reappear an ideal, deterioration, even almost real electricity
Ripple communication environments, when various in analog satellite communication link, the influence propagated signal of space-variant, already as communication, observing and controlling
Etc. the indispensable validation test means of technical field.Radio wave, can be inevitable in satellite communication link transmitting procedure
Influenceed by noise jamming, channel fading, ionospheric scintillation, the transponder random non-ideal characteristic such as non-linear.Wherein, influence
One principal element of satellite communication system transmission error rates is the phase noise deterioration of transponder local oscillation signal on star.For
The influence of research local oscillation signal phase noise, domestic and foreign scholars generally based on white noise modeling, by various linear or
Nonlinear complex transformations, obtain the noise with power law spectral property, emulate phase noise characteristic.It can be seen that, study phase noise
Theoretical and implementation method is modeled to satellite communication link, emulation and simulation are respectively provided with significance.
Research data shows, the production method of white noise mainly includes linear congruent algorithm, postpones Fibonacci method, linear
Shift register method and cellular automaton theory etc..Compared with Fibonacci method is postponed, the former is in random number point for linear congruential method
Effect is poor in the performance tests such as uniformity, the subsequence dependence of cloth, but the latter needs more multiplier resources,
FPGA (Field Programmable Gate Array) hardware resource consumption is big.Linear shift register method is application at present
A kind of widest method, with algorithm it is simple, speed is fast, repeatability is strong and is easy to FPGA hardware the outstanding advantages such as realizes.
However, because the method has linear feedback structure, can cause its pseudo random number for producing that there is stronger correlation, it is uniform white
Noise produces quality relatively poor.Comparatively speaking, cellular automaton theory is the generation for being just used for uniform white noise in recent years, by
There are the outstanding advantages such as the cycle is long, speed is fast, statistical property good, realization occupancy hardware resource is few in its noise for producing, once
Appearance just receives the extensive concern of domestic and foreign scholars.
Both at home and abroad on phase noise analogy method, mainly there is the method based on wavelet transformation, based on fractional order integration
Method of method, the method based on inverse FFT and time-domain filtering etc..Because the series of wavelet transformation is limited, power law is set a song to music
Line has waviness phenomena.Fractional order integration method need to make corresponding limitation on the basis of Brownian movement makes the discrete noise sequence of generation
Time domain convergence is listed in, because the time domain of Brownian movement is non-stationary, it is impossible to obtain reasonable system function corresponding with Brownian movement.
Need accurately to portray the power spectral density of actual phase noise based on inverse FFT method, and inverse transformation process needs
Closed solutions, because phase noise time domain is uncertain, it is difficult to obtain closed solutions.Comparatively speaking, the method for time-domain filtering is by changing
Become the coefficient gain of iir filter and be combined generation power rate characteristic curve, led to white noise with noise shaping theoretical foundation
Filtering is crossed to produce phase noise.However, it is existing based on time-domain filtering method realize phase noise simulate when exist it is real-time
The poor, speed of property is low.
The content of the invention
In view of this, the invention provides a kind of Parallel Implementation method of real-time phase noise hardware generator, based on thin
Cellular automaton theory and time-domain filtering method, can realize real-time, high speed, parallel phase noise mould on FPGA processor
Intend.
The Parallel Implementation method of real-time phase noise hardware generator of the invention, comprises the following steps：
Step 1, it is the cellular automaton of null boundary 90/150 rule to select cellular automaton rule, under this rule, according to
The Cycle Length for intending generation white noise calculates the order M and regular vector d for obtaining cellular automaton, wherein, d={ d (m), m=
1,2 ..., M }, element d (m) in rule vector is 0 or 1；
Step 2, sets the initial vector s of cellular automaton0It is s0={ s0(m), m=1,2,3..., M }, and initial vector
It is non-vanishing vector；Wherein, element s0M () is 0 or 1；
Step 3, produces one group of uniform white noise of Parallel Implementation inside FPGA, specifically includes following sub-step：
Step 3.1, the sample frequency f according to real application systemssWith the work clock f of FPGAclk, calculate parallel wayWhereinExpression rounds up；
Step 3.2 is according to rule vector d and initial vector s0, obtain the initial vector s on the parallel each road under regular vector dp
={ sp(m), m=1,2 ..., M }, p=1,2 ..., N；
Wherein, parallel 1st road initial vector s1Middle arbitrary element s1M () is：
Wherein, symbolTable XOR, m=1,2,3 ..., M；s0(0) ≡ 0, s0(M+1)≡0；
Any parallel pth road initial vector spMiddle element spM () is：
And sp(0) ≡ 0 and sp(M+1)≡0
Step 3.3, according to the cellular automaton of null boundary 90/150 rule, is derived by the parallel each road under regular vector d
Recurrence function f；Wherein, cp(n)=f (cp(n-1)), p=1,2 ..., N；Wherein, cpN () is pth road, the state at the n-th moment
Vector, cp(n-1) it is pth road, the state vector at the (n-1)th moment, cp(0)=sp；
Step 3.4, N number of initial vector s that step 3.2 is producedpIt is considered as one group of binary number of Mbit, according to step
The 3.3 recurrence function relation f, the parallel generation N roads uniform white noise w in FPGA for derivingp(n), p=1,2 ..., N；
Step 4, generates the phase noise on parallel N roads, specifically includes following sub-step：
Step 4.1, for parallel each road, builds first order IIR filtering device group in parallel, wherein, each first order IIR filtering device point
Not Dui Yingyu each section of phase noise two-power-law distribution character, wherein, the transmission function of k-th first order IIR filtering device isWherein,fkTo intend k-th frequency of analogue phase noise；AkMade an uproar to intend analogue phase
The phase noise value of k-th frequency of sound, k=1,2 ..., K；
Step 4.2, parallel each road carries out shaping filter using its first order IIR filtering Qi Zuduigai roads uniform white noise in parallel
, then be added for filter result by ripple, and generation meets the noise of power law spectral property, is denoted as
Step 4.3, on parallel each road, the phase noise of generation and input signal is modulated, and generation superposition phase is made an uproar
Signal after sound；
Step 5, after carrying out parallel-serial converter treatment in order to the signal after the N roads superposition phase noise of step 4 generation,
The output signal with phase noise is produced through digital-to-analogue conversion.
Further, in the step 1, rule vector is obtained by Euclidean algorithm or table look-up.
Beneficial effect：
Present invention contrast prior art, has the following advantages that：
First, it is proposed that the uniform white noise parallel generation algorithm based on cellular automaton theory and the realization based on FPGA
Method.On the basis of cellular automaton theory, the present invention is according to uniform white noise Cycle Length, the height of real system that need to be produced
Fast sample frequency and FPGA tick-over clocks, give the choosing method of cellular automaton rule, order and parallel way, push away
The recurrence function for having led the computational methods of N roads initial vector and cellular automaton parallel generation algorithm needed for Parallel Implementation is closed
System, finally gives the FPGA high-speed parallel implementation methods of the uniform white noise based on cellular automaton.Therefore, the present invention is carried
Method has taken into account the plurality of advantages that cellular automaton theory generates uniform white noise, such as the cycle is long, speed is fast, statistical property good,
Realize that occupancy hardware resource lacks, while drastically increasing the real-time and formation speed of uniform white noise.
Then, on the basis of real-time parallel generation white noise, parallel first order IIR filtering device group is designed, by setting
Yield value at corner frequency, realizes that the noise for meeting power law spectral property is exported by filtering.
Finally, the equivalents of phase noise are obtained by above-mentioned white noise, completion phase noise mould is superimposed with useful signal
Intend, and the phase noise simulation of different power law spectrums can be realized by adjusting filter gain parameter.
In sum, the white noise production method that the present invention is previously mentioned in phase noise simulation process is sent out with existing hardware
Raw device is compared, can under relatively low FPGA resource consumption, in real time, at high speed the generation cycle it is long, with the measured white noise of roomy, matter
Sound, and the controllable phase noise analog hardware generator of parameter is realized on this basis.
Brief description of the drawings
Fig. 1 is phase noise simulated implementation structured flowchart.
Fig. 2 is hardware generator structured flowchart of the present invention.
Specific embodiment
Develop simultaneously embodiment below in conjunction with the accompanying drawings, and the present invention will be described in detail.
The invention provides a kind of Parallel Implementation method of real-time phase noise hardware generator, managed according to cellular automaton
By with IIR filterings, it is parallel on FPGA, in real time, generate power-law noise at high speed, and on this basis with effectively letter
Number superposition, complete parameter controllable phase noise simulation.The present invention first, is adopted according to noise periods length, the high speed of real system
Sample frequency and FPGA tick-over clocks etc., determine order, rule and the parallel way of cellular automaton；Then, according to cell
Automatic machine order and rule, regular vector is obtained using Euclidean algorithm or table look-up；Meanwhile, according to cellular automaton theory,
Required N roads initial vector and function recurrence relation during derivation Parallel Implementation vectorial by the non-zero initial for arbitrarily setting, and
One group of uniform white noise of FPGA inside generation；Then, according to the frequency and the corresponding phase noise of frequency for intending analogue phase noise
Value, designs first order IIR filtering device group in parallel, and give the transmission function of first order IIR filtering device；Finally white noise is passed through
First order IIR filtering device group filtering in parallel, is met the output noise of Power Law, by the equivalents of phase noise with
Input signal is modulated and is capable of achieving simulation of mutually making an uproar to useful signal, by being put outside parallel-serial converter and D/A.
Comprise the following steps that：
Step 1：The Cycle Length of white noise is produced as needed, determines the rule and order of cellular automaton.
If the Cycle Length for needing to produce white noise is L, in order to generate longer cycle with relatively low cellular automaton order
Uniform white noise, present invention selection null boundary 90/150 cellular automaton rule.Under this cellular automaton rule, order M
It is calculated as follows：
Wherein,Expression rounds up operation.
Step 2：The cellular automaton of null boundary 90/150 rule and order M determined according to step 1, can be by Euclid
Algorithm or table look-up obtains a rule vector of M rank cellular automatons, is denoted as：
D={ d (m), m=1,2 ..., M },
Wherein element only exists 0 and 1 two kind of possibility, i.e. d (m) ∈ { 0,1 } in rule vector.
Step 3：The non-vanishing vector of any M element is set as the initial vector of cellular automaton, wherein each element
Only 0 or 1 two kind of value, it is denoted as s0={ s0(m), m=1,2,3..., M }, wherein m represents the position of element in vector, and deposits
In s0(m)∈{0,1}。
Step 4：According to cellular automaton rule, order M, regular vector d, initial vector s0, derive cellular automaton
Parallel Implementation algorithm, and one group of uniform white noise of Parallel Implementation is produced inside FPGA.
It is specific as follows：
Step 4.1：Sample frequency f according to real application systemssThe work clock to be used is realized with FPGA hardware
fclk, calculate parallel wayWhereinExpression rounds up operation.
Step 4.2：According to rule vector d and initial vector s0, by cellular automaton theory recursion generation Parallel Implementation institute
The N number of initial vector for needing, is designated as sp={ sp(m), m=1,2 ..., M；P=1,2 ..., N }, wherein m ∈ [1, M] represent vector
The position of middle element, p ∈ [1, N] represent parallel way.
This step by step concrete principle it is as follows：
According to cellular automaton theory, the initial vector s on parallel pth=1 tunnel1Middle arbitrary element s1M () can be by regular vector
D and initial vector s0Middle element is calculated as follows：
Wherein, symbolTable XOR, vector element position m=1,2,3 ..., M.According to the cell of null boundary 90/150
, there is s in automatic machine rule0(0) ≡ 0 and s0(M+1)≡0。
Any parallel pth road initial vector spMiddle element can be by the road of pth -1 initial vector sp-1Middle element and regular vector d1
It is calculated as follows：
Wherein, there is s in p=2,3 ..., Np(0) ≡ 0 and sp(M+1)≡0。
Therefore, according to rule vector d and initial vector s0, as needed for recursion by (2) and (3) formula obtains Parallel Implementation
N number of initial vector sp={ sp(m), m=1,2 ..., M, p=1,2 ..., N }.
Step 4.3：According to the cellular automaton of null boundary 90/150 rule, the function on any pth road when deriving Parallel Implementation
Recurrence relation cp(n)=f (cp(n-1))。
This step by step principle it is as follows：
According to cellular automaton theory, any n-th moment state vector s (n)={ s (m, n), m=1 ..., M；N=0,
1 ... } in arbitrary element s (m, n) can be calculated as follows under the rule of null boundary 90/150：
Wherein, d (m) is element in any regular vector d.
It is known quantity and to only exist 0 or 1 two kind of value in view of any regular vector d, therefore by (4) formula recursion 1 time, can
I other words, the state vector s (n+1) at the (n+1)th moment is unrelated with regular vector, can be by the n-th moment state vector s
N () is by fixed functional relation f1Represent, be designated as s (n+1)=f1(s(n))。
Similarly, recursion is carried out according to (4) (5) two formula again, the functional relation f that s (n+2) and s (n) determines can be obtained2, it is designated as
S (n+2)=f2(s(n))。
The like, after recursion n times, can obtain
S (n+N)=f (s (n)) (6)
I other words, the n-th+N can be directly calculated by state vector s (n) at the n-th moment according to the functional relation f for determining
The state vector s (n+N) at moment.
If in view of cellular automaton by N roads Parallel Implementation, any pth road, the n-th moment Parallel Implementation cellular automaton
Produced state vector cp(n)={ cp(m, n), m=1 ..., M；N=0,1 ... } original serial cellular automaton should be corresponded to
(6) state vector at N × (n-1)+p moment that formula is produced.I other words, there is following relation：
It can be seen from (6) and (7) formula, equal sign the right state vector meets：S (N × (n-1)+p)=f (s (N × (n-2)+
P)), the state vector c of such Parallel Implementationp(n) and cp(n-1) equally exist：
cp(n)=f (cp(n-1)) (8)
I other words, any pth road, the state vector c at the n-th momentpN () can be by the state vector c of previous momentp(n-1) press
Unified functional relation f is calculated.
Step 4.4：The N number of initial vector s containing individual 0,1 elements of M that step 4.2 is producedpIt is considered as Mbit binary numbers, root
According to the recurrence function relation f that step 4.3 is derived, the parallel generation N roads uniform white noise in FPGA.
This step by step principle it is as follows：
If setting cp(n)={ cp(m, n), m=1 ..., M, n=1 ..., ∞；P=1 ..., N } it is any pth road, n-th
The 1st group of state vector that moment produces, then cpN () recursion can obtain as the following formula：
cp(n)=f (cp(n-1)) (9)
Wherein, cp(0)=sp, n=1 ..., ∞, p=1 ..., N.
When specific FPGA is realized, first by state vector cpN M 0,1 element regards Mbit binary numbers as in (), then by (9)
The functional relation f that formula determines carries out recursion, thus can obtain the Mbit uniform white noise values of parallel generation, and w is designated as againp(n),
P=1,2 ..., N；N=1,2 ....
Step 5：N roads white noise based on step 4 generation carries out time domain IIR filtering and realizes that phase noise is simulated, and generation is full
The phase noise of the power exponent distribution of sufficient power law spectrum model is simultaneously superimposed with input signal.
Step 5.1：The realization of phase noise is after being filtered to input white noise by several first order IIR filtering devices in parallel
Superposition is obtained, and realizes that block diagram is as shown in Figure 1；Wherein, each first order IIR filtering device corresponds respectively to phase noise two-power-law point
Each section of cloth characteristic, wherein, the transmission function of k-th first order IIR filtering device is
Wherein,fkTo intend k-th frequency of analogue phase noise；AkTo intend k-th of analogue phase noise
The phase noise value of frequency.
Assuming that the phase noise frequency for intending simulation is fk=10Hz, 100Hz, 1KHz, 10KHz, 100KHz, at each frequently
A first order IIR filtering device is needed at point, thus k=5, filter coefficient a can be obtained by formula (10)k=1-wk；
Step 5.2：Realize that parallel each road utilizes its first order IIR filtering Qi Zuduigai roads uniform white noise in parallel in FPGA
Molding filtration is carried out, then filter result is added, the noise for meeting power law spectral property of generation is denoted as
Step 5.3：On parallel each road, the phase noise of generation and input signal are modulated, generation superposition phase is made an uproar
Signal after sound.
Derived according to correlation theory, it is known that phase noise approximate representation isCan be represented with Signal averaging process
For：
Multiplied result is intercepted into M high0Bit, wherein M0It is the number of significant digit of D/A.So far, the parallel product of phase noise is completed
The raw and additive process with signal.
Step 6：To the output signal s after the N roads superposition phase noise of step 5 generationp(n), p=1,2 ..., N is by suitable
After sequence carries out parallel-serial converter treatment, the output signal with phase noise is produced through being put outside D/A.
In sum, presently preferred embodiments of the present invention is these are only, is not intended to limit the scope of the present invention.
All any modification, equivalent substitution and improvements within the spirit and principles in the present invention, made etc., should be included in of the invention
Within protection domain.
Claims (2)
1. a kind of Parallel Implementation method of real-time phase noise hardware generator, it is characterised in that comprise the following steps：
Step 1, it is the cellular automaton of null boundary 90/150 rule to select cellular automaton rule, under this rule, is given birth to according to plan
Cycle Length into white noise calculates the order M and regular vector d of acquisition cellular automaton, wherein, d=d (m), m=1,
2 ..., M }, element d (m) in rule vector is 0 or 1；
Step 2, sets the initial vector s of cellular automaton0It is s0={ s0(m), m=1,2,3..., M }, and initial vector is non-
Null vector；Wherein, element s0M () is 0 or 1；
Step 3, produces one group of uniform white noise of Parallel Implementation inside FPGA, specifically includes following sub-step：
Step 3.1, the sample frequency f according to real application systemssWith the work clock f of FPGAclk, calculate parallel wayWhereinExpression rounds up；
Step 3.2 is according to rule vector d and initial vector s0, obtain the initial vector s on the parallel each road under regular vector dp=
{sp(m), m=1,2 ..., M }, p=1,2 ..., N；
Wherein, parallel 1st road initial vector s1Middle arbitrary element s1M () is：
Wherein, symbolTable XOR, m=1,2,3 ..., M；s0(0) ≡ 0, s0(M+1)≡0；
Any parallel pth road initial vector spMiddle element spM () is：
And sp(0) ≡ 0 and sp(M+1)≡0
Step 3.3, according to the cellular automaton of null boundary 90/150 rule, the parallel each road being derived by under regular vector d is passed
Push away function f；Wherein, cp(n)=f (cp(n-1)), p=1,2 ..., N；Wherein, cp(n) be pth road, the state at the n-th moment to
Amount, cp(n-1) it is pth road, the state vector at the (n-1)th moment, cp(0)=sp；
Step 3.4, N number of initial vector s that step 3.2 is producedpIt is considered as one group of binary number of Mbit, is derived according to step 3.3
Recurrence function relation f, the parallel generation N roads uniform white noise w in FPGAp(n), p=1,2 ..., N；
Step 4, generates the phase noise on parallel N roads, specifically includes following sub-step：
Step 4.1, for parallel each road, builds first order IIR filtering device group in parallel, wherein, each first order IIR filtering device is right respectively
Should in each section of phase noise two-power-law distribution character, wherein, the transmission function of k-th first order IIR filtering device isWherein,fkTo intend k-th frequency of analogue phase noise；AkMade an uproar to intend analogue phase
The phase noise value of k-th frequency of sound, k=1,2 ..., K；
Step 4.2, parallel each road carries out molding filtration using its first order IIR filtering Qi Zuduigai roads uniform white noise in parallel, so
Filter result is added afterwards, generation meets the noise of power law spectral property, is denoted as
Step 4.3, on parallel each road, the phase noise of generation and input signal is modulated, after generation superposition phase noise
Signal；
Step 5, after carrying out parallel-serial converter treatment in order to the signal after the N roads superposition phase noise of step 4 generation, through number
Mould conversion produces the output signal with phase noise.
2. the Parallel Implementation method of white Gaussian noise hardware generator in real time as claimed in claim 1, it is characterised in that described
In step 1, rule vector is obtained by Euclidean algorithm or table look-up.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107483019A (en) * | 2017-06-20 | 2017-12-15 | 深圳市鼎阳科技有限公司 | A kind of white noise production method and device |
| CN109581114A (en) * | 2018-12-11 | 2019-04-05 | 武汉水院电气有限责任公司 | A kind of power frequency component and impact signal superposition phase control circuit |
-
2016
- 2016-11-24 CN CN201611053420.1A patent/CN106774625A/en active Pending
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| 张晖: "相位噪声模拟器实现技术研究", 《电子技术应用》 * |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107483019A (en) * | 2017-06-20 | 2017-12-15 | 深圳市鼎阳科技有限公司 | A kind of white noise production method and device |
| CN109581114A (en) * | 2018-12-11 | 2019-04-05 | 武汉水院电气有限责任公司 | A kind of power frequency component and impact signal superposition phase control circuit |
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