CN106711051A - La-based medium material high-K metal gate structure based on Si substrate and preparation method thereof - Google Patents
La-based medium material high-K metal gate structure based on Si substrate and preparation method thereof Download PDFInfo
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 67
- 239000002184 metal Substances 0.000 title claims abstract description 67
- 239000000758 substrate Substances 0.000 title claims abstract description 22
- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 239000000463 material Substances 0.000 title claims abstract description 12
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims abstract description 22
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 17
- 239000001301 oxygen Substances 0.000 claims abstract description 16
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 16
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims abstract description 13
- 229910052593 corundum Inorganic materials 0.000 claims abstract description 13
- 229910001385 heavy metal Inorganic materials 0.000 claims abstract description 13
- 229910001845 yogo sapphire Inorganic materials 0.000 claims abstract description 13
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910002244 LaAlO3 Inorganic materials 0.000 claims abstract description 11
- 238000001179 sorption measurement Methods 0.000 claims abstract description 9
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000010408 film Substances 0.000 claims description 73
- 235000012431 wafers Nutrition 0.000 claims description 67
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 45
- 238000006243 chemical reaction Methods 0.000 claims description 36
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- 229910052757 nitrogen Inorganic materials 0.000 claims description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims description 24
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 20
- UMAHMMJKEZXFRU-UHFFFAOYSA-N 1,2,3-tri(propan-2-yl)cyclopenta-1,3-diene Chemical compound CC(C)C1=C(C(C)C)C(C(C)C)=CC1 UMAHMMJKEZXFRU-UHFFFAOYSA-N 0.000 claims description 19
- 239000003989 dielectric material Substances 0.000 claims description 19
- 229910052746 lanthanum Inorganic materials 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 17
- 238000010926 purge Methods 0.000 claims description 17
- 238000004151 rapid thermal annealing Methods 0.000 claims description 17
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 16
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- 238000000231 atomic layer deposition Methods 0.000 claims description 13
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 claims description 13
- 239000008367 deionised water Substances 0.000 claims description 12
- 229910021641 deionized water Inorganic materials 0.000 claims description 12
- 239000006227 byproduct Substances 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 9
- 239000010409 thin film Substances 0.000 claims description 9
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 8
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910010037 TiAlN Inorganic materials 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- 239000007789 gas Substances 0.000 claims description 8
- 125000001449 isopropyl group Chemical group [H]C([H])([H])C([H])(*)C([H])([H])[H] 0.000 claims description 8
- 238000005137 deposition process Methods 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 7
- 125000004430 oxygen atom Chemical group O* 0.000 claims description 7
- MWQKURVBJZAOSC-UHFFFAOYSA-N 1-propan-2-ylcyclopenta-1,3-diene Chemical compound CC(C)C1=CC=CC1 MWQKURVBJZAOSC-UHFFFAOYSA-N 0.000 claims description 5
- 229910002425 LaScO3 Inorganic materials 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
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- 238000001704 evaporation Methods 0.000 claims description 4
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- 238000001020 plasma etching Methods 0.000 claims description 4
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- 230000008023 solidification Effects 0.000 claims description 4
- 229910001868 water Inorganic materials 0.000 claims description 4
- 229910018512 Al—OH Inorganic materials 0.000 claims description 3
- WSFSSNUMVMOOMR-UHFFFAOYSA-N Formaldehyde Chemical compound O=C WSFSSNUMVMOOMR-UHFFFAOYSA-N 0.000 claims description 3
- 238000010276 construction Methods 0.000 claims description 3
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 claims description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims description 2
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- 238000010521 absorption reaction Methods 0.000 claims 1
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- 230000005669 field effect Effects 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 6
- 239000005001 laminate film Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000000427 thin-film deposition Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- -1 Pt Category reaction Chemical compound 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
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- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000008246 gaseous mixture Substances 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- CMIAIUZBKPLIOP-YZLZLFLDSA-N methyl (1r,4ar,4br,10ar)-7-(2-hydroperoxypropan-2-yl)-4a-methyl-2,3,4,4b,5,6,10,10a-octahydro-1h-phenanthrene-1-carboxylate Chemical compound C1=C(C(C)(C)OO)CC[C@@H]2[C@]3(C)CCC[C@@H](C(=O)OC)[C@H]3CC=C21 CMIAIUZBKPLIOP-YZLZLFLDSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 150000002910 rare earth metals Chemical class 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a La-based medium material high-K metal gate structure based on a Si substrate and a preparation method thereof, and mainly solves the problems that the gate oxide dielectric constant of the conventional high-K metal gate structure is low and gate metal is diffused to the gate oxide. The high-K metal gate structure comprises a La-based high-k gate medium film (1), a TiN barrier layer (2), a Ti oxygen adsorption layer (3) and a heavy metal Pt gate electrode (4) which are arranged on the Si substrate from the bottom to the top. A La2O3 or LaAlO3 or La2O3/Al2O3 laminated structure of which the thickness is 4-10nm is adopted for the La-based high-k gate medium film; the thickness of the TiN barrier layer is 2-3nm; the thickness of the Ti oxygen adsorption layer is 4-6nm; and the thickness of the heavy metal Pt gate electrode is 100-150nm. The gate oxide dielectric constant is high and the gate oxide/substrate interface property is great so that the structure can be used for manufacturing a high-dielectric-property metal oxide semiconductor field effect transistor.
Description
Technical field
The invention belongs to semiconductor materials and devices technical field, more particularly to a kind of high-K metal gate structure and preparation side
Method, can be used for manufacture high dielectric property mos field effect transistor, and large scale integrated circuit production
With preparation.
Background technology
Integrated level with integrated circuit constantly reduces, the size of mos field effect transistor MOSFET
Constantly reduce, corresponding gate-oxide thicknesses also constantly reduce.By the end of 2005, the photoetching technique of 65nm tended into
It is ripe, as the SiO of gate dielectric film in high performance FET device2The thickness of layer has reduced to 1nm or so, i.e., only
It is the spacing of several atomic layers.With the continuous reduction of oxide thickness, the electric leakage caused by electron tunneling is exponentially increased, by
This high power consumption for causing and integrity problem are more and more severeer, while excessively thin gate oxide is also not enough to block gate medium and crystalline substance
The diffusion of impurity in circle, can cause threshold voltage shift, influence device performance.In order to solve the above problems, Intel Company exists
65nm techniques are improved within 2007, using high-k gate dielectric material HfO2Substitution conventional gate dielectric film SiO2Layer, by k gate oxides high
+ metal gate structure replaces traditional SiO2+ polysilicon gate construction has been applied in its MOSFET technique.High-k
Material can have larger physical thickness while holding capacitor density is constant, solve SiO2Because close to physical thickness pole
The problems such as electric leakage for limiting and producing and reliability.But HfO2Relative dielectric constant be only about 14, with holding for device size
Continuous scaled down, HfO2The demand of integrated circuit development can not have been met, it is necessary to introduce the bigger gate medium of dielectric constant
Material.
Most representational La based compounds, such as La in rare-earth oxide2O3、LaAlO3、HfLaOxAnd LaLuO3Deng,
It is 25 and good heat endurance because it possesses the energy gap more than 5.5eV, gate breakdown field intensity high, dielectric constant, incites somebody to action
As one of most promising high dielectric constant material of future generation.But because wafer Si is in La base high-k gate dielectric films
High diffusivity coefficient, can be readily formed the boundary layer of low-k, can thus increase equivalent oxide thickness, deteriorate device
Interfacial characteristics.
On the other hand, traditional high-K metal gate structure directly deposits heavy metal as gate electrode on k gate oxides high
Conductive layer, because heavy metal ion can spread to k gate oxides high, and can introduce impurity, by serious shadow in k gate oxides high
The oeverall quality of high-K metal gate structure is rung, increases grid leakage current, so as to influence the reliability of device.
The content of the invention
Deficiency it is an object of the invention to be directed to above-mentioned prior art, proposes a kind of La base medium materials based on Si substrates
Material high-K metal gate structure and preparation method, to reduce the thickness of La bases high-k gate dielectric films and wafer interface boundary layer, subtract
Diffusion of the weak heavy metal ion in k gate oxides high, so as to improve the electrology characteristic of high-K metal gate structure, improves device
Reliability.
To achieve the above object, La based dielectric material high-K metal gate structure of the present invention based on Si substrates, on a si substrate
Include La bases high-k gate dielectric films and heavy metal Pt gate electrodes (4) from bottom to top, it is characterised in that：La base high-k gate dielectric films
(1) TiN barrier layers (2) and Ti oxygen elements adsorption layer (3) are had additional and heavy metal Pt gate electrodes (4) between；The TiN barrier layers
(2) thickness is 2-3nm, on La bases high-k gate dielectric films (1), to barrier metal Ti and heavy metal Pt to La bases
High-k gate dielectric films (1) spread；Ti oxygen elements adsorption layer (3) thickness be 4-6nm, on TiN barrier layers (2), with
The oxygen element of La bases high-k gate dielectric films (1) and wafer Si interfaces is adsorbed during thermal anneal process.
To achieve the above object, the preparation method of La based dielectric material high-K metal gate structure of the present invention based on Si substrates,
Comprise the following steps：
(1) Si wafers are cleaned；
(2) it is the La of 4-10nm to use atomic layer deposition method deposition thickness on Si wafers2O3Or LaAlO3Or HfLaOx
Or LaScO3Or LaLuO3La base high-k gate dielectric films；
(3) substrate for depositing La base high-k gate dielectric films is carried out into the fast speed heats of 60-90s under 500-700 DEG C of vacuum
Annealing；
(4) after thermal annealing, the TiN for depositing 2-3nm thickness on La base high-k gate dielectric films using e-beam evaporation is thin
Film；
(5) the thick metal Ti films of 4-6nm are deposited in TiAlN thin film using magnetically controlled sputter method；
(6) the thick Pt metal films of 100-150nm are deposited on metal Ti films using magnetically controlled sputter method；
(7) using the Pt metal film of photoetching process treatment deposit, gate electrode is formed, obtains La base high-k gate dielectric materials
High-K metal gate structure；
(8) 97%N by the high-K metal gate structure of La base high-k gate dielectric materials at 300-500 DEG C2/ 3%H2Mixed gas
Annealed 20-30 minutes in atmosphere, complete the preparation process to the La based dielectric material high-K metal gate structures based on Si substrates.
The invention has the advantages that：
1. the present invention uses La bases high-k gate dielectric material as gate oxide, due to the dielectric of La base high-k gate dielectric materials
Constant compares HfO2It is higher by nearly 1 times, thus the dielectric constant of overall gate oxide can be increased, 1nm is less than in equivalent oxide thickness
When can guarantee that gate oxide has larger physical thickness, reduce by gate leakage current caused by direct tunnelling and device
Power consumption；
2., using TiAlN thin film as barrier layer, due to TiN, chemical stability is good at high temperature for the present invention, not with the gold such as Pt
Category reaction, and with good electric conductivity, thus during follow-up Pt Metal depositions and thermal anneal process can be stopped Pt metal to grid
The diffusion of oxide layer.
3. the present invention uses metal Ti films as oxygen element adsorption layer, because metal Ti is obvious with oxygen element binding ability
More than Si, thus can during thermal anneal process by long-range suction-operated by the oxygen element of gate oxide and wafer Si interfaces
Metal Ti thin layers are adsorbed to, so as to reduce the oxygen element content of gate oxide and wafer Si interfaces, interface thickness is thinned
Degree.
Brief description of the drawings
Fig. 1 is traditional high-K metal gate structure schematic diagram；
Fig. 2 is La based dielectric material high-K metal gate structure schematic diagram of the present invention based on Si substrates；
Fig. 3 is the general flow chart that the present invention prepares the La based dielectric material high-K metal gate structures based on Si substrates；
Fig. 4 for the present invention in prepare La2O3The sub-process figure of film；
Fig. 5 for the present invention in prepare Al2O3The sub-process figure of film；
Fig. 6 for the present invention in prepare LaAlO3The sub-process figure of film；
Fig. 7 is to deposit a La for circulation2O3Burst length schematic diagram；
Fig. 8 is to deposit an Al for circulation2O3Burst length schematic diagram.
Specific embodiment
Reference picture 1, traditional high-K metal gate structure includes from bottom to top on a si substrate：HfO2Gate dielectric membrane 1 and gold
Category Pt gate electrodes 2, wherein：HfO2The thickness of high-k gate dielectric films 1 is 4-10nm；The thickness of Pt metal gate electrode 2 is 100-
150nm。
Reference picture 2, La based dielectric material high-K metal gate structure of the present invention based on Si substrates, on a si substrate from lower
On include：La bases high-k gate dielectric films 1, TiN barrier layers 2, Ti oxygen elements adsorption layer 3 and heavy metal Pt gate electrodes 4.Wherein,
The thickness of La bases high-k gate dielectric films 1 is 4-10nm, and the material of the La base high-k gate dielectric films includes La2O3Or LaAlO3Or
HfLaOxOr LaScO3Or LaLuO3, its Main Function is the dielectric constant for improving gate dielectric material；The thickness of TiN barrier layers 2 is 2-
3nm, its Main Function is to stop the diffusion of Pt metal in follow-up Pt Metal depositions and thermal anneal process to gate oxide；Ti oxygen unit
The thickness of plain adsorption layer 3 is 4-6nm, and its Main Function is by gate oxide during thermal anneal process by long-range suction-operated
Metal Ti thin layers are adsorbed to the oxygen element of wafer Si interfaces, so as to reduce the oxygen element of gate oxide and wafer Si interfaces
Content is with thinning interfacial layer thickness；The thickness of heavy metal Pt gate electrodes 4 is 100-150nm, and its Main Function is as conductive gate electricity
Pole.
Reference picture 3, three kinds of implementations of La based dielectric material high-K metal gate structure of the present invention based on Si substrates given below
Example.
Embodiment 1：Prepare La2O3The high-K metal gate structure of high-k gate dielectric material.
Step 1, cleans Silicon Wafer.
1a. ratios are 5:1:1 NH4OH, H2O2And H2O is equipped with SC-1 solution, is 1 with ratio:50 HF and H2O is equipped with
HF solution；
1b. is once cleaned 10 minutes during Si wafers to be placed on the SC-1 solution that temperature is 75 DEG C, and is rushed with deionized water
Wash 2 minutes, to remove the particle of organic pollution or attachment on Si pieces；
1c. will in the Si wafers after the cleaning of SC-1 solution are placed in HF solution secondary cleaning 60 seconds, and use deionized water
Middle flushing, to remove the natural oxidizing layer SiO of Si crystal column surfaces2；
1d. puts in deionized water with being cleaned by ultrasonic 5 minutes, to remove the suction on surface the Si wafers after secondary cleaning
Attached particle, then with deionized water rinsing 2 minutes, and dried up with 99.999% high pure nitrogen.
Step 2, atomic layer deposition apparatus reaction chamber is put into by the Si wafers after cleaning, is being blown using atomic layer deposition method
La is deposited on Si wafers after dry2O3Film.
Reference picture 4, this step is implemented as follows：
Si wafers after cleaning are put into atomic layer deposition apparatus reaction chamber by 2a. under ultra-clean indoor environment, then by atom
The pressure of layer deposition apparatus cavity is evacuated to 9hPa, and temperature is heated to 290 DEG C, purging 99.999% High Purity Nitrogen air-flow used
Amount is set as 100sccm, setting deposit La2O3Cycle-index m；
2b. deposits a triisopropyl cyclopentadiene lanthanum pulse on Si wafers, and deposition time is 0.1s, in such as Fig. 7
Shown in t1, reaction generation La-O-La-iPr CP*And isopropylcyclopentadiene；
Fail to participate in after the triisopropyl cyclopentadiene lanthanum that 2c. is deposited to failing on Si wafers and deposit saturation
Isopropylcyclopentadiene generated in the triisopropyl cyclopentadiene lanthanum and deposition process of deposit is purged, flushing times
It is 4.0s, as shown in t2 in Fig. 7；
2d. deposits an ozone purge, deposition time again on the Si wafers after triisopropyl cyclopentadiene lanthanum is deposited
It is 0.3s, as shown in t3 in Fig. 7, makes La-O-La-iPr CP*There is exchange reaction with the oxygen atom in ozone, generate La-OH*,
Organic by-products and O2；
2e. with isopropylcyclopentadiene lanthanum to reacting and reaction reaches the ozone for failing to participate in reaction after saturation not successfully
And organic by-products and O2Purged, flushing times are 10s, as shown in t4 in Fig. 7；
2f. repeat step 2b- steps 2e m times, until La2O3The thickness of film reaches 6nm.
Step 3, will complete La2O3The Si wafers of thin-film deposition are placed in the vacuum environment that temperature is 500 DEG C and anneal.
3a. will complete La2O3The Si wafers of thin-film deposition are put into rapid thermal annealing furnace cavity, are passed through 99.999% high-purity
Air in nitrogen 5min purging rapid thermal annealing furnace cavities；
The pressure of rapid thermal annealing furnace cavity is evacuated to 1hPa by 3b.；
Rapid thermal anneler cavity temperature is heated to 500 DEG C by 3c. with the heating rate of 20 DEG C/s, and is kept in this temperature
60s；
3d. to 99.999% high pure nitrogen is continually fed into rapid thermal annealing furnace cavity, until cavity temperature is down to 100
℃。
Step 4, using e-beam evaporation in La2O3The thick TiAlN thin films of 2nm are deposited on film.
Step 5, the thick metal Ti films of 4nm are deposited using magnetically controlled sputter method in TiAlN thin film.
Step 6, the thick Pt metal films of 100nm are deposited using magnetically controlled sputter method on metal Ti films.
Step 7, by photoetching process, makes the gate electrode of high-K metal gate structure.
7a. rotates resist coating on the Pt metal film of deposit, and photoresist is dried；
7b. is exposed and develops to the photoresist on Pt metal film, forms gate electrode pattern；
7c. dries to solidify photoresist to exposing and after the photoresist that develops is carried out；
7d. uses CF4Plasma is performed etching to the Si wafers after solidification photoresist, etching depth to La2O3K grid high
Dielectric film, forms gate electrode；
Be sequentially placed into Si wafers after plasma etching in acetone soln, ethanol, deionized water and be cleaned by ultrasonic by 7e.
5min, washes remaining photoresist on Pt metal film off, then dried up with 99.999% high pure nitrogen.
Step 8, in 400 DEG C of 97%N2/ 3%H2Annealed in mixed gas atmosphere.
Be put into the Si wafers for completing photoetching process in annealing furnace cavity by 8a., is continually fed into 97%N2/ 3%H2Gaseous mixture
Body；
Annealing furnace cavity temperature is heated to 400 DEG C by 8b. with the heating rate of 10 DEG C/s, and keeps 20min in this temperature；
8c. in fast annealing furnace cavity to being continually fed into 99.999% high pure nitrogen, until cavity temperature is down to 100 DEG C, it is complete
Prepared into high-K metal gate structure.
Embodiment 2, prepares La2O3/Al2O3Laminated construction as k gate oxides high high-K metal gate structure.
Step one, cleans Silicon Wafer.
This step it is 1 identical the step of implementing with embodiment 1.
Step 2, atomic layer deposition apparatus reaction chamber is put into by the Si wafers after cleaning, is existed using atomic layer deposition method
La is deposited on Si wafers after drying2O3/Al2O3Laminate film.
Reference picture 4 and Fig. 5, this step are implemented as follows：
2.1) under ultra-clean indoor environment, the Si wafers after pretreated cleaning are put into atomic layer deposition apparatus reaction
Chamber, then chamber pressure is evacuated to 15hPa, temperature is heated to 300 DEG C, set 99.999% high pure nitrogen used by purging
Flow is 120sccm, setting deposit La2O3Cycle-index m and deposit Al2O3Cycle-index n；
2.2) a triisopropyl cyclopentadiene lanthanum pulse is deposited on Si wafers, deposition time is 0.1s, in such as Fig. 7
Shown in t1, reaction generation La-O-La-iPr CP*And isopropylcyclopentadiene；
2.3) ginseng is failed after the triisopropyl cyclopentadiene lanthanum and deposit saturation that are deposited on Si wafers to failing
The byproduct of reaction generated in triisopropyl cyclopentadiene lanthanum and deposition process with deposit is purged, and flushing times are
4.0s, as shown in t2 in Fig. 7；
2.4) on the Si wafers after triisopropyl cyclopentadiene lanthanum is deposited, then an ozone purge is deposited, during deposit
Between be 0.3s, as shown in t3 in Fig. 7, make La-O-La-iPr CP*There is exchange reaction with the oxygen atom in ozone, generate La-
OH*, organic by-products and O2；
2.5) to being reacted with triisopropyl cyclopentadiene lanthanum not successfully and reaction reaches and fails after saturation to participate in reaction
Ozone and organic by-products and O2Purged, flushing times are 10s, as shown in t4 in Fig. 7；
2.6) repeat step 2.2)-step 2.5) m times, until La2O3The thickness of film reaches 4nm；
2.7) in La2O3A trimethyl aluminium pulse is deposited on film, Al-O-Al-CH is generated3And CH *4, deposition time is
0.1s, as shown in t1 in Fig. 8；
2.8) to failing in La2O3Fail to participate in the three of deposit after the trimethyl aluminium and deposit saturation that are deposited on film
CH generated in aluminium methyl and deposition process4Purged, flushing times are 3.0s, as shown in t2 in Fig. 8；
2.9) La after trimethyl aluminium is deposited2O3An ozone purge is deposited on film again, deposition time is 0.5s, such as
In Fig. 8 shown in t3, make Al-O-Al-CH3* there is exchange reaction with the oxygen atom in ozone, generate Al-OH*, CH2O and O2Three kinds
Gas；
2.10) to being reacted with trimethyl aluminium not successfully and reaction reaches the ozone and CH that fail to participate in reaction after saturation2O
And O2Purged, flushing times are 4.0s, as shown in t4 in Fig. 8；
2.11) repeat step 2.7)-step 2.10) n times, until Al2O3The thickness of film reaches 2nm.
Step 3, will complete La2O3/Al2O3The Si wafers of laminate film deposit are placed in the vacuum environment that temperature is 650 DEG C
Middle annealing.
3.1) La will be completed2O3/Al2O3The Si wafers of laminate film deposit are put into rapid thermal annealing furnace cavity, are passed through
99.999% high pure nitrogen 5min, to purge the air in rapid thermal annealing furnace cavity；
3.2) pressure of rapid thermal annealing furnace cavity is evacuated to 1hPa；
3.3) rapid thermal anneler cavity temperature is heated to 650 DEG C with the heating rate of 15 DEG C/s, and this temperature is protected
Hold 75s；
3.4) to 99.999% high pure nitrogen is continually fed into rapid thermal annealing furnace cavity, until cavity temperature is down to 100
℃。
Step 4, using e-beam evaporation in La2O3/Al2O3The thick TiAlN thin films of 2.5nm are deposited on laminate film.
Step 5, the thick metal Ti films of 5nm are deposited using magnetically controlled sputter method in TiAlN thin film.
Step 6, the thick Pt metal films of 120nm are deposited using magnetically controlled sputter method on metal Ti films.
Step 7, by photoetching process, makes the gate electrode of HKMG structures.
7.1) resist coating is rotated on the Pt metal film of deposit, and photoresist is dried；
7.2) photoresist on Pt metal film is exposed and is developed, form gate electrode pattern；
7.3) dry to solidify photoresist to exposing and after the photoresist that develops is carried out；
7.4) CF is used4Plasma is performed etching to the Si wafers after solidification photoresist, etching depth to La2O3/Al2O3
Laminate film, forms gate electrode；
7.5) the Si wafers after plasma etching are sequentially placed into acetone soln, ethanol, deionized water and are cleaned by ultrasonic
5min, washes remaining photoresist on Pt metal film off, then dried up with 99.999% high pure nitrogen.
Step 8, in 450 DEG C of 97%N2/ 3%H2Annealed in mixed gas atmosphere.
8.1) the Si wafers for completing photoetching process are put into annealing furnace cavity, and are continually fed into 97%N2/ 3%H2Mixing
Gas；
8.2) annealing furnace cavity temperature is heated to 450 DEG C with the heating rate of 5 DEG C/s, and this temperature is kept into 25min；
8.3) to being continually fed into 99.999% high pure nitrogen in fast annealing furnace cavity, until cavity temperature is down to 100 DEG C, it is complete
Prepared into high-K metal gate structure.
Embodiment 3, prepares LaAlO3The high-K metal gate structure of k gate oxides material high.
Step A, cleans Silicon Wafer.
This step it is 1 identical the step of implementing with embodiment 1.
Step B, atomic layer deposition apparatus reaction chamber is put into by the Si wafers after cleaning, is being blown using atomic layer deposition method
LaAlO is deposited on Si wafers after dry3Film.
Reference picture 6, this step is implemented as follows：
B1. under ultra-clean indoor environment, the Si wafers after pretreated cleaning are put into atomic layer deposition apparatus reaction
Chamber, then chamber pressure is evacuated to 20hPa, temperature is heated to 310 DEG C, set 99.999% high pure nitrogen used by purging
Flow is 150sccm, setting deposit La2O3Cycle-index m=1, deposit Al2O3Cycle-index n=1；
B2. a triisopropyl cyclopentadiene lanthanum pulse is deposited on Si wafers, deposition time is 0.1s, in such as Fig. 7
Shown in t1, reaction generation La-O-La-iPr CP*And isopropylcyclopentadiene；
B3. fail to participate in after the triisopropyl cyclopentadiene lanthanum and deposit saturation that are deposited on Si wafers to failing
Byproduct of reaction generated in the triisopropyl cyclopentadiene lanthanum and deposition process of deposit is purged, and flushing times are
4.0s, as shown in t2 in Fig. 7；
B4. on the Si wafers after triisopropyl cyclopentadiene lanthanum is deposited, then an ozone purge, deposition time are deposited
It is 0.3s, as shown in t3 in Fig. 7, makes La-O-La-iPr CP*There is exchange reaction with the oxygen atom in ozone, generate La-OH*,
Organic by-products and O2；
B5. to being reacted with triisopropyl cyclopentadiene lanthanum not successfully and reaction reaches and fails after saturation to participate in the smelly of reaction
Oxygen and organic by-products and O2Purged, flushing times are 10s, as shown in t4 in Fig. 7；
B6. a trimethyl aluminium pulse is deposited on the Si wafers for completing step B5, Al-O-Al-CH is generated3And CH *4, form sediment
The product time is 0.1s, as shown in t1 in Fig. 8；
B7. fail to participate in the trimethyl of deposit after the trimethyl aluminium and deposit saturation that are deposited on Si wafers to failing
CH generated in aluminium and deposition process4Purged, flushing times are 3.0s, as shown in t2 in Fig. 8；
B8. an ozone purge is deposited again on the Si wafers after trimethyl aluminium is deposited, deposition time is 0.5s, such as Fig. 8
Shown in middle t3, make Al-O-Al-CH3* there is exchange reaction with the oxygen atom in ozone, generate Al-OH*, CH2O and O2；
B9. to being reacted with trimethyl aluminium not successfully and reaction reaches the ozone and CH that fail to participate in reaction after saturation2O and
O2Purged, flushing times are 4.0s, as shown in t4 in Fig. 8；
B10. repeat step B2 to B9, until LaAlO3The thickness of film reaches 8nm.
Step C, will complete LaAlO3The Si wafers of thin-film deposition are placed in the vacuum environment that temperature is 700 DEG C and anneal.
C1. LaAlO will be completed3The Si wafers of thin-film deposition are put into rapid thermal annealing furnace cavity, are passed through 99.999% high
Air in pure nitrogen gas 5min purging rapid thermal annealing furnace cavities；
C2. the pressure of rapid thermal annealing furnace cavity is evacuated to 1hPa；
C3. rapid thermal anneler cavity temperature is heated to 700 DEG C with 15 DEG C/s of heating rate, and this temperature is kept
90s；
C4. to 99.999% high pure nitrogen is continually fed into rapid thermal annealing furnace cavity, until cavity temperature is down to 100
℃。
Step D, using e-beam evaporation in LaAlO3The thick TiAlN thin films of 3nm are deposited on film.
Step E, the thick metal Ti films of 6nm are deposited using magnetically controlled sputter method in TiAlN thin film.
Step F, the thick Pt metal films of 150nm are deposited using magnetically controlled sputter method on metal Ti films.
Step G, by photoetching process, makes the gate electrode of high-K metal gate structure.
G1. resist coating is rotated on the Pt metal film of deposit, and photoresist is dried；
G2. the photoresist on Pt metal film is exposed and is developed, form gate electrode pattern；
G3. dry to solidify photoresist to exposing and after the photoresist that develops is carried out；
G4. CF is used4Plasma is performed etching to the Si wafers after solidification photoresist, etching depth to LaAlO3Film,
Form gate electrode；
G5. the Si wafers after plasma etching are sequentially placed into acetone soln, ethanol, deionized water and are cleaned by ultrasonic
5min, washes remaining photoresist on Pt metal film off, then dried up with 99.999% high pure nitrogen
Step H, in 500 DEG C of 97%N2/ 3%H2Annealed in mixed gas atmosphere.
H1. the Si wafers for completing photoetching process are put into annealing furnace cavity, and are continually fed into 97%N2/ 3%H2Mixing
Gas；
H2. annealing furnace cavity temperature is heated to 500 DEG C with the heating rate of 5 DEG C/s, and this temperature is kept into 30min；
H3. to being continually fed into 99.999% high pure nitrogen in fast annealing furnace cavity, until cavity temperature is down to 100 DEG C, it is complete
Prepared into high-K metal gate structure.
Above description is only three specific embodiments of the invention, does not constitute any limitation of the invention.Obviously for
For one of skill in the art, after present invention and principle is understood, all may be without departing substantially from principle of the invention, structure
In the case of, various amendments and the change in form and details are carried out, but these are based on the amendment of invention thought and change still
Within claims of the invention.
Claims (8)
1. a kind of La based dielectric materials high-K metal gate structure and preparation method based on Si substrates, on a si substrate from bottom to top
Including La bases high-k gate dielectric films (1) and heavy metal Pt gate electrodes (4), it is characterised in that：La bases high-k gate dielectric films (1) with
TiN barrier layers (2) and Ti oxygen elements adsorption layer (3) are had additional between heavy metal Pt gate electrodes (4)；The thickness on the TiN barrier layers (2)
It is 2-3nm to spend, and on La bases high-k gate dielectric films (1), is situated between to La bases k grid high to barrier metal Ti and heavy metal Pt
Matter film (1) spreads；Ti oxygen elements adsorption layer (3) thickness is 4-6nm, on TiN barrier layers (2), with thermal annealing
The oxygen element of La bases high-k gate dielectric films (1) and wafer Si interfaces is adsorbed in technical process.
2. the structure according to claims 1, it is characterised in that La base high-k gate dielectric films, using La2O3Or LaAlO3
Or La2O3/Al2O3Laminated construction or HfLaOxOr LaScO3Or LaLuO3Material.
3. a kind of preparation method of the La based dielectric material high-K metal gate structures based on Si substrates, comprises the following steps：
(1) Si wafers are cleaned；
(2) it is the La of 4-10nm to use atomic layer deposition method deposition thickness on Si wafers2O3Or LaAlO3Or HfLaOxOr
LaScO3Or LaLuO3La base high-k gate dielectric films；
(3) substrate for depositing La base high-k gate dielectric films is carried out into the fast speed heats of 60-90s under 500-700 DEG C of vacuum to move back
Fire；
(4) after thermal annealing, the thick TiAlN thin films of 2-3nm are deposited on La base high-k gate dielectric films using e-beam evaporation；
(5) the thick metal Ti films of 4-6nm are deposited in TiAlN thin film using magnetically controlled sputter method；
(6) the thick Pt metal films of 100-150nm are deposited on metal Ti films using magnetically controlled sputter method；
(7) sample with Pt metal film is processed using photoetching process, the Pt metal film deposited on sample is formed grid electricity
Pole；
(8) 97%N of the sample of gate electrode at 300-500 DEG C will be formed2/ 3%H2Annealed 20-30 minutes in mixed gas atmosphere,
Complete the preparation process of the La based dielectric material high-K metal gate structures of Si substrates.
4. method according to claim 3, wherein cleans in step (1) to Si wafers, carries out as follows：
(1.1) it is 5 with ratio:1:1 NH4OH, H2O2And H2O is equipped with SC-1 solution, is 1 with ratio:50 HF and H2O is equipped with HF
Solution；
(1.2) Si wafers are placed in the SC-1 solution that temperature is 75 DEG C and are once cleaned 10 minutes, and with deionized water rinsing 2
Minute, to remove the particle of organic pollution or attachment on Si pieces；
(1.3) secondary cleaning 60 seconds in the Si wafers after the cleaning of SC-1 solution being placed in into HF solution, and with deionized water
Rinse, to remove the natural oxidizing layer SiO of Si crystal column surfaces2；
(1.4) the Si wafers after secondary cleaning are put in deionized water with being cleaned by ultrasonic 5 minutes, to remove the absorption on surface
Particle, then with deionized water rinsing 2 minutes, and dried up with high pure nitrogen.
5. preparation method according to claim 3, it is characterised in that existed with atomic layer deposition method in the step (2)
La base high-k gate dielectric films are deposited on Si wafers after cleaning, is carried out as follows：
(2.1) under ultra-clean indoor environment, the Si wafers after cleaning are put into atomic layer deposition apparatus reaction chamber, then by cavity pressure
9-20hPa is evacuated to by force, temperature is heated to 290-310 DEG C, the nitrogen flow set used by purging is 150sccm, according to
Material type and thickness setting the deposit La of the La base high-k gate dielectric films of growth2O3Cycle-index m and deposit Al2O3Follow
Ring frequency n；
(2.2) a triisopropyl cyclopentadiene lanthanum pulse is deposited on Si wafers, deposition time is 0.1s, reaction generation
La-O-La-iPr CP*And isopropylcyclopentadiene；
(2.3) fail to participate in forming sediment after the triisopropyl cyclopentadiene lanthanum and deposit saturation that are deposited on Si wafers to failing
Byproduct of reaction generated in long-pending triisopropyl cyclopentadiene lanthanum and deposition process is purged, and flushing times are
4.0s；
(2.4) on the Si wafers after triisopropyl cyclopentadiene lanthanum is deposited, then an ozone purge is deposited, deposition time is
0.3s, makes La-O-La-iPr CP*There is exchange reaction with the oxygen atom in ozone, generate La-OH*, organic by-products and O2；
(2.5) to being reacted with triisopropyl cyclopentadiene lanthanum not successfully and reaction reaches the ozone for failing to participate in reaction after saturation
And organic by-products and O2Purged, flushing times are 10s；
(2.6) repeat step (2.2) to (2.5) m times；
(2.7) a trimethyl aluminium pulse is deposited on the Si wafers for completing step B5, Al-O-Al-CH is generated3And CH *4, deposit
Time is 0.1s；
(2.8) fail to participate in the trimethyl aluminium of deposit after the trimethyl aluminium and deposit saturation that are deposited on Si wafers to failing
And the CH generated in deposition process4Purged, flushing times are 3.0s；
(2.9) ozone purge is deposited again on the Si wafers after trimethyl aluminium is deposited, deposition time is 0.5s, makes Al-O-
Al-CH3* there is exchange reaction with the oxygen atom in ozone, generate Al-OH*, CH2O and O2；
(2.10) to being reacted with trimethyl aluminium not successfully and reaction reaches the ozone and CH that fail to participate in reaction after saturation2O and O2
Purged, flushing times are 4.0s；
(2.11) repeat step (2.7) to (2.10) n times；
(2.11) repeat step (2.6) and (2.11), until La base high-k gate dielectric films reach set thickness.
6. preparation method according to claim 3, it is characterised in that the annealing in the step (3), enters as follows
OK：
(3.1) the Si wafers that will complete the deposit of La bases high-k gate dielectric films are put into rapid thermal annealing furnace cavity, are passed through nitrogen and are blown
The air in rapid thermal annealing furnace cavity is swept, purge time is 5min；
(3.2) pressure of rapid thermal annealing furnace cavity is evacuated to 1hPa；
(3.3) temperature of rapid thermal annealing furnace cavity is heated to 500-700 DEG C with the heating rate of 15-20 DEG C/s, and herein
Temperature keeps 60-90s；
(3.4) to nitrogen is continually fed into rapid thermal annealing furnace cavity, until cavity temperature is down to 100 DEG C.
7. preparation method according to claim 3, it is characterised in that the photoetching in the step (7), enters as follows
OK：
(7.1) resist coating is rotated on the Pt metal film of deposit, and photoresist is dried；
(7.2) photoresist on Pt metal film is exposed and is developed, form gate electrode pattern；
(7.3) dry to solidify photoresist to exposing and after the photoresist that develops is carried out；
(7.4) CF is used4Plasma is performed etching to the Si wafers after solidification photoresist, etching depth to La base high-k gate dielectrics
Film, forms gate electrode；
(7.5) the Si wafers after plasma etching are sequentially placed into acetone soln, ethanol, deionized water and are cleaned by ultrasonic
5min, washes remaining photoresist on Pt metal film off, then dried up with high pure nitrogen.
8. preparation method according to claim 3, it is characterised in that in the step (1), step (2) and step (7)
Purging cooling in purging and step (3) and step (8), its process conditions are as follows：
Gas used is 99.999% high pure nitrogen；
Nitrogen flow is set as 100-150sccm.
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| US6326670B1 (en) * | 1999-03-11 | 2001-12-04 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
| CN102299061A (en) * | 2010-06-22 | 2011-12-28 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device |
| CN105336599A (en) * | 2014-07-23 | 2016-02-17 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN105470306A (en) * | 2015-11-10 | 2016-04-06 | 西安电子科技大学 | LaAlO3/SrTiO3 heterojunction field effect transistor based on La-based gate and manufacturing method |
-
2016
- 2016-11-16 CN CN201611024999.9A patent/CN106711051A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6326670B1 (en) * | 1999-03-11 | 2001-12-04 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
| CN102299061A (en) * | 2010-06-22 | 2011-12-28 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device |
| CN105336599A (en) * | 2014-07-23 | 2016-02-17 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN105470306A (en) * | 2015-11-10 | 2016-04-06 | 西安电子科技大学 | LaAlO3/SrTiO3 heterojunction field effect transistor based on La-based gate and manufacturing method |
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