CN106685584B - HDLC transceiver controller based on FPGA - Google Patents
HDLC transceiver controller based on FPGA Download PDFInfo
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- CN106685584B CN106685584B CN201510757573.3A CN201510757573A CN106685584B CN 106685584 B CN106685584 B CN 106685584B CN 201510757573 A CN201510757573 A CN 201510757573A CN 106685584 B CN106685584 B CN 106685584B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0006—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format
- H04L1/0007—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format by modifying the frame length
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
- H04L1/0063—Single parity check
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
- H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
- H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
- H04L69/324—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
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Abstract
The invention provides an HDLC transceiver controller based on an FPGA. The HDLC transceiver controller includes: the HDLC comprises a processor interface module, an HDLC transmitting module and an HDLC receiving module. The processor interface module is used for providing an interface for the processor, exchanging data with the processor and controlling the HDLC sending module and the HDLC receiving module. The HDLC transmitting module is used for receiving data written by the processor and encoding the data into HDLC frames, transmitting the encoded HDLC frames to a device in communication with the processor, the HDLC receiving module is used for receiving and decoding the HDLC frames transmitted by the device in communication with the processor, storing the decoded data, and transmitting an interrupt signal to the processor to enable the processor to read the decoded data. The HDLC receiving and transmitting controller based on the FPGA provided by the invention can be compatible with processors with different time sequences to carry out HDLC frame receiving and transmitting control, does not occupy the resources of the processors, and has good universality.
Description
Technical Field
The invention relates to the technical field of communication and the field of rail transit, in particular to an HDLC transceiver controller based on an FPGA.
Background
The High-level data link control (HDLC) is a synchronous data transmission and bit-oriented data link layer protocol, has the characteristics of powerful error detection function, high efficiency and synchronous transmission, and is one of the most widely applied protocols in the communication field. The HDLC transceiver controller completes the encoding and decoding functions of HDLC frames and is responsible for the transmission and reception of HDLC protocol frame data.
The existing HDLC transceiver controller is mainly implemented by using an HDLC dedicated chip and software programming. The HDLC special chip has a lot of resources not to be used, which causes resource waste, and the complicated layout and wiring of the HDLC special chip has to be considered when designing a circuit, in addition, the upgrade speed of the HDLC special chip is too high, and the universality is poor. The software programming implementation mode is that HDLC receiving and transmitting control is realized through an application program of a processor, but the method can occupy the resources of the processor so as to reduce the execution speed of the processor, and the time delay and the synchronism of signals are not easy to predict, so that the program and the debugging are required to be modified again for the processors with different time sequences.
Disclosure of Invention
The HDLC transceiver controller based on the FPGA provided by the invention can be compatible with processors with different time sequences to carry out HDLC frame transceiver control, has the advantages of software programming and HDLC special chips, does not occupy the resources of the processors, and has good universality.
The HDLC transceiver controller provided by the invention realizes the transceiving control function of HDLC on an FPGA, and comprises:
the HDLC comprises a processor interface module, an HDLC transmitting module and an HDLC receiving module;
the processor interface module is used for: providing an interface for a processor, carrying out data exchange with the processor, controlling the HDLC transmitting module and the HDLC receiving module, returning to an idle state by the processor interface module after the processor executes a read/write operation if the processing period of the processor is smaller than the processing period of the HDLC receiving/transmitting controller, and returning to the idle state until the read/write operation is finished if the processing period of the processor is greater than or equal to the processing period of the HDLC receiving/transmitting controller, wherein the processor interface module enters a write waiting state when the processor executes a read/write operation;
the HDLC sending module is used for: receiving the data written by the processor and encoding the data into HDLC frames, and transmitting the encoded HDLC frames to a device in communication with the processor;
the HDLC receiving module is used for: and receiving and decoding HDLC frames sent by a device in communication with the processor, storing decoded data, and sending an interrupt signal to the processor to enable the processor to read the decoded data.
Further, the HDLC transmitting module includes:
the HDLC sending state register is used for marking the state of the HDLC sending module;
the first data buffer is used for receiving and storing the data written by the processor;
a check code generating unit, configured to generate a cyclic redundancy check CRC-16 check code from the data stored in the first data buffer;
the clock synchronization unit is used for performing clock synchronization on the check code;
the data insertion 0 unit is used for carrying out parallel/serial conversion and insertion 0 processing on the check code after clock synchronization;
the flag bit inserting unit is used for inserting frame head and frame tail into the data subjected to parallel/serial conversion and 0 insertion operation to obtain an encoded HDLC frame;
and the transmitting unit is used for transmitting the encoded HDLC frame to a device in communication with the processor.
Further, the HDLC receiving module includes:
a receiving unit, configured to receive an HDLC frame sent by a device in communication with the processor;
the frame identification unit is used for carrying out frame identification on the received HDLC frame and removing the head and the tail of the frame;
the zero code removing unit is used for carrying out zero code removing processing and serial/parallel conversion on HDLC frame data after frame identification;
the clock synchronization unit is used for performing clock synchronization on the data subjected to zero code removal processing and serial/parallel conversion;
the checking unit is used for performing CRC check on the data after clock synchronization;
the second data buffer is used for storing the data subjected to CRC check and sending an interrupt signal to the processor when a preset condition is met so that the processor reads the decoded data;
and the HDLC receiving state register is used for identifying the state of the HDLC receiving module.
Further, the processor interface module includes: address lines, data lines, chip select signals, write signals, read signals, and interrupt signals.
The HDLC transceiver controller based on the FPGA provided by the invention can be compatible with processors with different time sequences to carry out HDLC frame transceiver control through special processing of the processor interface module, has the advantages of software programming and HDLC special chips, does not occupy the resources of the processor because the HDLC transceiver controller is realized through the FPGA, can transplant codes on different types of FPGA chips, and is suitable for HDLC frame transceiver control in different scenes, and has good universality.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description of the embodiments or the drawings used in the description of the prior art will be given in brief, it being obvious that the drawings in the description below are some embodiments of the invention and that other drawings can be obtained from them without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a HDLC transceiver controller based on an FPGA according to an embodiment of the present invention;
FIG. 2 is a schematic diagram showing the working state of a processor interface module in a first embodiment of an HDLC transceiver controller based on an FPGA;
FIG. 3 is a schematic diagram of a second embodiment of an HDLC transceiver controller based on an FPGA;
FIG. 4 is a schematic diagram of a hardware system according to the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention provides an HDLC (high-level data link control) transceiver controller based on an FPGA (field programmable gate array), which realizes an HDLC frame transceiver control function through the FPGA. The method can be well adapted to processors with different working time sequences, can be directly used without modifying FPGA codes, is used as an independent hardware module, does not occupy processor resources, is basically unchanged in hardware circuit design, can be used for transplanting codes to FPGA chips with different models, can be suitable for HDLC frame receiving and dispatching control in different scenes, and has the advantages of software programming and HDLC special chips. The following detailed description refers to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a first embodiment of an HDLC transceiver controller based on an FPGA according to the present invention, as shown in fig. 1, the HDLC transceiver controller of this embodiment may include: the device comprises a processor interface module 10, an HDLC sending module 11 and an HDLC receiving module 12, wherein the processor interface module 10 is used for: providing an interface for a processor, performing data exchange with the processor, and controlling the HDLC transmitting module 11 and the HDLC receiving module 12, fig. 2 is a schematic diagram of an operating state of the processor interface module in a first embodiment of the HDLC transceiver controller based on FPGA according to the present invention, and in fig. 2, taking a processing period of the HDLC transceiver controller as an example, as shown in fig. 2, if the processing period of the processor is smaller than that of the HDLC transceiver controller, the processor interface module 10 returns to an idle state after the processor performs a read/write operation once; if the processing period of the processor is greater than or equal to the processing period of the HDLC transceiver controller, the processor interface module 10 enters a write waiting state when the processor performs a read/write operation once, and returns to an idle state until the read/write operation ends, so that the unique and accurate reading/writing of the HDLC transceiver controller by the processor is ensured. Therefore, the HDLC receiving and transmitting controller can work normally for processors with different time sequences, so that the HDLC receiving and transmitting controller can be compatible with the processors with different time sequences to carry out HDLC frame receiving and transmitting control.
The HDLC transmission module 11 is configured to: and receiving the data written by the processor and encoding the data into HDLC frames, and transmitting the encoded HDLC frames to a device in communication with the processor.
Specifically, when the processor needs to send data to the HDLC transceiver controller, the HDLC transmitting module 11 is read to determine the state of the HDLC transmitting module, determine whether it is idle, and when the HDLC transmitting module 11 is determined to be idle, the processor may send data.
The HDLC receiving module 12 is configured to: and receiving and decoding the HDLC frame transmitted by the device in communication with the processor, storing the decoded data, and transmitting an interrupt signal to the processor to enable the processor to read the decoded data.
Specifically, when the HDLC receiving module has data for the processor to read, an interrupt signal is sent to the processor, and then the processor determines how much data can be read by the HDLC receiving module by reading the HDLC receiving module 12 to determine the state of the HDLC receiving module, and finally reads the data.
The HDLC transceiver controller based on the FPGA provided by the embodiment can be compatible with processors with different time sequences to carry out HDLC frame transceiver control through special processing of the processor interface module, and has the advantages of software programming and HDLC special chips.
Fig. 3 is a schematic structural diagram of a second embodiment of an HDLC transceiver controller based on an FPGA according to the present invention, as shown in fig. 3, in this embodiment, based on the embodiment shown in fig. 1, the HDLC transmitting module 11 may specifically include: the HDLC transmission status register 110 is used to identify the status of the HDLC transmission module. The first data buffer 111 is configured to receive and store data written by the processor. A check code generating unit 112 for generating a cyclic redundancy check CRC-16 check code from the data stored in the first data buffer. The clock synchronization unit 113 is configured to perform clock synchronization on the check code. And the data insertion 0 unit 114 is used for performing parallel/serial conversion and insertion 0 processing on the check code after clock synchronization. The flag bit inserting unit 115 is configured to insert the header and the tail of the frame into the data after performing the parallel/serial conversion and the 0 insertion operation, so as to obtain the encoded HDLC frame. And a transmitting unit 116 for transmitting the encoded HDLC frames to a device in communication with the processor.
The HDLC receiving module 12 may include: and a receiving unit 120 for receiving the HDLC frames transmitted by the device in communication with the processor. The frame identification unit 121 is configured to perform frame identification on the received HDLC frame. The zero code removal unit 122 is configured to perform zero code removal processing and serial/parallel conversion on the HDLC frame after frame identification. And a clock synchronization unit 123 for performing clock synchronization on the data after the zero code removal processing and serial/parallel conversion. And a checking unit 124, configured to perform CRC check on the clock-synchronized data. The second data buffer 125 is configured to store the data after CRC check, and send an interrupt signal to the processor when a preset condition is satisfied. The HDLC receive status register 126 is used to identify the status of the HDLC receive module.
Wherein, in particular, the processor interface module 10 comprises: address lines, data lines, chip select signals, write signals, read signals, and interrupt signals.
The HDLC transceiver controller based on the FPGA provided by the embodiment can be compatible with processors with different time sequences to carry out HDLC frame transceiver control through special processing of the processor interface module, and has the advantages of software programming and HDLC special chips.
The following describes in detail the operation of the HDLC transceiver controller based on FPGA according to the present invention with a specific embodiment.
In this embodiment, an AT91 processor is used as a CPU of the system, a read-write test program of the AT91 processor uses a C language to program, control data transmission and reception, uses a VHDL language to implement an HDLC transceiver controller, and downloads the HDLC transceiver controller to an FPGA chip to implement HDLC frame transceiver control. Fig. 4 is a schematic diagram of the hardware system structure of the present invention, as shown in fig. 4. And connecting the HDLC transmitting module with the HDLC receiving module in the FPGA, enabling the AT91 processor to access the FPGA through a reserved address bus, a reserved data bus and a reserved I/O interface, and testing various functions of the HDLC transceiver controller by an application layer. The test procedure was as follows:
the AT91 processor reads the HDLC sending status register in the HDLC sending module 11 to judge the status of the HDLC sending module 11, when judging that the HDLC sending module 11 is idle, the HDLC receiving and sending controller of the FPGA writes data into the FPGA, the HDLC receiving module 12 decodes the data written into the frame after receiving the frame and stores the decoded data, then sends an interrupt signal to the AT91 processor, and after receiving the interrupt signal, the AT91 processor initiates a reading operation to the HDLC receiving status register to judge the status of the HDLC receiving module 12 and read the data of the HDLC receiving module 12. Finally, the AT91 processor compares the received data with the transmitted data to determine if the data is lost in the form of erroneous frames. After successful debugging, the HDLC transmitting module and the HDLC receiving module are disconnected in the FPGA, so that the HDLC transmitting module and the HDLC receiving module can be normally used.
Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the method embodiments described above may be performed by hardware associated with program instructions. The foregoing program may be stored in a computer-readable storage medium. The program, when executed, performs steps including the method embodiments described above; and the aforementioned storage medium includes: various media that can store program code, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (2)
1. HDLC transceiver controller based on FPGA, its characterized in that, HDLC transceiver controller realizes HDLC's transceiver control function on FPGA, HDLC transceiver controller includes:
the HDLC comprises a processor interface module, an HDLC transmitting module and an HDLC receiving module;
the processor interface module is used for: providing an interface for the processor, carrying out data exchange with the processor, controlling the HDLC transmitting module and the HDLC receiving module, if the processing period of the processor is smaller than that of the HDLC receiving and transmitting controller, returning to an idle state after the processor executes a read/write operation, if the processing period of the processor is greater than or equal to that of the HDLC receiving and transmitting controller, and entering a write waiting state by the processor interface module when the processor executes a read/write operation until the read/write operation is ended;
the HDLC sending module is used for: receiving the data written by the processor and encoding the data into HDLC frames, and transmitting the encoded HDLC frames to a device in communication with the processor;
the HDLC receiving module is used for: receiving and decoding HDLC frames transmitted by a device in communication with the processor, storing the decoded data, and transmitting an interrupt signal to the processor to cause the processor to read the decoded data;
the HDLC transmitting module comprises:
the HDLC sending state register is used for marking the state of the HDLC sending module;
the first data buffer is used for receiving and storing the data written by the processor;
a check code generating unit, configured to generate a cyclic redundancy check CRC-16 check code from the data stored in the first data buffer;
the clock synchronization unit is used for performing clock synchronization on the check code;
the data insertion 0 unit is used for carrying out parallel/serial conversion and insertion 0 processing on the check code after clock synchronization;
the flag bit inserting unit is used for inserting frame head and frame tail into the data subjected to parallel/serial conversion and 0 insertion operation to obtain an encoded HDLC frame;
a transmitting unit for transmitting the encoded HDLC frames to a device in communication with the processor;
the HDLC receiving module includes:
a receiving unit, configured to receive an HDLC frame sent by a device in communication with the processor;
the frame identification unit is used for carrying out frame identification on the received HDLC frame and removing the head and the tail of the frame;
the zero code removing unit is used for carrying out zero code removing processing and serial/parallel conversion on HDLC frame data after frame identification;
the clock synchronization unit is used for performing clock synchronization on the data subjected to zero code removal processing and serial/parallel conversion;
the checking unit is used for performing CRC check on the data after clock synchronization;
the second data buffer is used for storing the data subjected to CRC check and sending an interrupt signal to the processor when a preset condition is met so that the processor reads the decoded data;
and the HDLC receiving state register is used for identifying the state of the HDLC receiving module.
2. The HDLC transceiver controller of claim 1 wherein the processor interface module includes: address lines, data lines, chip select signals, write signals, read signals, and interrupt signals.
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| CN1271129A (en) * | 1999-04-21 | 2000-10-25 | 深圳市中兴通讯股份有限公司 | Synchronous association method and interface circuit between CPU and read/write object with complex time sequence |
| JP2002064584A (en) * | 2000-08-22 | 2002-02-28 | Matsushita Electric Ind Co Ltd | Hdlc transmitter-receiver, hdlc receiver, and hdlc transmitter |
| CN103118005A (en) * | 2013-01-04 | 2013-05-22 | 中国兵器工业集团第二一四研究所苏州研发中心 | High-level data link control (HDLC) protocol controller |
| CN205139625U (en) * | 2015-11-09 | 2016-04-06 | 中车大连电力牵引研发中心有限公司 | HDLC transceiver controller based on FPGA |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1271129A (en) * | 1999-04-21 | 2000-10-25 | 深圳市中兴通讯股份有限公司 | Synchronous association method and interface circuit between CPU and read/write object with complex time sequence |
| JP2002064584A (en) * | 2000-08-22 | 2002-02-28 | Matsushita Electric Ind Co Ltd | Hdlc transmitter-receiver, hdlc receiver, and hdlc transmitter |
| CN103118005A (en) * | 2013-01-04 | 2013-05-22 | 中国兵器工业集团第二一四研究所苏州研发中心 | High-level data link control (HDLC) protocol controller |
| CN205139625U (en) * | 2015-11-09 | 2016-04-06 | 中车大连电力牵引研发中心有限公司 | HDLC transceiver controller based on FPGA |
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