CN106682306A - Rapid FPGA wire arrangement method - Google Patents
Rapid FPGA wire arrangement method Download PDFInfo
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Abstract
The invention discloses a rapid FPGA wire arrangement method. The rapid FPGA wire arrangement method adopts a new wire re-arrangement strategy and a wavefront spreading method and conducts wire arrangement on all wire networks in an iterated mode till a legal wire arrangement result is found or the maximum iteration number is reached. In each time of wire arrangement iteration process, the new wire re-arrangement strategy only re-arrange illegal routes, legal routes are kept, and accordingly the time required for each time of wire arrangement iteration is shortened. When wire arrangement is conducted on each wire network leakage end point, the probability that nodes, farther away from target leakage end points t, on a wire arrangement tree exist on an optimal route connected with t is low. Therefore, during wavefront initialization, wire arrangement tree nodes relatively closer to the t are only used; when the wire arrangement tree is larger, the time for wavefront initialization can be remarkably shortened. On the premise that key route delaying and wire length are optimized, the wire arrangement operating time is obviously shortened.
Description
Technical field
The present invention relates to field of computer technology, more particularly to a kind of quick FPGA wiring methods.
Background technology
In recent years, developing rapidly with integrated circuit technique, field programmable gate array (FPGA), because it has integrated level
High, logical resource is abundant, flexible design and the features such as reconfigurability, in space industry and national defence application widely,
Annual China is needed from a large amount of fpga chips of external import and software kit, and country's FPGA industries are to be developed, restrict state
The factor of interior FPGA industry developments, is mainly a lack of the high-quality FPGA design software of high-performance of independent research.
The design cycle of FPGA, it is main to include design input, behavior integration, Technology Mapping, packing, place and route.Its
In, wiring is a particularly important link, and it directly influences the quality and performance of whole circuit.The wiring of FPGA be exactly
Interconnection resource is reasonably distributed to the gauze in circuit, by being programmed to interconnection resource so as to connect on the basis of layout
The beginning and end of institute's wired network, and ensure that the resource in chip is not reused.First had to before wiring as fpga chip
Set up oriented interconnection resource figure G<V,E>, wherein V is the set of node, metal connecting line, input/output pin and logical block
The resources such as pin；E is the set on side, represents the programmable switch box for being used for connecting these resources.One interconnection resource figure can be with
For representing arbitrary wire structures, so as to wiring unit can be connected up independently of actual fpga chip.Therefore, FPGA cloth
Line is actually the process that feasible path is searched in interconnection resource figure.Wiring needs are solved two problems：(1) in cloth circuit passband
All of gauze.When the interconnection resource of FPGA is less, resource contention is there may be in wiring process so as to cause wiring not
It is legal.Therefore wiring needs reasonable distribution interconnection resource, solves the congestion problems between gauze, all of line in cloth circuit passband
Net.(2) circuit quality is optimized.The timing performance of circuit determines by critical path time delay, it requires the key after wiring
Path delay is as far as possible little.Therefore, wiring problem is also a multi-objective optimization question, and Routing Algorithm needs to solve two phases simultaneously
The subproblem for mutually affecting and vying each other.
What academic circles at present and industrial quarters were usually used to FPGA wiring problems is calculated based on crowded negotiation PathFinder
The wiring method of method.The method iteratively carries out taking out stitches-weigh cloth until without not crowded or reach greatest iteration for institute's wired network
Number of times.In iterative process each time, remove the result of last time cloth line interation and call wavefront expansion to own each gauze
Drain terminal is connected up, wherein allowing multiple gauzes to use identical interconnection resource；After all of gauze completes weight cloth, institute is updated
The cost of some interconnection resources, and to being punished by the interconnection resource that multiple gauzes take simultaneously, so as to connect up next time
The resource is used with less probability during iteration.Wherein, wavefront expansion is the core for being based on crowded negotiation PathFinder algorithms,
Very big amount of calculation is needed simultaneously, and wavefront expansion account for a big chunk time of wiring process.As previously mentioned,
FPGA Routing Algorithms are connected up based on interconnection resource figure to gauze.When the drain terminal point to gauze is connected up, first
The gauze is currently connected up into the upper all of node of tree and is added to wavefront, the section for spending cost minimum is then selected from Priority Queues
Point v goes out team, and wavefront expansion terminates if v is the disconnected node of leakage.Otherwise calculate the cost cost of the neighbor node of v and be added to ripple
Before.Wherein cost includes two parts：Pathcost and expectedcost, two parts realize A* algorithms by weights α.
Pathcost represents the cost from source node to present node, and expectedcost is represented from present node to drain terminal node
It is expected to spend.Wavefront expansion just terminates when finding to the path of the disconnected node of leakage from source node.Because the method is changing every time
Dai Zhong, needs to carry out each gauze all of drain terminal point weight cloth according to strategy is rerouted；In addition, when wavefront is initialized, needing
The upper all nodes of current wiring tree are added to into wavefront, thus this can expend substantial amounts of CPU time.
The content of the invention
The present invention is to overcome above-mentioned traditional PathFinder Routing Algorithms CPU elapsed times in FPGA wiring applications longer
Defect, be improved by counterweight routing strategy and wavefront expansion, and solve the problems, such as cloth line mass and time-consuming mutually restriction,
A kind of quick FPGA wiring methods are proposed, is not reducing reducing the time of FPGA wirings in the case of connecting up outcome quality.
For achieving the above object, the invention provides a kind of quick FPGA wiring methods, it is characterised in that the quick FPGA
Wiring method is comprised the following steps：
The first step, each gauze is made up of source source and multiple drain terminal sink in circuit meshwork list, first for
Every a pair of source of gauze and sink distribute a Bounding Box sink-box, and each sink-box is dimensioned to corresponding
The Bounding Box of source and sink is toward one unit of external expansion；
Second step, initialization wiring, each drain terminal t to each gauze calls wiring unit on interconnection resource figure
The minimum paths of cost are found for target drain terminal t；
3rd step, defines integer variable i as the index of gauze set N, and i is initialized as into 0, will gather
SinkSet is empty, and from gauze set N the 1st gauze N [i] is taken；
4th step, checks the wiring tree RT that the gauze N [i] of last iteration sets up, and path illegal on RT is removed, by these
The occupancy of the interconnection resource node on path subtracts 1 and corresponding drain terminal sink is added in set SinkSet；
5th step, to current wiring tree RT Time-Series analyses are re-started, and connect up the time delay Tdel of root vertex root
(root) it is defined as：
Tdel (root)=0.5*rootC*rootR
Wherein, rootCRepresent the electric capacity of root node root, rootRThe resistance of root node root is represented, for every on RT
One node n, time delay Tdel (n) of node n is defined as：
Tdel (n)=Tdel (npre)+sT+sC*sR+0.5*nC*nR
Wherein, npreRepresent the predecessor node of node n, Tdel (npre) represent npreTime delay, s represents connecting node npreWith
The switch of n, sT、sCAnd sRInherent delay, electric capacity and the resistance of s, n are represented respectivelyCAnd nRThe electric capacity and electricity of node n are represented respectively
Resistance；
6th step, to each drain terminal in SinkSet, calls wiring unit to seek for target drain terminal t on interconnection resource figure
Look for the paths that cost is minimum；
7th step, plus 1 by variable i, and from gauze set N i-th gauze N [i] is taken, if N [i] is sky, i.e., there is no N
[i], performs the 8th step, otherwise goes to the 4th step and continues executing with；
8th step, checks that wiring result, with the presence or absence of crowded, if there is crowded, then updates the crowded of all interconnection resources
Degree, turns the 3rd step and continues executing with；If there is no crowded, then it is cabled successfully, algorithm terminates；If there is section on interconnection resource figure
More than capacity values, then node v exists crowded and wiring result is illegal, v's for point v, the wherein value of the occupancy of v
Occupancy represents the number of times that node v is used, and capacity represents the capacity of node v；Updating interconnection resource crowding
When, the current crowding of node v is：
PresentCost (v)=1+pres_fac* (1+occupancy-capacity)
Wherein pres_fac represents current crowded penalty factor, if node v exists crowded, the history crowding of v is：
HistoryCost (v) +=hist_fac* (occupancy-capacity)
Wherein hist_fac represents the crowded penalty factor of history.
Further, in second step and the 6th step, wiring unit is called to find into for target drain terminal t on interconnection resource figure
Originally the concrete grammar of a minimum paths is：
Step one, is initialized, for the node n on wiring tree, if n is at sink pair with current wiring tree to wavefront
In the Bounding Box sink-box for answering, then calculate from path cost Bcost (n) and source of gauze source point source to n to
Path cost Tcost (n) of target drain terminal point t, by node n wavefront is added to；If n is not in the range of sink-box, no
Wavefront is added it to, Bcost (n) and Tcost (n) are defined as：
Bcost (n)=critt*Tdel(n)
Tcost (n)=Bcost (n)+α * estn,t
Wherein crittThe criticality of target endpoint t is represented, Tdel (n) represents the time delay of node n, estn,tRepresent from node
The path estimation cost of n to t, parameter alpha is used for balancing impact of the path estimated cost in total path cost；
Step 2, selects the node v of cost minimization from wavefrontminIf, vminIt is target drain terminal point t, goes to step four；
Step 3, for vminNeighbor node v, calculate from path cost Bcost (v) of gauze source point source to v with
And node v is added to wavefront by source to path cost Tcost (v) of target drain terminal point t, goes to step two execution, if v
On current wiring tree, then Bcost (v) and Tcost (v) are：
Bcost (v)=critt*Tdel(v)
Tcost (v)=Bcost (v)+α * estv,t
If not on current wiring tree, Bcost (v) and Tcost (v) is v：
Bcost (v)=Bcost (vmin)+Cost(v)
Tcost (v)=Bcost (v)+α * estv,t
Wherein crittThe criticality of target endpoint t is represented, Tdel (v) represents the time delay of node v, estv,tRepresent from node
The path estimation cost of v to t, parameter alpha is used for balancing impact of the path estimated cost in total path cost, and Cost (v) is represented
The use cost of node v；
Cost (v)=critt*dv+(1-critt)*bv*pv*hv
Wherein dvRepresent the inherent delay of node v, bvRepresent the basic use cost of v, pvRepresent the current crowding of v, hv
Represent the history crowding of v；
Step 4, sets up from t to the path of source node source, and updates the crowding of node on the path.
Further, in the 4th step, the concrete grammar for removing path illegal on current wiring tree RT is：
Step one, chooses the upper first node n of wiring tree；
Step 2, if taking the capacity capacity, wiring tree RT of the line screen occupancy more than n of node n
The path of upper all use n is the illegal route, the drain terminal point of these path connections is added in set SinkSet, by these
The occupancy of the interconnection resource on path subtracts 1 and updates its current crowding PresCost (n)：
PresCost (n)=1+pres_fac* (1+occupancy-capacity)
Wherein pres_fac represents current crowded penalty factor；
Step 3, if n is gauze drain terminal point, from the connection criticality of gauze source point source to n 0.9 and n is more than
Time delay n in iteration more than before minimum time delay, then the path that n is located is the illegal route, by the interconnection resource on the path
Occupancy subtract 1 and update its current crowding PresCost (n), addition n to set SinkSet in；
Step 4, if exist on wiring tree not being accessed for node n, takes out node n and goes to step 2 and continue to hold
OK.
The invention has the beneficial effects as follows：
(1) present invention is improved the strategy for rerouting so that improved rewiring strategy can reduce each cloth
The number of paths of weight cloth, realizes the acceleration to wiring process during line interation.
(2) present invention is improved the wavefront expansion for connecting up bottom, due to only using when wavefront is initialized
Part wiring tree, reduces the wavefront initialized time.
(3) present invention preferably resolves the low problem of CPU elapsed time length, efficiency in existing FPGA wiring process.
The technique effect of the design, concrete structure and generation of the present invention is described further below with reference to accompanying drawing, with
It is fully understood from the purpose of the present invention, feature and effect.
Description of the drawings
Fig. 1 is the overview flow chart of quick FPGA wiring methods of the invention；
Fig. 2 is the flow chart of quick FPGA wirings initialization wiring of the invention；
Fig. 3 is the flow chart after present invention initialization wiring.
Specific embodiment
In order that the objects, technical solutions and advantages of the present invention become more apparent, with reference to embodiments, to the present invention
It is further elaborated.It should be appreciated that specific embodiment described herein is not used to only to explain the present invention
Limit the present invention.
Below in conjunction with the accompanying drawings and specific embodiment to the present invention application principle be further described, it should be noted that
The present embodiment gives detailed embodiment and specific operating process, but the guarantor of the present invention premised on the technical program
Shield scope is not limited to the present embodiment.
As shown in figure 1, the quick FPGA wiring methods of the embodiment of the present invention are comprised the following steps：
The first step, distributes and calculates Bounding Box.Each connection for gauze distributes a Bounding Box sink-box, each
Individual sink-box is dimensioned to the Bounding Box of corresponding source and sink toward one unit of external expansion.
Second step, initialization wiring.Each drain terminal t to each gauze, calls wiring unit on interconnection resource figure
The minimum paths of cost are found for target drain terminal t.
3rd step, cloth line interation.In wiring iterative process every time, the fast wiring method travels through all of gauze, and
The result of member-retaining portion last iteration, so as to the drain terminal point quantity that the needs for reducing current iteration are rerouted.If wiring result
There is crowded, the then wiring of cloth line interation continuation next time；Otherwise, it is cabled successfully.Wherein rewiring tool is carried out to each gauze
Body is comprised the following steps：
Step (a), travels through the wiring tree RT of the gauze, removes wherein illegal path and corresponding sink is saved in into collection
In closing SinkSet, the wiring tree RT of the gauze is produced by the front iteration that once connects up, by the road of the gauze source point to all drain terminal points
Footpath is constituted.
Step (b), calls wiring unit to be that the sink being not connected with the gauze is connected up.Wiring unit is every time by wiring
Wavefront is extended on resource map is connected up for a sink；In the wavefront expansion starting stage, first with current wiring tree
On part of nodes wavefront is initialized, then the node n of wherein cost minimization is extended, and the neighbours of n are saved
Point is added to wavefront.
The present invention's concretely comprises the following steps：
(1) one Bounding Box sink-box of distribution is connected per a pair for gauze, it is right that each sink-box is dimensioned to
Source source answered and the Bounding Box of drain terminal sink are toward one unit of external expansion；
(1a) abscissas and vertical coordinate of the source and sink on interconnection resource figure is calculated；
(1b) Bounding Box for sink-box being set to into source and sink is onesize, then by sink-box toward extending out
One unit of exhibition.
(2) initialization wiring.Each drain terminal t to each gauze, calls wiring unit to be mesh on interconnection resource figure
Mark drain terminal t finds the minimum paths of cost and specifically includes following steps：
(2a) wavefront is initialized with current wiring tree.For the node n on wiring tree, if n is in sink correspondences
Bounding Box sink-box in, then calculate from path cost Bcost (n) and source of gauze source point source to n to mesh
Path cost Tcost (n) of mark drain terminal point t, by node n wavefront is added to；If n is not in the range of sink-box, will not
It is added to wavefront.Bcost (n) and Tcost (n) are defined as：
Bcost (n)=critt*Tdel(n)
Tcost (n)=Bcost (n)+α * estn,t
Wherein crittThe criticality of target endpoint t is represented, Tdel (n) represents the time delay of node n, estn,tRepresent from node
The path estimation cost of n to t, parameter alpha is used for balancing impact of the path estimated cost in total path cost；
(2b) the node v of cost minimization is selected from wavefrontmin.If vminIt is target drain terminal point t, turns (2d)；
(2c) for vminNeighbor node v, calculate from path cost Bcost (v) of gauze source point source to v and
Node v is added to wavefront by source to path cost Tcost (v) of target drain terminal point t, goes to step (2b) execution.If v
On current wiring tree, then Bcost (v) and Tcost (v) are：
Bcost (v)=critt*Tdel(v)
Tcost (v)=Bcost (v)+α * estv,t
If not on current wiring tree, Bcost (v) and Tcost (v) is v：
Bcost (v)=Bcost (vmin)+Cost(v)
Tcost (v)=Bcost (v)+α * estv,t
Wherein crittThe criticality of target endpoint t is represented, Tdel (v) represents the time delay of node v, estv,tRepresent from node
The path estimation cost of v to t, parameter alpha is used for balancing impact of the path estimated cost in total path cost, and Cost (v) is represented
The use cost of node v；
Cost (v)=critt*dv+(1-critt)*bv*pv*hv
Wherein dvRepresent the inherent delay of node v, bvRepresent the basic use cost of v, pvRepresent the current crowding of v, hv
Represent the history crowding of v；
(2d) set up from t to the path of source node source, and update the crowding of node on the path.
The occupancy of v represents the number of times that node v is used, and adds 1 by the value of occupancy, and node v's is current crowded
Spend and be：
PresentCost (v)=1+pres_fac* (1+occupancy-capacity)
Wherein pres_fac represents current crowded penalty factor.
(3) integer variable i is defined as the index of gauze set N, i is initialized as into 0, comprising upper in set SinkSet
Secondary iteration last gauze needs the drain terminal point of weight cloth, therefore SinkSet is empty；The 1st gauze N is taken from gauze set N
Gauze carries out descending sort according to the number of drain terminal point sink in [i], wherein gauze set N, is that sink numbers are maximum in N [i]
Gauze；
(4) check that last iteration is the wiring tree RT that gauze N [i] sets up, remove path illegal on RT；
(4a) the upper first interconnection resource node n of wiring tree is chosen；
If the capacity capacitys of the line screen occupancy more than n of node n (4b) is taken, on wiring tree RT
The path of all use n is the illegal route, the drain terminal point of these path connections is added in set SinkSet, by these roads
The occupancy of the interconnection resource on footpath subtracts 1 and updates its current crowding PresCost (n)：
PresCost (n)=1+pres_fac* (1+occupancy-capacity)
Wherein pres_fac represents current crowded penalty factor.
If (4c) n is gauze drain terminal point sink, from the connection criticality of gauze source point source to n 0.9 and n is more than
Time delay n in iteration more than before minimum time delay, then the path that n is located is the illegal route, by the interconnection resource on the path
Occupancy subtract 1 and update its current crowding PresCost (n), n is added in set SinkSet；
If (4d) existing and not being accessed for node n on wiring tree, take out node n and go to (4b) and continue executing with.
(5) due to having removed the illegal route on wiring tree, current wiring is set the time sequence information of upper each node and is changed
Become, need to re-start Time-Series analyses to current wiring tree RT；
(5a) the time delay Tdel (root) for connecting up root vertex root is defined as：
Tdel (root)=0.5*rootC*rootR
Wherein, rootCRepresent the electric capacity of root node root, rootRRepresent the resistance of root node root.
(5b) for each node n on wiring tree RT, time delay Tdel (n) of node n is defined as：
Tdel (n)=Tdel (npre)+sT+sC*sR+0.5*nC*nR
Wherein, npreRepresent the predecessor node of node n, Tdel (npre) represent npreTime delay, s represents connecting node npreWith
The switch of n, sT、sCAnd sRInherent delay, electric capacity and the resistance of s, n are represented respectivelyCAnd nRThe electric capacity and electricity of node n are represented respectively
Resistance.
The time delay of known wiring root vertex, carrying out calculating according to above-mentioned formula can derive upper each node of wiring tree
Time delay, the time delay per paths is exactly the time delay of corresponding drain terminal point sink.
(6) to each drain terminal in SinkSet, wiring unit is called to find into for target drain terminal t on interconnection resource figure
This minimum paths, concrete steps are with (2a)-(2d)；
(7) if there is the gauze for not weighing cloth, then next gauze execution step (4) is taken；Otherwise go to step (8) execution；
(8) check whether wiring is successful, if wiring result is legal, wiring terminates, and otherwise continues to connect up next time repeatedly
Generation；
(8a) all nodes on interconnection resource figure, if there is node n on interconnection resource figure, wherein n's are traveled through
More than capacity values, then node n exists crowded the value of occupancy and wiring result is illegal, goes to step (8b)；If institute
There is interconnection resource not occur crowded, then go to step (3)；
(8b) the current crowding and history crowding of all interconnection resource nodes are updated.For a node v,
Occupancy represents the number of times that node v is used, and capacity represents the capacity of node v.The current crowding of node v is：
PresentCost (v)=1+pres_fac* (1+occupancy-capacity)
Wherein pres_fac represents current crowded penalty factor.If node v exists crowded, the history crowding of v is：
HistoryCost (v) +=hist_fac* (occupancy-capacity)
Wherein hist_fac represents the crowded penalty factor of history.
With reference to Fig. 2, Fig. 3 and emulation experiment, the present invention will be further described：
As shown in Fig. 2 the initialization wiring method for realizing quick FPGA wirings of the present invention is as follows：
The first step, according to fpga chip information creating interconnection resource figure RRG, the node on RRG represents FPGA interconnectors
The pin of resource or logical block, the side of connecting node represents switch.Every a pair of source and sink for gauze after layout distributes
One Bounding Box sink-box；Sink-box is actually a rectangular area, and each sink-box is dimensioned to correspondence
Source and sink Bounding Box toward one unit of external expansion.
Second step, each drain terminal t to each gauze calls wiring unit to be target drain terminal t on interconnection resource figure
The minimum paths of cost are found, so as to obtain a primary route wiring result；In initialization wiring process, it is allowed to many
Individual gauze uses identical interconnection resource.
Step one, is initialized, if t is first drain terminal of the gauze, currently with current wiring tree to wavefront
Wiring tree only includes the source point of the gauze.For the node n on wiring tree, judge n whether at sink pair by the two of n coordinates
In the Bounding Box sink-box for answering, if n is inside sink-box, the path cost from gauze source point source to n is calculated
Node n is added to wavefront by Bcost (n) and source to path cost Tcost (n) of target drain terminal point t；If n does not exist
In the range of sink-box, then wavefront is not added it to.In fact, wavefront is a Priority Queues realized by minimum heapsort
PQ, it is also a sequencer procedure according to Tcost (n) that node n is added to into wavefront, and the Tcost values of heap top node are less.
Bcost (n) and Tcost (n) are defined as：
Bcost (n)=critt*Tdel(n)
Tcost (n)=Bcost (n)+α * estn,t
Wherein crittThe criticality of target endpoint t is represented, Tdel (n) represents the time delay of node n, estn,tRepresent from node
The path estimation cost of n to t, parameter alpha is used for balancing impact of the path estimated cost in total path cost, realizes directional
Heuristic search, accelerate search destination node t process, α spans be 1.0 to 1.4；
Step 2, selects the node v of cost minimization from wavefront PQmin, node vminIt is removed node in rear PQ again
It is ranked up.If vminIt is target drain terminal point t, goes to step four；
Step 3, accesses vminNeighbor node v, calculate from path cost Bcost (v) of gauze source point source to v with
And node v is added to wavefront PQ by source to path cost Tcost (v) of target drain terminal point t.If v is current wiring tree
On node, then Bcost (v) and Tcost (v) are：
Bcost (v)=critt*Tdel(v)
Tcost (v)=Bcost (v)+α * estv,t
If not on current wiring tree, Bcost (v) and Tcost (v) is v：
Bcost (v)=Bcost (vmin)+Cost(v)
Tcost (v)=Bcost (v)+α * estv,t
Wherein crittThe criticality of target endpoint t is represented, Tdel (v) represents the time delay of node v, estv,tRepresent from node
The path estimation cost of v to t, parameter alpha is used for balancing impact of the path estimated cost in total path cost, and Cost (v) is represented
The use cost of node v；
Cost (v)=critt*dv+(1-critt)*bv*pv*hv
Wherein dvRepresent the inherent delay of node v, bvRepresent the basic use cost of v, pvRepresent the current crowding of v, hv
Represent the history crowding of v；The criticality crit of target endpoint ttIt is defined as：
Wherein 0.99 for path maximum criticality, slacktThe time delay allowance from gauze source source to t is represented,
DmaxThe circuit critical path time delay is represented, η is control connection allowance to crowding and the parameter of time delay tradeoff.
Step 4, target drain terminal point t is marked, and sets up from t to the path of source node source and preserve wire bond
Really；The use degree occupancy of some on the path is added 1 and current crowding is updated；When re-starting to whole wiring tree
Sequence is analyzed, and wavefront PQ is emptied.
As shown in figure 3, iteration wiring method is as follows after the initialization wiring for realizing quick FPGA wirings of the present invention：
3rd step, defines integer variable i as the index of gauze set N, i is initialized as into 0, according to maximum gauze
Drain terminal number be set SinkSet allocation spaces, take the 1st gauze N [i] from gauze set N, the electricity is saved in set N
All of gauze in road network table, and according to the number descending preservation of gauze target drain terminal；
4th step, checks that last iteration is the wiring tree RT that gauze N [i] sets up, and the source from gauze N [i] is to all leakages
The path at end together constitutes wiring tree RT；Path illegal on RT is removed, by accounting for for the interconnection resource node on these paths
Degree of having subtracts 1 and corresponding drain terminal sink is added in set SinkSet；
Step one, chooses the upper first interconnection resource node n of wiring tree；
Step 2, if taking the capacity capacity, wiring tree RT of the line screen occupancy more than n of node n
The path of upper all use n is the illegal route, calls recursive function free_route_tree () to remove these paths, by these
The drain terminal point of path connection is added in set SinkSet, subtracts 1 and more by the occupancy of the interconnection resource on these paths
New its current crowding PresCost (n)：
PresCost (n)=1+pres_fac* (1+occupancy-capacity)
Wherein pres_fac represents current crowded penalty factor.
Step 3, if n is gauze drain terminal point, from the connection criticality of gauze source point source to n 0.9 and n is more than
Time delay n in iteration more than before minimum time delay, then the path that n is located is the illegal route, by the interconnection resource on the path
Occupancy subtract 1 and update current crowding PresCost (n) using above-mentioned formula, in addition n to set SinkSet；
Step 4, if exist on wiring tree not being accessed for node n, takes out node n and goes to step 2 and continue to hold
OK.
5th step, after having removed the illegal route on wiring tree RT, the overall timing performance of RT changes, to current cloth
Line tree RT re-starts Time-Series analyses, and the time delay Tdel (root) for connecting up root vertex root is defined as：
Tdel (root)=0.5*rootC*rootR
Wherein, rootCRepresent the electric capacity of root node root, rootRRepresent the resistance of root node root.Due to connecting up tree root
The time delay of node root can be calculated according to the resistance of root and capacitance information, be calculated according to below equation, successively
The delayed data of the upper all nodes of current wiring tree can be obtained.For each node n on RT, the time delay of node n
Tdel (n) is defined as：
Tdel (n)=Tdel (npre)+sT+sC*sR+0.5*nC*nR
Wherein, npreRepresent the predecessor node of node n, Tdel (npre) represent npreTime delay, s represents connecting node npreWith
The switch of n, sT、sCAnd sRInherent delay, electric capacity and the resistance of s, n are represented respectivelyCAnd nRThe electric capacity and electricity of node n are represented respectively
Resistance.
6th step, after the illegal route on wiring tree has been removed, corresponding drain terminal point is stored in set SinkSet.
To each sink in SinkSet, call wiring unit and find minimum one of cost for target drain terminal t on interconnection resource figure
Path, with the step one in second step to step 4；
7th step, from gauze set N next gauze is taken, and i adds 1, if N [i] is sky, i.e., there is no N [i], represents this
Secondary cloth line interation has completed the heavy cloth to all of gauze in the circuit meshwork list, performs the 8th step；Otherwise go to the continuation of the 4th step
Weight cloth next one gauze N [i]；
8th step, after the heavy cloth to institute's wired network is completed, checks and whether there is on interconnection resource figure RRG node v so that
The value of the occupancy of v is taken by multiple gauzes simultaneously more than capacity values, then node v, and wiring result is illegal, is updated
The crowding of all interconnection resources, turns the 3rd step and continues cloth line interation next time：When interconnection resource crowding is updated, node v
Current crowding be：
PresentCost (v)=1+pres_fac* (1+occupancy-capacity)
Wherein pres_fac represents current crowded penalty factor.If node v exists crowded, the history crowding of v is：
HistoryCost (v) +=hist_fac* (occupancy-capacity)
Wherein hist_fac represents the crowded penalty factor of history.
If do not exist on interconnection resource figure RRG there is crowded node, then it represents that be cabled successfully, by wiring result output
To in the file of .route forms.
The effect of the present invention can be by following emulation further instruction：
1st, simulated conditions, are emulated in Fedora-17-i386 systems, and hardware platform is the core work stations of HPZ800 tetra-.
VPR (Versatile Placement and of the quick FPGA wiring methods proposed by the present invention in University of Toronto
Routing) realize on 7.0, VPR 7.0 be current academia at the scene in programmable gate array (FPGA) placement-and-routing problem most
One of good instrument.Quick FPGA wiring methods (RORA) are compared with VPR 7.0, emulation adopts field-programmable gate array
Row (FPGA) structured file is k4n10.xml, the lut of as 4 inputs, and 10 lut are encapsulated in each configurable logic cell CLB
FPGA structure.From test circuit include that the MCNC circuits of 20 maximums, VPR test circuits, IWLS2005 and QUIP are electric
Road.Test circuit is divided into 3 groups, and the wiring times of VPR 7.0 of circuit are less than 10 seconds in second group, the VPR of the 3rd group of test circuit
7.0 wiring times are more than 10 seconds.All circuits use 1.2 times of minimal channel widths.
2nd, emulation content, is respectively adopted fast wiring method proposed by the present invention and VPR 7.0 conventional in the world is connected up
Instrument carries out emulation experiment, the time delay of circuit and line length after result is taken and connected up from the CPU of wiring process and is compared.Its
In, time delay represents final circuit critical path time delay, and it determines the speed of service of final circuit；Line length represents final circuit institute
The total wire length to be used.Emulation every time is repeated 10 times, and the simulation experiment result is averaged, and obtains the wiring side of the present invention
Method (RORA) is contrasted with the wiring methods of existing VPR 7.0 in cloth linear velocity and quality simulation.
3rd, simulation result, is emulated with three groups of circuits, is as a result distinguished as shown in Table 1, 2 and 3：
The wiring method of the present invention of table 1 connects up Comparative result with VPR 7.0
The wiring method of the present invention of table 2 connects up Comparative result with VPR 7.0
The wiring method of the present invention of table 3 connects up Comparative result with VPR 7.0
As it can be seen from table 1 being better than the sides of wiring of existing VPR 7.0 in time-consuming aspect fast wiring method proposed by the present invention
Method, wiring time averagely reduces 68.5%, and time delay and line length reduce respectively 2.5% and 1.4%；From table 2 it can be seen that during wiring
Between it is average reduce 63%, time delay and line length reduce 0.5%；As shown in table 3, compare with VPR 7.0, it is proposed by the present invention quick
Wiring method reduces wiring time 66.7%, and the time delay of circuit critical path reduces 0.2%, and total line length reduces 2%.It is imitative according to more than
True experiment and data result, with currently, in the world compared with main flow wiring tool VPR 7.0, average wiring time is reduced the present invention
66.1%, the time delay of circuit critical path reduces 1.1%, and line length reduces 1.3%.When circuit is bigger, the present invention is connected up to FPGA
Acceleration effect it is better.
To sum up, quick FPGA wiring methods of the invention, belong to computer realm.Present invention employs new rewiring plan
Omit and wavefront expansion, realize the acceleration to wiring process so that the time delay of final circuit and two important performance indexes of line length are equal
In the case of optimization, hence it is evident that reduce wiring time.
The preferred embodiment of the present invention described in detail above.It should be appreciated that one of ordinary skill in the art without
Need creative work just can make many modifications and variations with design of the invention.Therefore, all technologies in the art
Personnel are available by logical analysis, reasoning, or a limited experiment on the basis of existing technology under this invention's idea
Technical scheme, all should be in the protection domain being defined in the patent claims.
Claims (3)
1. a kind of quick FPGA wiring methods, it is characterised in that the quick FPGA wiring methods are comprised the following steps：
The first step, each gauze is made up of source source and multiple drain terminal sink in circuit meshwork list, is first gauze
Every a pair of source and sink distribute a Bounding Box sink-box, each sink-box is dimensioned to corresponding
The Bounding Box of source and sink is toward one unit of external expansion；
Second step, initialization wiring, each drain terminal t to each gauze calls wiring unit to be mesh on interconnection resource figure
Mark drain terminal t finds the minimum paths of cost；
3rd step, defines integer variable i as the index of gauze set N, and i is initialized as into 0, and set SinkSet is put
Sky, from gauze set N the 1st gauze N [i] is taken；
4th step, checks the wiring tree RT that the gauze N [i] of last iteration sets up, and path illegal on RT is removed, by these paths
On the occupancy of interconnection resource node subtract 1 and corresponding drain terminal sink be added in set SinkSet；
5th step, to current wiring tree RT Time-Series analyses are re-started, and the time delay Tdel (root) for connecting up root vertex root is fixed
Justice is：
Tdel (root)=0.5*rootC*rootR
Wherein, rootCRepresent the electric capacity of root node root, rootRThe resistance of root node root is represented, for each on RT
Node n, time delay Tdel (n) of node n is defined as：
Tdel (n)=Tdel (npre)+sT+sC*sR+0.5*nC*nR
Wherein, npreRepresent the predecessor node of node n, Tdel (npre) represent npreTime delay, s represents connecting node npreWith n's
Switch, sT、sCAnd sRInherent delay, electric capacity and the resistance of s, n are represented respectivelyCAnd nRThe electric capacity and resistance of node n are represented respectively；
6th step, to each drain terminal in SinkSet, calls wiring unit to find into for target drain terminal t on interconnection resource figure
This minimum paths；
7th step, plus 1 by variable i, and from gauze set N i-th gauze N [i] is taken, if N [i] is sky, i.e., there is no N [i], holds
The step of row the 8th, otherwise goes to the 4th step and continues executing with；
8th step, checks that wiring result, with the presence or absence of crowded, if there is crowded, then updates the crowding of all interconnection resources,
Turn the 3rd step to continue executing with；If there is no crowded, then it is cabled successfully, algorithm terminates；If there is node on interconnection resource figure
More than capacity values, then node v exists crowded the value of the occupancy of v, wherein v and wiring result is illegal, v's
Occupancy represents the number of times that node v is used, and capacity represents the capacity of node v；Updating interconnection resource crowding
When, the current crowding of node v is：
PresentCost (v)=1+pres_fac* (1+occupancy-capacity)
Wherein pres_fac represents current crowded penalty factor, if node v exists crowded, the history crowding of v is：
HistoryCost (v) +=hist_fac* (occupancy-capacity)
Wherein hist_fac represents the crowded penalty factor of history.
2. FPGA wiring methods as claimed in claim 1 quick, it is characterised in that in second step and the 6th step, call cloth
Line device is that the concrete grammar that target drain terminal t finds the minimum paths of cost is on interconnection resource figure：
Step one, is initialized, for the node n on wiring tree, if n is corresponding in sink with current wiring tree to wavefront
In Bounding Box sink-box, then calculate from path cost Bcost (n) and source of gauze source point source to n to target
Path cost Tcost (n) of drain terminal point t, by node n wavefront is added to；If n is not in the range of sink-box, not by it
Wavefront is added to, Bcost (n) and Tcost (n) are defined as：
Bcost (n)=critt*Tdel(n)
Tcost (n)=Bcost (n)+α * estn,t
Wherein crittThe criticality of target endpoint t is represented, Tdel (n) represents the time delay of node n, estn,tRepresent from node n to t
Path estimation cost, parameter alpha be used for balance impact of the path estimated cost in total path cost；
Step 2, selects the node v of cost minimization from wavefrontminIf, vminIt is target drain terminal point t, goes to step four；
Step 3, for vminNeighbor node v, calculate from path cost Bcost (v) of gauze source point source to v and
Node v is added to wavefront by source to path cost Tcost (v) of target drain terminal point t, goes to step two execution, if v exists
On current wiring tree, then Bcost (v) and Tcost (v) are：
Bcost (v)=critt*Tdel(v)
Tcost (v)=Bcost (v)+α * estv,t
If not on current wiring tree, Bcost (v) and Tcost (v) is v：
Bcost (v)=Bcost (vmin)+Cost(v)
Tcost (v)=Bcost (v)+α * estv,t
Wherein crittThe criticality of target endpoint t is represented, Tdel (v) represents the time delay of node v, estv,tRepresent from node v to t
Path estimation cost, parameter alpha is used for balancing impact of the path estimated cost in total path cost, and Cost (v) represents node v
Use cost；
Cost (v)=critt*dv+(1-critt)*bv*pv*hv
Wherein dvRepresent the inherent delay of node v, bvRepresent the basic use cost of v, pvRepresent the current crowding of v, hvRepresent v
History crowding；
Step 4, sets up from t to the path of source node source, and updates the crowding of node on the path.
3. FPGA wiring methods as claimed in claim 1 quick, it is characterised in that in the 4th step, remove current wiring tree
The concrete grammar in the upper illegal paths of RT is：
Step one, chooses the upper first node n of wiring tree；
Step 2, if taking the capacity capacitys of the line screen occupancy more than n of node n, institute on wiring tree RT
It is the illegal route to have using the path of n, the drain terminal point of these path connections is added in set SinkSet, by these paths
On the occupancy of interconnection resource subtract 1 and update its current crowding PresCost (n)：
PresCost (n)=1+pres_fac* (1+occupancy-capacity)
Wherein pres_fac represents current crowded penalty factor；
Step 3, if n is gauze drain terminal point, from connection criticality the prolonging more than 0.9 and n of gauze source point source to n
When minimum time delay more than n in iteration before, then the path that n is located is the illegal route, by the interconnection resource on the path
Occupancy subtracts 1 and updates its current crowding PresCost (n), in addition n to set SinkSet；
Step 4, if existing and not being accessed for node n on wiring tree, takes out node n and goes to step 2 and continue executing with.
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| CN111709205A (en) * | 2020-05-29 | 2020-09-25 | 成都华微电子科技有限公司 | FPGA wiring method |
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| CN109710981A (en) * | 2018-02-27 | 2019-05-03 | 上海安路信息科技有限公司 | The wiring method and system of FPGA |
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| CN112183000B (en) * | 2020-10-10 | 2023-03-07 | 上海思尔芯技术股份有限公司 | Hypergraph partitioning method supporting interconnection constraint |
| CN117131825A (en) * | 2023-10-27 | 2023-11-28 | 中科亿海微电子科技（苏州）有限公司 | Repair wiring method and device based on setup time |
| CN117131825B (en) * | 2023-10-27 | 2024-01-30 | 中科亿海微电子科技（苏州）有限公司 | Repair wiring method and device based on setup time |
| CN117787172A (en) * | 2023-12-27 | 2024-03-29 | 苏州异格技术有限公司 | Construction method and device of wiring resource diagram, computer equipment and storage medium |
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