CN106681856B - Decoding method, memory storage device and memory control circuit unit - Google Patents

Decoding method, memory storage device and memory control circuit unit Download PDF

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Publication number
CN106681856B
CN106681856B CN201610711090.4A CN201610711090A CN106681856B CN 106681856 B CN106681856 B CN 106681856B CN 201610711090 A CN201610711090 A CN 201610711090A CN 106681856 B CN106681856 B CN 106681856B
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decoding
condition
memory
data
data based
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CN106681856A (en
Inventor
林玉祥
严绍维
杨政哲
赖国欣
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Hefei Core Storage Electronic Ltd
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Hefei Core Storage Electronic Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check

Abstract

The invention provides a decoding method, a memory storage device and a memory control circuit unit. The decoding method comprises the following steps: reading first data from a plurality of first memory cells of a rewritable non-volatile memory module; performing a first decoding operation on the first data based on a first decoding condition; and if the first decoding operation meets a first preset state, performing a second decoding operation on the first data based on a second decoding condition, wherein the rigor for locating the error bit in the first data based on the second decoding condition is higher than the rigor for locating the error bit in the first data based on the first decoding condition. Therefore, the decoding efficiency of the memory storage device can be improved.

Description

Decoding method, memory storage device and memory control circuit unit
Technical Field
The present invention relates to a decoding technique, and more particularly, to a decoding method, a memory storage device and a memory control circuit unit.
Background
Digital cameras, mobile phones and MP3 players have grown very rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable nonvolatile memory module (e.g., flash memory) has the characteristics of data non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices exemplified above.
Generally, a memory device has one or more built-in decoding mechanisms for correcting errors that may be present in data read from the memory device. For example, such decoding mechanisms may include decoding algorithms such as a Bit-Flipping (Bit-Flipping) algorithm, a Min-Sum (Min-Sum) algorithm, and a Sum-Product (Sum-Product) algorithm. At the time of shipment of the memory device, the decoding algorithm built in the memory device is configured to use the optimized operating parameters. However, as the usage time and/or frequency of the memory device increases, the channel state of the memory device may also change. Even using optimized operating parameters tends to result in inefficient decoding of the memory device if the channel state of the memory device varies too much.
Disclosure of Invention
The invention provides a decoding method, a memory storage device and a memory control circuit unit, which can improve the decoding efficiency of the memory storage device.
An example embodiment of the present invention provides a decoding method for a rewritable nonvolatile memory module including a plurality of memory cells, the decoding method including: reading first data from a plurality of first memory cells of the plurality of memory cells; performing a first decoding operation on the first data based on a first decoding condition; and if the first decoding operation meets a first preset state, performing a second decoding operation on the first data based on a second decoding condition, wherein the rigor for locating the error bit in the first data based on the second decoding condition is higher than the rigor for locating the error bit in the first data based on the first decoding condition.
In an exemplary embodiment of the present invention, the decoding method further includes: performing a third decoding operation on the first data based on a third decoding condition if the first decoding operation meets a second predetermined condition, wherein the stringency for locating the erroneous bits in the first data based on the third decoding condition is lower than the stringency for locating the erroneous bits in the first data based on the first decoding condition.
In an exemplary embodiment of the present invention, the decoding method further includes: counting an iteration count value of the first decoding operation if the first decoding condition meets a stage condition; and if the iteration count value meets the counting condition, judging that the first decoding operation meets the first preset state.
In an exemplary embodiment of the present invention, the decoding method further includes: and if the first decoding condition does not meet the stage condition and the total number of the bits turned over by the first decoding operation meets the number condition, judging that the first decoding operation meets the second preset state.
In an exemplary embodiment of the present invention, the decoding method further includes: the count condition is selected from a first candidate count condition and a second candidate count condition, wherein the first candidate count condition corresponds to a first count value, the second candidate count condition corresponds to a second count value, and the first count value is different from the second count value.
In an exemplary embodiment of the present invention, the decoding method further includes: selecting the second decoding condition from a first candidate decoding condition and a second candidate decoding condition, wherein a stringency of locating an erroneous bit in the data based on the first candidate decoding condition is higher than a stringency of locating the erroneous bit in the data based on the second candidate decoding condition.
In an exemplary embodiment of the present invention, the decoding method further includes: performing a parity check operation on the first data to obtain a syndrome sum of the first data; if the syndrome summation is smaller than a preset value, reducing the error weight value of the bit in the first data from a first error weight value to a second error weight value; and flipping the bit in the first decoding operation if the second error weight value is greater than a flipping threshold corresponding to the first decoding condition.
Another exemplary embodiment of the present invention provides a memory storage device including a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The rewritable non-volatile memory module includes a plurality of memory cells. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module, and configured to send a read instruction sequence, where the read instruction sequence indicates to read first data from a plurality of first memory cells of the plurality of memory cells, and to perform a first decoding operation on the first data based on a first decoding condition, and if the first decoding operation meets a first preset state, the memory control circuit unit is further configured to perform a second decoding operation on the first data based on a second decoding condition, where a strictness of locating an error bit in the first data based on the second decoding condition is higher than a strictness of locating the error bit in the first data based on the first decoding condition.
In an exemplary embodiment of the invention, if the first decoding operation satisfies a second predetermined condition, the memory control circuit unit is further configured to perform a third decoding operation on the first data based on a third decoding condition, wherein the stringency for locating the error bits in the first data based on the third decoding condition is lower than the stringency for locating the error bits in the first data based on the first decoding condition.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to count an iteration count value of the first decoding operation if the first decoding condition meets a stage condition, and determine that the first decoding operation meets the first preset state if the iteration count value meets a count condition.
In an exemplary embodiment of the invention, the memory control circuit unit determines that the first decoding operation satisfies the second predetermined state if the first decoding condition does not satisfy the phase condition and the total number of bits inverted by the first decoding operation satisfies the number condition.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to select the counting condition from a first candidate counting condition and a second candidate counting condition, wherein the first candidate counting condition corresponds to a first counting value, the second candidate counting condition corresponds to a second counting value, and the first counting value is different from the second counting value.
In an example embodiment of the present invention, the memory control circuit unit is further configured to select the second decoding condition from a first candidate decoding condition and a second candidate decoding condition, wherein a stringency of locating an erroneous bit in the data based on the first candidate decoding condition is higher than a stringency of locating the erroneous bit in the data based on the second candidate decoding condition.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to perform a parity check operation on the first data to obtain a syndrome total of the first data, and if the syndrome total is smaller than a predetermined value, the memory control circuit unit is further configured to reduce an error weight value of a bit in the first data from a first error weight value to a second error weight value, and if the second error weight value is greater than a rollover threshold corresponding to the first decoding condition, the memory control circuit unit is further configured to rollover the bit in the first decoding operation.
Another exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable non-volatile memory module including a plurality of memory cells, the memory control circuit unit including a host interface, a memory interface, an error checking and correcting circuit, and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is to connect to the rewritable non-volatile memory module. The memory management circuitry is coupled to the host interface, the memory interface, and the error checking and correcting circuitry, the memory management circuitry to send a sequence of read instructions, wherein the read instruction sequence instructs reading of first data from a plurality of first memory cells of the plurality of memory cells, the error checking and correcting circuit is used for executing a first decoding operation on the first data based on a first decoding condition, if the first decoding operation meets a first preset state, the error checking and correcting circuit is also to perform a second decoding operation on the first data based on a second decoding condition, wherein the error checking and correcting circuit locates erroneous bits in the first data based on the second decoding condition with a higher stringency than the error checking and correcting circuit locates the erroneous bits in the first data based on the first decoding condition.
In an exemplary embodiment of the invention, if the first decoding operation satisfies a second predetermined condition, the error checking and correcting circuit is further configured to perform a third decoding operation on the first data based on a third decoding condition, wherein the error checking and correcting circuit locates the error bits in the first data less stringent based on the third decoding condition than the error checking and correcting circuit locates the error bits in the first data less stringent based on the first decoding condition.
In an exemplary embodiment of the invention, the memory management circuit is further configured to count an iteration count value of the first decoding operation if the first decoding condition meets a stage condition, and determine that the first decoding operation meets the first predetermined state if the iteration count value meets a count condition.
In an exemplary embodiment of the invention, the memory management circuit determines that the first decoding operation satisfies the second predetermined state if the first decoding condition does not satisfy the phase condition and the total number of bits inverted by the first decoding operation satisfies the number condition.
In an example embodiment of the present invention, the memory management circuit is further configured to select the counting condition from a first candidate counting condition and a second candidate counting condition, wherein the first candidate counting condition corresponds to a first counting value, the second candidate counting condition corresponds to a second counting value, and the first counting value is different from the second counting value.
In an example embodiment of the present invention, the memory management circuit is further configured to select the second decoding condition from a first candidate decoding condition and a second candidate decoding condition, wherein the error checking and correcting circuit locates the erroneous bits in the data with a higher stringency based on the first candidate decoding condition than the error checking and correcting circuit locates the erroneous bits in the data with a higher stringency based on the second candidate decoding condition.
In an exemplary embodiment of the invention, the error checking and correcting circuit is further configured to perform a parity checking operation on the first data to obtain a syndrome total of the first data, and if the syndrome total is smaller than a predetermined value, the error checking and correcting circuit is further configured to reduce an error weight value of a bit in the first data from a first error weight value to a second error weight value, and if the second error weight value is greater than a flipping threshold corresponding to the first decoding condition, the error checking and correcting circuit is further configured to flip the bit in the first decoding operation.
Based on the above, after the first decoding operation conforms to the first predetermined state, the decoding condition adopted by the decoding algorithm is updated to more rigorously locate the erroneous bits in the data to be decoded, thereby improving the processing efficiency of the decoding operation in the situation of error and convergence failure.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention.
FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.
FIG. 3 is a diagram illustrating a host system and a memory storage device according to another exemplary embodiment of the invention.
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.
FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.
FIG. 6 is a diagram illustrating a parity check matrix according to an exemplary embodiment of the present invention.
FIG. 7 is a graph illustrating threshold voltage distributions of memory cells according to an exemplary embodiment of the present invention.
Fig. 8 is a diagram illustrating switching phases in an iterative decoding operation according to an exemplary embodiment of the present invention.
Fig. 9A is a diagram illustrating a handover phase according to an example embodiment of the invention.
Fig. 9B is a diagram illustrating a handover phase according to another example embodiment of the present invention.
Fig. 9C is a diagram illustrating a handover phase according to another example embodiment of the present invention.
FIG. 10 is a diagram illustrating a parity check operation according to an exemplary embodiment of the present invention.
Fig. 11 is a flowchart illustrating a decoding method according to an exemplary embodiment of the present invention.
Fig. 12 is a flowchart illustrating a decoding method according to another exemplary embodiment of the present invention.
The reference numbers illustrate:
10. 30: a memory storage device;
11. 31: a host system;
110: a system bus;
111: a processor;
112: a random access memory;
113: a read-only memory;
114: a data transmission interface;
12: input/output (I/O) devices;
20: a main board;
201: a U disk;
202: a memory card;
203: a solid state disk;
204: a wireless memory storage device;
205: a global positioning system module;
206: a network interface card;
207: a wireless transmission device;
208: a keyboard;
209: a screen;
210: a horn;
32: an SD card;
33: a CF card;
34: an embedded storage device;
341: an embedded multimedia card;
342: an embedded multi-chip package storage device;
402: a connection interface unit;
404: a memory control circuit unit;
406: a rewritable non-volatile memory module;
502: a memory management circuit;
504: a host interface;
506: a memory interface;
508: an error checking and correcting circuit;
510: a buffer memory;
512: a power management circuit;
600. 1000: a parity check matrix;
710. 720: a state;
701: reading a voltage;
730: an overlap region;
1001: a code word;
1002: checking the vector;
s1101: a step of reading first data from a plurality of first memory cells of a rewritable nonvolatile memory module;
s1102: a step of performing a first decoding operation on the first data based on a first decoding condition;
s1103: step (judging whether the first decoding operation conforms to a first preset state or not);
s1104: a step of performing a second decoding operation on the first data based on a second decoding condition;
s1105: step (judging whether the first decoding operation accords with a second preset state or not);
s1106: a step of performing a third decoding operation on the first data based on a third decoding condition;
s1201: a step of reading first data from a plurality of first memory cells of a rewritable nonvolatile memory module;
s1202: a step of performing a parity check operation on the first data to obtain a syndrome sum of the first data;
s1203: step (judging whether the syndrome summation is smaller than a preset value);
s1204: a step of reducing an error weight value of each bit in the first data from a first error weight value to a second error weight value;
s1205: a step of performing a decoding operation on the first data based on a decoding condition;
s1206: step (judging whether the decoding operation accords with a first preset state or not);
s1207: a step of updating the decoding condition to a second decoding condition;
s1208: step (judging whether the decoding operation accords with a second preset state or not);
s1209: step (update decoding condition to third decoding condition).
Detailed Description
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention. Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all connected to a system bus (system bus) 110.
In the present exemplary embodiment, the host system 11 is connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 through data transfer interface 114. The host system 11 is connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 over the system bus 110.
In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be connected to the memory storage device 10 by wire or wirelessly through the data transmission interface 114. The memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be, for example, a Near Field Communication (NFC) memory storage device, a wireless fidelity (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a low power Bluetooth memory storage device (e.g., iBeacon) based memory storage device based on various wireless communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.
In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34. The embedded memory device 34 includes embedded Multi media card (eMMC) 341 and/or embedded Multi Chip Package (eMCP) memory device 342, which directly connects the memory module to the host system.
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404, and a rewritable nonvolatile memory module 406.
In the exemplary embodiment, connection interface unit 402 is compatible with Serial Advanced Technology Attachment (SATA) standards. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, High Speed Peripheral Component connection interface (PCI Express) standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed (UHS-I) interface standard, Ultra High Speed (UHS-II) interface standard, Memory Stick (Memory Stick, MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, Universal Flash (Flash) interface standard, CP interface standard, CF interface standard, Device interface (Electronic drive interface), IDE) standard or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404.
The memory control circuit unit 404 is used for executing a plurality of logic gates or control instructions implemented by hardware or software and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to instructions of the host system 11.
The rewritable nonvolatile memory module 406 is connected to the memory control circuit unit 404 and stores data written by the host system 11. The rewritable nonvolatile memory module 406 may be a Single Level Cell (SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a multiple Level Cell (TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
In the present exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 constitute a plurality of physical programming cells, and the physical programming cells constitute a plurality of physical erasing cells. For example, memory cells on the same byte line may constitute one or more physically programmed cells. If each memory cell can store more than 2 bits, the physical program cells on the same byte line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical programming cell is faster than that of the upper physical programming cell, and/or the reliability of the lower physical programming cell is higher than that of the upper physical programming cell.
In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, the physical programming unit is a physical page (page) or a physical fan (sector). If the physical program cells are physical pages, the physical program cells usually include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region stores system data (e.g., error correction codes). In the present exemplary embodiment, the data bit region includes 32 physical fans, and the size of one physical fan is 512-bit group (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. For example, the physical erase unit is a physical block (block).
In the present exemplary embodiment, each memory cell in the rewritable non-volatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage is also referred to as "writing data to the memory cell" or "programming the memory cell". Each memory cell in rewritable non-volatile memory block 406 has multiple memory states as the threshold voltage changes. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.
FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.
Referring to FIG. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, a memory interface 506, and an error checking and correcting circuit 508.
The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 502 is explained below, it is equivalent to the operation of the memory control circuit unit 404.
In the present exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in software. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.
In another exemplary embodiment, the control instructions of the memory management circuit 502 may also be stored in the form of program code in a specific area of the rewritable non-volatile memory module 406 (e.g., a system area of the memory module dedicated for storing system data). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.
In addition, in another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in hardware. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups thereof of the rewritable non-volatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406. The memory read circuit is used to issue a read command sequence to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 406 to perform corresponding operations of writing, reading, and erasing. In an example embodiment, the memory management circuit 502 may also issue other types of instruction sequences to the rewritable non-volatile memory module 406 to instruct the corresponding operations to be performed.
In the present exemplary embodiment, memory management circuit 502 configures a plurality of logic units to map physical erase units in rewritable non-volatile memory module 406. One logical unit may refer to one logical address, one logical program unit, one logical erase unit, or consist of multiple continuous or discontinuous logical addresses. In addition, a logical unit may be mapped to one or more physical erase units.
In the present exemplary embodiment, the memory management circuit 502 records the mapping relationship between the logical unit and the physical erase unit (also referred to as a logical-to-physical mapping relationship) in at least one logical-to-physical mapping table. When the host system 11 is going to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 502 can perform data access to the memory storage device 10 according to the logical-to-physical mapping table.
The host interface 504 is connected to the memory management circuit 502 and is used for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the exemplary embodiment, host interface 504 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transfer standard.
Memory interface 506 is coupled to memory management circuit 502 and is used to access rewritable non-volatile memory module 406. That is, data to be written to rewritable non-volatile memory module 406 is converted via memory interface 506 into a format that is acceptable to rewritable non-volatile memory module 406. Specifically, if memory management circuit 502 is to access rewritable non-volatile memory module 406, memory interface 506 transmits a corresponding sequence of instructions. For example, the command sequences may include a write command sequence for indicating data to be written, a read command sequence for indicating data to be read, an erase command sequence for indicating data to be erased, and command sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). These sequences of instructions are generated, for example, by memory management circuitry 502 and transferred to rewritable non-volatile memory module 406 through memory interface 506. The sequences of instructions may include one or more signals or data on a bus. Further, these signals or data may include instruction codes or program codes. For example, the read command sequence includes the read identification code, the memory address, and other information.
The error checking and correcting circuit 508 is connected to the memory management circuit 502 and is used for performing error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 508 performs the error checking and correcting operation on the read data according to the error correction code and/or the error check code.
In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 510 and a power management circuit 512.
The buffer memory 510 is connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is connected to the memory management circuit 502 and is used to control the power of the memory storage device 10.
In the exemplary embodiment, the error checking and correcting circuit 508 supports low-density parity-check (LDPC) codes. For example, the error checking and correcting circuit 508 may utilize low density parity check codes for encoding and decoding. In low density parity check codes, a check matrix (also called parity check matrix) is used to define the valid code words. The parity check matrix is hereinafter labeled matrix H and a codeword is labeled V. If the multiplication of the parity check matrix H and the codeword V is a zero vector, it means that the codeword V is a valid codeword (valid code word), according to the following equation (1). Where the operator represents a matrix multiplication modulo 2(mod 2). In other words, the null space (null space) of the matrix H contains all valid codewords. However, the invention does not limit the content of the codeword V. For example, the codeword V may also include an error correction code or an error check code generated by any algorithm.
Figure BDA0001087634940000141
Where the dimension of matrix H is k-times-n (k-by-n) and the dimension of codeword V is 1-times-n. k and n are positive integers. The codeword V includes information bits and parity bits, i.e. the codeword V can be represented as [ U P ], where the vector U is composed of information bits and the vector P is composed of parity bits. The dimension of vector U is 1-times- (n-k) and the dimension of vector P is 1-times-k. In a codeword, parity bits are used to protect information bits and can be considered as an error correction code or an error check code generated corresponding to the information bits. Here, protecting the information bits means, for example, maintaining the accuracy of the information bits. For example, when a piece of data is read from the rewritable nonvolatile memory module 406, the parity bits in the data can be used to correct the error that may exist in the corresponding data.
In an exemplary embodiment, the information bits and parity bits in a codeword are collectively referred to as data bits. For example, there are n data bits in the codeword V, where the information bits are (n-k) bits in length and the parity bits are k bits in length. Therefore, the code rate of the codeword V is (n-k)/n.
In general, a generating matrix (hereinafter, denoted as G) is used when encoding using the low density parity check code, so that the following equation (2) can be satisfied for an arbitrary vector U. Where the dimension that yields the matrix G is (n-k) -times-n.
Figure BDA0001087634940000151
The codeword V generated by equation (2) is a valid codeword. Equation (2) can therefore be substituted into equation (1), thereby yielding equation (3) below.
Figure BDA0001087634940000152
Since the vector U may be an arbitrary vector, the following equation (4) is necessarily satisfied. That is, after the parity check matrix H is determined, the corresponding generation matrix G may also be determined.
Figure BDA0001087634940000153
In decoding a codeword V, a parity check operation is performed on the data bits in the codeword V, for example, the parity check matrix H is multiplied by the codeword V to generate a vector (hereinafter denoted as S, as shown in equation (5) below). If the vector S is a zero vector (i.e., every element in the vector S is zero), it indicates that decoding is successful and the codeword V can be directly output. If the vector S is not a zero vector (i.e., at least one element in the vector S is not zero), it indicates that there is at least one error in the codeword V and that the codeword V is not a valid codeword.
Figure BDA0001087634940000154
The dimension of the vector S is k-times-1. Each element in the vector S is also referred to as a syndrome. If the codeword V is not a valid codeword, the ECC circuit 508 performs a decoding operation to attempt to correct the error in the codeword V.
FIG. 6 is a diagram illustrating a parity check matrix according to an exemplary embodiment of the present invention.
Referring to FIG. 6, the parity check matrix 600 has dimensions of k-by-n. For example, k is 8 and n is 9. However, the present invention does not limit what the positive integers k and n are. Each column (row) of parity check matrix 600 also represents a constraint. Taking the first column of the parity check matrix 600 as an example, if a codeword is a valid codeword, the modulo-2 addition is performed on the 3 rd, 5 th, 8 th and 9 th bits in the codeword, and then a bit "0" is obtained. Those skilled in the art will understand how to encode the parity check matrix 600, and will not be described in detail here. In addition, the parity check matrix 600 is only an exemplary matrix and is not intended to limit the present invention.
When memory management circuitry 502 is to store a plurality of bits to rewritable non-volatile memory module 406, error checking and correction circuitry 508 generates k parity bits corresponding to every (n-k) bits to be stored (i.e., information bits). Next, memory management circuitry 502 writes the n bits (i.e., data bits) as a codeword to rewritable non-volatile memory module 406.
FIG. 7 is a graph illustrating threshold voltage distributions of memory cells according to an exemplary embodiment of the present invention.
Referring to fig. 7, the horizontal axis represents the threshold voltage of the memory cells, and the vertical axis represents the number of the memory cells. For example, FIG. 7 shows the distribution of threshold voltages of each memory cell in a physical program cell. Assuming that state 710 corresponds to a bit "1" and state 720 corresponds to a bit "0", if the threshold voltage of a memory cell belongs to state 710, the memory cell stores a bit "1"; conversely, if the threshold voltage of a memory cell belongs to state 720, the memory cell stores a bit "0". It is noted that, in the present exemplary embodiment, one state in the threshold voltage distribution corresponds to one bit value (i.e., "0" or "1"), and the threshold voltage distribution of the memory cell has two possible states. However, in other exemplary embodiments, each state in the threshold voltage distribution may correspond to a plurality of bit values and the distribution of the threshold voltages of the memory cells may have four, eight or any other states. In addition, the present invention does not limit the bits represented by each state. For example, in another exemplary embodiment of FIG. 7, state 710 may also correspond to bit "0" and state 720 corresponds to bit "1".
In the exemplary embodiment, when data is to be read from rewritable non-volatile memory module 406, memory management circuit 502 sends a read command sequence to rewritable non-volatile memory module 406. The read command sequence is used to instruct the rewritable non-volatile memory module 406 to read data (hereinafter also referred to as first data) from a plurality of memory cells (hereinafter also referred to as first memory cells). In the exemplary embodiment, the first memory cells belong to the same physical programming cell. However, in another exemplary embodiment, the first memory cell may belong to a different physical programming cell. According to this read command sequence, the rewritable non-volatile memory module 406 can read the first memory cell using the read voltage 701 in fig. 7. If the threshold voltage of one of the first memory cells is less than the read voltage 701, the memory cell is turned on and the memory management circuit 502 reads the bit "1". Conversely, if the threshold voltage of one of the first memory cells is greater than the read voltage 701, the memory cell will not be turned on and the memory management circuit 502 will read the bit "0".
In the exemplary embodiment, states 710 and 720 include an overlap region 730. The area of the overlap region 730 is positively correlated to the total number of memory cells in the first memory cell whose threshold voltages fall within the overlap region 730. Overlap region 730 indicates that some of the first memory cells should store a bit of "1" (belonging to state 710), but have a threshold voltage greater than applied read voltage 701; alternatively, some of the first memory cells should store a bit of "0" (belonging to state 720), but have a threshold voltage less than the applied read voltage 701. In other words, some bits of the data read by applying the read voltage 701 may have errors.
Generally, if the first memory cell has a short lifetime (e.g., the first memory cell has a short data storage time) and/or the first memory cell has a low lifetime (e.g., the first memory cell has a low read count, write count, and/or erase count), the area of the overlap region 730 is typically small, and even the overlap region 730 may not exist (i.e., the states 710 and 720 do not overlap). Alternatively, if the memory storage device 10 is shipped from the factory, the overlap region 730 does not normally exist. If the area of the overlap region 730 is small, the number of error bits in the data read from the first memory cell by applying the read voltage 701 is often small.
However, as the usage time and/or usage degree of the rewritable non-volatile memory module 406 (or the first memory cell) increases, the area of the overlap region 730 gradually increases. For example, if the first memory cell has a long lifetime (e.g., data is stored in the first memory cell for a long time) and/or the first memory cell has a high lifetime (e.g., the first memory cell has a high read count, write count, and/or erase count), the area of the overlap region 730 may be increased (e.g., the states 710 and 720 may change to flat and/or the states 710 and 720 may be closer to each other). If the area of the overlap region 730 is large, the number of error bits in the data read from the first memory cell by applying the read voltage 701 tends to be large. In other words, the area of the overlap region 730 is positively correlated to the probability of an erroneous bit in the data read from the first memory cell.
In the exemplary embodiment, after receiving the read first data from the rewritable non-volatile memory module 406, the error checking and correcting circuit 508 performs a parity check operation to verify whether there is an error in the first data. If it is determined that there is an error in the first data, the error checking and correcting circuit 508 performs a decoding operation to attempt to correct the error in the first data.
In the exemplary embodiment, the error checking and correcting circuit 508 performs an iterative (iteration) decoding operation. An iterative decoding operation is used to decode a decode unit from the rewritable non-volatile memory module 406. For example, one decoding unit is one codeword. In an iterative decoding operation, a parity check operation for checking the correctness of data and a decoding operation for correcting errors in the data are repeatedly performed until a successful decoding or a total number of iterations reaches a predetermined number. If the total number of iterations reaches the predetermined number, the entire iterative decoding operation for the data fails, and the error checking and correcting circuit 508 stops decoding. In addition, if it is determined by the parity check operation that there is no error in a certain data, the error check and correction circuit 508 outputs the data.
In the exemplary embodiment, the error checking and correcting circuit 508 may perform a plurality of decoding operations on the first data based on different decoding conditions. It should be noted that the strictness (strict level) used by the error checking and correcting circuit 508 to locate the error bit in the first data may be different based on different decoding conditions. For example, in some cases, the error checking and correcting circuit 508 performs at least one of the iterative decoding operations based on the decoding condition that locates the error bits with higher stringency (i.e., stricter). Moreover, in some cases, the error checking and correcting circuit 508 may instead perform at least one of the same iterative decoding operations based on less stringent (i.e., more relaxed) decoding conditions that locate the erroneous bits.
In this exemplary embodiment, the higher precision of positioning the error bits means that the judgment and screening of the error bits in the first data are more strict, so that one or more bits in the first data are less likely to be judged as error bits. Conversely, less stringent positioning of erroneous bits means that the erroneous bits in the first data are more loosely determined and filtered, so that one or more bits in the first data are more easily determined to be erroneous bits. In other words, there is a higher probability of flipping more bits for performing a decoding operation on a codeword based on a decoding condition with less strict positioning of erroneous bits, but the probability of flipping to a bit that does not need to be flipped (i.e., false flipping) is also increased; conversely, performing a decoding operation on the codeword based on a decoding condition with a higher stringency for locating erroneous bits has a higher probability of flipping fewer bits, but also reduces the probability of flipping to bits that do not need to be flipped. It should be noted that flipping a bit as referred to herein means changing the bit value of the bit, for example, changing the bit value of a bit from "1" to "0" or from "0" to "1".
In the exemplary embodiment, the error checking and correcting circuit 508 is configured with a plurality of stages (stages), wherein each stage corresponds to a decoding condition. In the same iterative decoding operation for the first data, the error checking and correction circuitry 508 may switch in such stages. In addition, at each stage, the error checking and correction circuitry 508 may perform one or more decoding operations.
Fig. 8 is a diagram illustrating switching phases in an iterative decoding operation according to an exemplary embodiment of the present invention. Referring to FIG. 8, assume that there are phases 0-15 for the error checking and correcting circuit 508, where phase 0 is the phase where the error bits are located with the highest (i.e., most stringent) stringency, and phase 15 is the phase where the error bits are located with the lowest (i.e., most relaxed) stringency. In the phase 0 to the phase 15, the stringency of the positioning error bits gradually decreases. For example, the stringency at phase 0 is higher than the stringency at phase 1, the stringency at phase 1 is higher than the stringency at phase 2, and the stringency at phase 14 is higher than the stringency at phase 15.
In the exemplary embodiment, if the ECC circuit 508 is currently operating in stage 0 (i.e., performing the decoding operation based on the decoding condition of stage 0) and it is determined that the decoding condition needs to be switched, the ECC circuit 508 switches to stage 1. If the error checking and correcting circuit 508 is currently operating in stage 1 (i.e., performing a decoding operation based on the decoding conditions of stage 1) and it is determined that it is necessary to switch the decoding conditions, the error checking and correcting circuit 508 switches to stage 2. By analogy, the error checking and correcting circuit 508 may switch from stage 0 to stage 15 one by one in the same iterative decoding operation on the first data until one of the decoding operations is successful or the total number of iterations reaches a predetermined number. It should be noted that during the switching from phase 0 to phase 15, the error checking and correcting circuit 508 is more and more loose in positioning the error bits in the data to be decoded, so that the total number of error bits flipped in each decoding operation may gradually increase. However, this also means that the total number of bits that are "flipped" in each decoding operation may also gradually increase.
In some cases, if there are too many bits that are "flipped" in a decoding operation, it may cause multiple decoding operations that are performed consecutively to remain in a state of error divergence. In the error divergence state, even if more decoding operations are performed, the total number of error bits in the data may not be reduced or may be in a condition of oscillation up and down, thereby eventually causing the entire iterative decoding operation to fail (e.g., the total number of iterations reaches a predetermined number). Therefore, in the exemplary embodiment, the error checking and correcting circuit 508 can return to one of the stages 0 to 14 from the stage 15. By increasing the rigor of the positioning error bit in the decoding operation again, the executed decoding operation has high probability of being out of the error divergence state, and the subsequent decoding success rate is increased. In addition, there is a higher probability of flipping to true error bits by increasing the stringency of locating error bits in the decoding operation than the conventional method of using noise interference (i.e., randomly changing one or more bit values of the data to be decoded) or the like to try to get out of the error divergence state.
Returning to FIG. 8, if the error checking and correcting circuit 508 is currently operating in stage 15 (i.e., performing the decoding operation based on the decoding conditions of stage 15) and it is determined that the decoding conditions need to be switched, the error checking and correcting circuit 508 switches back to one of stages 0-14, thereby increasing the precision of positioning the error bits in the next decoding operation. After switching back from phase 15 to the more stringent phase, error checking and correction circuit 508 may continue to switch to phase 15 unless one of the decoding operations performed therebetween is successful or the total number of iterations reaches a predetermined number. Furthermore, if the error checking and correcting circuit 508 switches back from stage 15 to the existing stage multiple times during the same iterative decoding operation, the stage that is switched back each time may be different. Taking fig. 8 as an example, if the previous switching from phase 15 to the existing phase is back to phase 7 (marked as "1" in fig. 8), the next switching from phase 15 to the existing phase may be back to phase 9 (marked as "2" in fig. 8).
It should be noted that the stages 0 to 15 in fig. 8 are only an example. In other exemplary embodiments not mentioned, the total number of stages in which the error checking and correction circuitry 508 may operate may be more or less. In addition, the error checking and correcting circuit 508 may also skip one or more stages in a single switch, for example, switch directly from stage 0 to stage 2, and so on.
Specifically, it is assumed that the error checking and correcting circuit 508 currently performs a certain decoding operation (hereinafter also referred to as a first decoding operation) on the first data based on a certain decoding condition (hereinafter also referred to as a first decoding condition). If the first decoding operation fails, the memory management circuit 502 determines whether the first decoding operation conforms to a predetermined state (hereinafter also referred to as a first predetermined state). If the first decoding operation meets the first predetermined condition, the error checking and correcting circuit 508 performs another decoding operation (hereinafter also referred to as a second decoding operation) on the first data based on another decoding condition (hereinafter also referred to as a second decoding condition), wherein the rigor of locating the error bits in the first data based on the second decoding condition is higher than the rigor of locating the error bits in the first data based on the first decoding condition.
The memory management circuit 502 determines whether the first decoding operation matches another predetermined state (hereinafter also referred to as a second predetermined state). If the first decoding operation meets the second predetermined condition, the error checking and correcting circuit 508 performs another decoding operation (hereinafter also referred to as a third decoding operation) on the first data based on another decoding condition (hereinafter also referred to as a third decoding condition), wherein the rigor of locating the error bits in the first data based on the third decoding condition is lower than the rigor of locating the error bits in the first data based on the first decoding condition. If the first decoding operation does not satisfy the first predetermined state or the second predetermined state, the error checking and correcting circuit 508 performs the first decoding operation on the first data again based on the first decoding condition.
Fig. 9A is a diagram illustrating a handover phase according to an example embodiment of the invention. Referring to FIG. 9A, assume that the error checking and correcting circuit 508 is currently operating at stage n (i.e., the first decoding condition). If the first decoding operation at stage n fails and the stop condition of the entire iterative decoding operation has not been reached (e.g., the total number of iterations reaches a predetermined number), the memory management circuit 502 determines whether the first decoding condition meets a stage condition. For example, memory management circuitry 502 may determine whether phase n is the least stringent phase for locating erroneous bits (e.g., phase 15 in FIG. 8). If phase n is not the least stringent phase for locating the erroneous bits (e.g., phase n may be any of phase 0-phase 14 in FIG. 8), memory management circuit 502 determines that the first decoding condition does not satisfy the phase condition. In addition, the memory management circuit 502 determines whether the total number of bits flipped by the first decoding operation meets a number condition. For example, if the total number of bits flipped by the first decoding operation is zero (i.e., none of the bits is flipped in the first decoding operation), the memory management circuit 502 determines that the total number of bits flipped by the first decoding operation meets the number condition. Conversely, if the total number of bits flipped by the first decoding operation is not zero (i.e., at least one bit is flipped in the first decoding operation), the memory management circuit 502 determines that the total number of bits flipped by the first decoding operation does not meet the number condition. If the first decoding condition does not satisfy the stage condition and the total number of bits flipped by the first decoding operation satisfies the number condition, the error checking and correcting circuit 508 switches to operate at stage n +1 (i.e., the third decoding condition).
In other words, in the exemplary embodiment, since no bit is flipped in the previous decoding operation (i.e., the first decoding operation) and a decoding condition with lower stringency is available, the error checking and correcting circuit 508 reduces the stringency for locating the error bit in the next decoding operation (i.e., the third decoding operation), thereby increasing the probability that at least one bit in the data to be decoded is flipped.
Fig. 9B is a diagram illustrating a handover phase according to another example embodiment of the present invention. Referring to FIG. 9B, assume that the error checking and correcting circuit 508 is currently operating at stage m (i.e., the first decoding condition). If the first decoding operation at stage m fails and the stop condition of the entire iterative decoding operation has not been reached, the memory management circuit 502 determines whether the first decoding condition meets the stage condition. Since phase m is already the least stringent phase for locating the erroneous bits (e.g., phase 15 in fig. 8), memory management circuitry 502 may determine that the first decoding condition meets the phase condition. After determining that the first decoding condition meets the phase condition, the memory management circuit 502 counts an iteration count of the first decoding operation, wherein the iteration count indicates that the first decoding operation at phase m has been repeatedly (iterative) performed several times. Then, the memory management circuit 502 determines whether the iteration count value meets a count condition. If the iteration count does not satisfy the counting condition, the error checking and correcting circuit 508 continues to perform the first decoding operation at stage m. If the iteration count value meets the count condition, e.g., the iteration count value reaches 10 times, the error checking and correcting circuit 508 switches back to the more stringent stage p (i.e., the second decoding condition) for locating the error bits.
In other words, in the exemplary embodiment, the first decoding operation at stage m has been performed repeatedly many times (e.g., 10 times) and still fails to decode the first data successfully, which means that there is a high probability that the first data is repeatedly flipped to too many bits that do not need to be flipped. Therefore, the error checking and correcting circuit 508 increases the rigor of locating the error bits in the next decoding operation (i.e., the second decoding operation), thereby reducing the probability of the error bits being flipped. In addition, after operating at stage p, the error checking and correcting circuit 508 may be sequentially operated at stage p +1 and so on, as in the example embodiment of fig. 9A, which will not be described herein.
Fig. 9C is a diagram illustrating a handover phase according to another example embodiment of the present invention. Referring to fig. 9C, continuing with the example embodiment of fig. 9B, if the error checking and correcting circuit 508 is operated again at stage m, the decoding operation currently operated at stage m (i.e., the first decoding operation) fails, and the stop condition of the entire iterative decoding operation has not been reached, the memory management circuit 502 determines again that the first decoding operation meets the stage condition and counts the iteration count value of the first decoding operation. For example, the iteration count value indicates that the first decoding operation at stage m is performed a total of several times after returning from stage p to stage m again. Then, the memory management circuit 502 determines whether the iteration count value meets a count condition. For example, the memory management circuit 502 determines whether the iteration count corresponding to the first decoding operation at stage m is equal to 7. If the iteration count does not meet the count condition (e.g., the iteration count is less than 7), the error checking and correcting circuit 508 repeats the first decoding operation at stage m. If the iteration count value meets the count condition, e.g., the iteration count value reaches 7, the error checking and correcting circuit 508 switches back to the more stringent phase q where the erroneous bits are located (i.e., the new second decoding condition). After operating at stage q, the error checking and correcting circuit 508 may be subsequently operated at stage q +1, and so on, as in the example embodiment of FIG. 9A, which will not be described herein.
It is noted that in the exemplary embodiments of FIGS. 9B and 9C, the counting conditions for determining whether to return to the current phase p (or q) or to continue to remain at phase m are different. For example, in the same iterative decoding operation for the first data, the memory management circuit 502 may select a count condition corresponding to a different count value from a plurality of candidate count conditions as a basis for determining to return to the existing stage. For example, in an example embodiment of fig. 9B, the memory management circuit 502 may select a candidate counting condition (hereinafter also referred to as a first candidate counting condition) from a plurality of candidate counting conditions as a currently used counting condition, wherein the first candidate counting condition corresponds to a first counting value (e.g., 10). Then, in the example embodiment of fig. 9C, the memory management circuit 502 instead selects another candidate counting condition (hereinafter also referred to as a second candidate counting condition) from the candidate counting conditions as the currently used counting condition, wherein the second candidate counting condition corresponds to a second counting value (e.g., 7). By reducing the count value of the count condition used in sequence, the execution efficiency of the entire iterative decoding operation can be improved. However, in another exemplary embodiment, the counting condition used may also be constant in the same iterative decoding operation for the first data.
In the exemplary embodiment of fig. 9B and 9C, phase p is different from phase q (i.e., p is not equal to q), wherein the stringency of phase p for positioning error bits is higher than the stringency of phase q for positioning error bits. For example, in the same iterative decoding operation for the first data, the memory management circuit 502 may select an appropriate decoding condition from a plurality of candidate decoding conditions as the second decoding condition. For example, in an example embodiment of fig. 9B, the memory management circuit 502 may select one candidate decoding condition (hereinafter also referred to as a first candidate decoding condition) from a plurality of candidate decoding conditions as the second decoding condition to be used, which corresponds to the phase p. Then, in the example embodiment of fig. 9C, the memory management circuit 502 instead selects another candidate decoding condition (hereinafter also referred to as a second candidate decoding condition) from the candidate decoding conditions as a second decoding condition to be used, which corresponds to the phase q. By changing the second decoding condition from stage p to stage q, the efficiency of performing the entire iterative decoding operation can also be improved. However, in another exemplary embodiment, the error checking and correcting circuit 508 may always switch from phase m to the same phase (e.g., phase p or phase q) in the same iterative decoding operation for the first data, rather than a different phase.
FIG. 10 is a diagram illustrating a parity check operation according to an exemplary embodiment of the present invention. Referring to fig. 10, assuming that the first data read from the first memory cell includes a codeword 1001, the parity check matrix 1000 is multiplied by the codeword 1001 according to equation (5) to obtain a check vector 1002 (i.e., vector S) in the parity check operation. Where each bit in codeword 1001 corresponds to at least one element (i.e., syndrome) in check vector 1002. For example, bit V0 in codeword 1001 (corresponding to the first row in parity check matrix 1000) corresponds to syndromes S1, S4, and S7; bit V1 (corresponding to the second row in parity-check matrix 1000) corresponds to syndromes S2, S3, and S6, and so on. If bit V0 is an erroneous bit, at least one of the syndromes S1, S4, and S7 may be "1". If bit V1 is an error bit, at least one of syndromes S2, S3, and S6 may be "1", and so on. In other words, if the syndromes S0-S7 are all "0", it indicates that there may be no error in the codeword 1001, so the error checking and correcting circuit 508 can directly output the codeword 1001. However, if there is an error in codeword 801, at least one of syndromes S0-S7 may be "1", and error checking and correcting circuit 508 performs a decoding operation on codeword 1001.
In the exemplary embodiment, the error checking and correcting circuit 508 performs the decoding operation using a Bit-Flipping (Bit-Flipping) algorithm, so that the error checking and correcting circuit 508 identifies the bits of the first data that need to be flipped (i.e., the error bits) based on a Flipping threshold, wherein each stage (or decoding condition) corresponds to a Flipping threshold. For example, in the exemplary embodiment of fig. 8, the threshold value of the phase 0 is the largest, the threshold value of the phase 15 is the smallest, and the threshold values of the phases 0 to 15 are gradually decreased. However, in another exemplary embodiment, the error checking and correcting circuit 508 may perform the decoding operation using a decoding algorithm such as a Min-Sum (Min-Sum) algorithm or a Sum-Product (Sum-Product) algorithm.
In the exemplary embodiment, the error checking and correcting circuit 508 calculates the error weight of each bit in the codeword 1001 according to the parity check matrix 1000 and the check vector 1002. For example, the ECC circuit 508 adds the syndromes corresponding to the same bit in the codeword 1001 to obtain the error weight of the bit. For example, E0-E8 are used to represent the error weights of bits V0-V8, respectively, where the error weight E0 of bit V0 is equal to the sum of syndromes S1, S4, and S7; the error weight E1 of bit V1 is equal to the sum of syndromes S2, S3, and S6, and so on. It should be noted that the addition of syndromes S0-S7 is a general addition, not a modulo-2 addition. For example, the error checking and correcting circuit 508 may obtain the error weight of each bit in the codeword 1001 by the following equation (6), wherein each element in the vector f may be used to represent the error weight of each bit in the codeword.
f＝ST×H…(6)
After obtaining the error weights, the error checking and correcting circuit 508 flips all or at least a portion of the bits in the codeword 1001 for which the error weights are greater than the flipping threshold used. Therefore, by switching the phase (or decoding condition), the threshold value of the flip-flop used by the ECC 508 to identify the error bit is also adjusted, so that whether the ECC 508 locates the error bit strictly or loosely in a decoding operation can be determined.
In an exemplary embodiment, the error checking and correcting circuit 508 defines the error weight of each bit in the first data by the following equation (7), wherein equation (7) is also called a cost function (cost function).
EWi＝αAi+βBi…(7)
In equation (7), EWi represents the error weight of the ith bit (i.e., bit Vi) in the first data, Ai equals Ei in the example embodiment of fig. 10, and the value of Bi is set corresponding to whether the current value of bit Vi is equal to its initial value, for example, assuming that the initial value of bit Vi is "1", if bit Vi is changed to "0" after at least one decoding operation, the value of Bi is set to "1" to indicate that the current value of bit Vi is different from its initial value, whereas if bit Vi is still "1" after at least one decoding operation, the value of Bi is set to "0" to indicate that the current value of bit Vi is equal to its initial value, α and β are both constant.
In an exemplary embodiment, after obtaining the syndrome vector of the first data, the ECC circuit 508 obtains a syndrome sum of the first data. Taking FIG. 10 as an example, the ECC circuit 508 accumulates the syndromes S0-S7 to obtain a syndrome sum corresponding to the codeword 1001. For example, if there are k "1" S0-S7, the syndrome total of codeword 1001 is k. The ECC circuit 508 determines whether the syndrome sum is smaller than a predetermined value. If the syndrome sum is smaller than the predetermined value, the error checking and correcting circuit 508 decreases the error weight value of each bit in the first data, for example, from the first error weight value to the second error weight value. After reducing the error weight value of each bit in the first data, the next decoding operation may be performed. For example, in a next decoding operation (e.g., a first decoding operation), if the reduced error weight value (i.e., the second error weight value) of a bit is greater than the inversion threshold corresponding to the first decoding condition used, the error checking and correcting circuit 508 inverts the bit in the first decoding operation. However, if the statistical syndrome sum is not less than the predetermined value, the error checking and correcting circuit 508 does not actively reduce the error weight value of each bit in the first data.
In an exemplary embodiment, if the syndrome sum of the first data is determined to be less than the predetermined value, the error checking and correcting circuit 508 calculates the error weight of each bit of the first data by using the following equation (8). The value of the calculated error weight can be reduced using equation (8) compared to using equation (7).
EWi＝αAi…(8)
It should be noted that although the above exemplary embodiments all use the bit flipping algorithm as an example, in other embodiments not mentioned, the error checking and correcting circuit 508 may also use a decoding algorithm such as a min-sum algorithm or a sum-product algorithm to perform the decoding operation. Those skilled in the art should know which parameters need to be adjusted to adjust the stringency for positioning the error bits in various decoding algorithms, and will not be described herein.
Fig. 11 is a flowchart illustrating a decoding method according to an exemplary embodiment of the present invention. Referring to fig. 11, in step S1101, first data is read from a plurality of first memory cells of a rewritable non-volatile memory module. In step S1102, a first decoding operation is performed on the first data based on a first decoding condition. It should be noted that the present invention does not limit the first decoding operation to be the second decoding operation performed after the first data is read, as long as the first decoding operation belongs to the same iterative decoding operation for the first data. In step S1103, it is determined whether the first decoding operation conforms to a first preset state. If the first decoding operation meets the first predetermined condition, in step S1104, a second decoding operation is performed on the first data based on a second decoding condition, wherein the rigor of positioning the error bits in the first data based on the second decoding condition is higher than the rigor of positioning the error bits in the first data based on the first decoding condition. If the first decoding operation does not conform to the first predetermined state, in step S1105, it is determined whether the first decoding operation conforms to the second predetermined state. If the first decoding operation meets the second predetermined condition, in step S1106, a third decoding operation is performed on the first data based on a third decoding condition, wherein the stringency for locating the error bits in the first data based on the third decoding condition is lower than the stringency for locating the error bits in the first data based on the first decoding condition. If the first decoding operation does not conform to the first predetermined state or the second predetermined state, after step S1105, step S1102 may be repeated. It should be noted that in the decoding method of fig. 11, the entire iterative decoding operation is stopped as long as a stop condition of the entire iterative decoding operation is reached (for example, the decoding is successful or the total number of iterations reaches a predetermined number).
Fig. 12 is a flowchart illustrating a decoding method according to another exemplary embodiment of the present invention. Referring to fig. 12, in step S1201, first data is read from a plurality of first memory cells of a rewritable nonvolatile memory module. In step S1202, a parity check operation is performed on the first data to obtain a syndrome total of the first data. In step S1203, it is determined whether the syndrome total is smaller than a preset value. If the syndrome summation is smaller than the predetermined value, in step S1204, the error weight value of each bit in the first data is reduced from the first error weight value to the second error weight value. In step S1205, a decoding operation is performed on the first data based on a decoding condition. For example, the decoding condition at this time is the first decoding condition. In addition, if the syndrome total is not less than the preset value, the process also proceeds to step S1205 after step S1203. In step S1206, it is determined whether the decoding operation conforms to a first preset state. If the decoding operation meets the first predetermined condition, in step S1207, the decoding condition is updated to a second decoding condition, wherein the stringency for locating the error bits in the first data based on the second decoding condition is higher than the stringency for locating the error bits in the first data based on the first decoding condition. If the decoding operation does not conform to the first predetermined state, in step S1208, it is determined whether the decoding operation conforms to the second predetermined state. If the decoding operation meets the second predetermined condition, in step S1209, the decoding condition is updated to a third decoding condition, wherein the stringency for positioning the error bits in the first data based on the third decoding condition is lower than the stringency for positioning the error bits in the first data based on the first decoding condition. If the decoding operation does not conform to the first predetermined state or the second predetermined state, after step S1208, step S1202 may be repeated. In addition, after steps S1207 and S1209, step S1202 may be repeated. It should be noted that in the decoding method of fig. 12, the entire iterative decoding operation is stopped as long as a stop condition of the entire iterative decoding operation is reached (for example, the decoding is successful or the total number of iterations reaches a predetermined number).
However, the steps in fig. 11 and fig. 12 have been described in detail above, and are not repeated herein. It is to be noted that, the steps in fig. 11 and fig. 12 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the methods of fig. 11 and fig. 12 can be used with the above exemplary embodiments, or can be used alone, and the invention is not limited thereto.
In summary, the present invention can flexibly adjust the stringency of error bit positioning in the iterative decoding operation. In addition, the decoding efficiency of the memory storage device can be improved through the set switching rule.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (21)

1. A decoding method for a rewritable non-volatile memory module including a plurality of memory cells, the decoding method comprising:
reading first data from a plurality of first memory cells of the plurality of memory cells;
performing a first decoding operation on the first data based on a first decoding condition; and
if the first decoding operation meets a first preset state, executing a second decoding operation on the first data based on a second decoding condition,
wherein a stringency of locating erroneous bits in the first data based on the second decoding condition is higher than a stringency of locating the erroneous bits in the first data based on the first decoding condition,
wherein a probability of flipping the number of bits in the first decoding operation being performed on the first data based on the first decoding condition locating the stringency of the erroneous bits in the first data is higher than a probability of flipping the number of bits in the second decoding operation being performed based on the second decoding condition locating the stringency of the erroneous bits in the first data.
2. The decoding method according to claim 1, further comprising:
if the first decoding operation meets a second preset state, a third decoding operation is executed on the first data based on a third decoding condition,
wherein a stringency of locating the erroneous bits in the first data based on the third decoding condition is lower than the stringency of locating the erroneous bits in the first data based on the first decoding condition.
3. The decoding method according to claim 2, further comprising:
counting an iteration count value of the first decoding operation if the first decoding condition meets a stage condition; and
and if the iteration count value meets the counting condition, judging that the first decoding operation meets the first preset state.
4. The decoding method according to claim 3, further comprising:
and if the first decoding condition does not meet the stage condition and the total number of the bits turned over by the first decoding operation meets the number condition, judging that the first decoding operation meets the second preset state.
5. The decoding method according to claim 3, further comprising:
selecting the counting condition from a first candidate counting condition and a second candidate counting condition,
wherein the first candidate counting condition corresponds to a first count value, the second candidate counting condition corresponds to a second count value, and the first count value is different from the second count value.
6. The decoding method according to claim 1, further comprising:
selecting the second decoding condition from the first candidate decoding condition and the second candidate decoding condition,
wherein a stringency of locating an erroneous bit in data based on the first candidate decoding condition is higher than a stringency of locating the erroneous bit in the data based on the second candidate decoding condition.
7. The decoding method according to claim 1, further comprising:
performing a parity check operation on the first data to obtain a syndrome sum of the first data;
if the syndrome summation is smaller than a preset value, reducing the error weight value of the bit in the first data from a first error weight value to a second error weight value; and
flipping the bit in the first decoding operation if the second error weight value is greater than a flipping threshold corresponding to the first decoding condition.
8. A memory storage device, comprising:
a connection interface unit for connecting to a host system;
a rewritable non-volatile memory module including a plurality of memory cells; and
a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,
the memory control circuit unit is used for sending a reading instruction sequence, wherein the reading instruction sequence indicates that first data is read from a plurality of first storage units in the plurality of storage units,
the memory control circuitry unit is also to perform a first decoding operation on the first data based on a first decoding condition,
the memory control circuit unit is further configured to perform a second decoding operation on the first data based on a second decoding condition if the first decoding operation satisfies a first predetermined state,
wherein a stringency of locating erroneous bits in the first data based on the second decoding condition is higher than a stringency of locating the erroneous bits in the first data based on the first decoding condition,
wherein a probability of flipping the number of bits in the first decoding operation being performed on the first data based on the first decoding condition locating the stringency of the erroneous bits in the first data is higher than a probability of flipping the number of bits in the second decoding operation being performed based on the second decoding condition locating the stringency of the erroneous bits in the first data.
9. The memory storage device of claim 8, wherein the memory control circuit unit is further configured to perform a third decoding operation on the first data based on a third decoding condition if the first decoding operation satisfies a second predetermined state,
wherein a stringency of locating the erroneous bits in the first data based on the third decoding condition is lower than the stringency of locating the erroneous bits in the first data based on the first decoding condition.
10. The memory storage device of claim 9, wherein the memory control circuit unit is further configured to count an iteration count value of the first decoding operation if the first decoding condition satisfies a phase condition,
if the iteration count value meets a counting condition, the memory control circuit unit judges that the first decoding operation meets the first preset state.
11. The memory storage device of claim 10, wherein the memory control circuit unit determines that the first decoding operation satisfies the second predetermined state if the first decoding condition does not satisfy the phase condition and the total number of bits flipped by the first decoding operation satisfies a number condition.
12. The memory storage device of claim 10, wherein the memory control circuit unit is further configured to select the count condition from a first candidate count condition and a second candidate count condition,
wherein the first candidate counting condition corresponds to a first count value, the second candidate counting condition corresponds to a second count value, and the first count value is different from the second count value.
13. The memory storage device of claim 8, wherein the memory control circuit unit is further configured to select the second decoding condition from a first candidate decoding condition and a second candidate decoding condition,
wherein a stringency of locating an erroneous bit in data based on the first candidate decoding condition is higher than a stringency of locating the erroneous bit in the data based on the second candidate decoding condition.
14. The memory storage device of claim 8, wherein the memory control circuitry unit is further to perform a parity check operation on the first data to obtain a syndrome sum of the first data,
if the syndrome summation is smaller than a predetermined value, the memory control circuit unit is further configured to reduce an error weight value of a bit in the first data from a first error weight value to a second error weight value,
the memory control circuit unit is further configured to flip the bit in the first decoding operation if the second error weight value is greater than a flip threshold corresponding to the first decoding condition.
15. A memory control circuit unit for controlling a rewritable nonvolatile memory module including a plurality of memory cells, the memory control circuit unit comprising:
a host interface for connecting to a host system;
a memory interface to connect to the rewritable non-volatile memory module;
an error checking and correcting circuit; and
memory management circuitry connected to the host interface, the memory interface, and the error checking and correcting circuitry,
the memory management circuit is configured to send a read instruction sequence, wherein the read instruction sequence indicates to read first data from a plurality of first memory cells of the plurality of memory cells,
the error checking and correcting circuit is configured to perform a first decoding operation on the first data based on a first decoding condition,
the error checking and correcting circuit is further configured to perform a second decoding operation on the first data based on a second decoding condition if the first decoding operation satisfies a first predetermined condition,
wherein the error checking and correcting circuit locates erroneous bits in the first data based on the second decoding condition to be more stringent than the error checking and correcting circuit locates the erroneous bits in the first data based on the first decoding condition,
wherein a probability of flipping the number of bits in the first decoding operation being performed on the first data based on the first decoding condition locating the stringency of the erroneous bits in the first data is higher than a probability of flipping the number of bits in the second decoding operation being performed based on the second decoding condition locating the stringency of the erroneous bits in the first data.
16. The memory control circuit unit of claim 15, wherein the error checking and correcting circuit is further configured to perform a third decoding operation on the first data based on a third decoding condition if the first decoding operation satisfies a second predetermined condition,
wherein the error checking and correcting circuit locates the erroneous bits in the first data based on the third decoding condition less stringent than the error checking and correcting circuit locates the erroneous bits in the first data based on the first decoding condition.
17. The memory control circuit unit of claim 16, wherein the memory management circuit is further configured to count an iteration count value of the first decoding operation if the first decoding condition satisfies a phase condition,
if the iteration count value meets a counting condition, the memory management circuit judges that the first decoding operation meets the first preset state.
18. The memory control circuit unit of claim 17, wherein the memory management circuit determines that the first decoding operation satisfies the second predetermined state if the first decoding condition does not satisfy the phase condition and a total number of bits flipped by the first decoding operation satisfies a number condition.
19. The memory control circuit unit of claim 17, wherein the memory management circuit is further configured to select the count condition from a first candidate count condition and a second candidate count condition,
wherein the first candidate counting condition corresponds to a first count value, the second candidate counting condition corresponds to a second count value, and the first count value is different from the second count value.
20. The memory control circuit unit of claim 15, wherein the memory management circuit is further configured to select the second decoding condition from a first candidate decoding condition and a second candidate decoding condition,
wherein the error checking and correcting circuit locates erroneous bits in the data based on the first candidate decoding condition with a higher stringency than the error checking and correcting circuit locates the erroneous bits in the data based on the second candidate decoding condition.
21. The memory control circuit unit of claim 15, wherein the error checking and correction circuit is further configured to perform a parity check operation on the first data to obtain a syndrome sum of the first data,
if the syndrome summation is less than a predetermined value, the error checking and correcting circuit is further configured to reduce an error weight value of a bit in the first data from a first error weight value to a second error weight value,
the error checking and correcting circuit is further configured to flip the bit in the first decoding operation if the second error weight value is greater than a flip threshold corresponding to the first decoding condition.
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