CN106650006B - Debugging method and system of programmable logic device and electronic design automation terminal - Google Patents
Debugging method and system of programmable logic device and electronic design automation terminal Download PDFInfo
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Abstract
The embodiment of the invention provides a debugging method and a debugging system of a programmable logic device and an electronic design automation terminal. In the above scheme, the electronic design automation terminal can not only perform corresponding electronic design automation debugging on the debugged programmable logic device, but also take into account the protocol analysis function of the protocol analyzer, so that a professional protocol analyzer is not required to be purchased for debugging the debugged programmable logic device, the hardware cost of debugging is reduced, meanwhile, in the process of debugging the debugged programmable logic device, a debugging person only needs to pay attention to the electronic design automation terminal, and does not need to monitor a computer and the protocol analyzer simultaneously like the prior art, thereby simplifying the debugging process.
Description
Technical Field
The invention relates to the field of communication, in particular to a debugging method and a debugging system of a programmable logic device and an electronic design automation terminal.
Background
Programmable Logic Devices (PLDs) have Programmable characteristics, so in the design stage, designers can modify circuits as needed until the design is satisfied, which effectively reduces the cost, shortens the cycle of system design, and improves the flexibility of design and development. Meanwhile, the programmable logic device also has higher integration level, so that the programmable logic device is applied in the fields of communication, image processing and the like in a large scale.
The debugging work of the programmable logic device can be performed based on an EDA (electronic design automation) debugging program operated by a computer and other terminals. If the protocol contained in the programmable logic device is simple, the signal in the programmable logic device can be directly collected, the corresponding waveform is displayed, the waveform of a complete data packet is obtained from the displayed waveform in a form of human eye observation, and then the waveform of the data packet is analyzed, so that the debugging of the programmable logic device is realized. However, when a programmable logic device including a complex protocol design is debugged, it is difficult to acquire a data packet waveform through observation of human eyes, and the process is also complicated, and in this case, a protocol analyzer (protocol analyzer) is usually used to analyze data acquired from the inside of the programmable logic device. A protocol analyzer is a special test tool that monitors data streams in a data communication system and checks whether data exchange is correctly performed according to the specifications of a protocol. The protocol analyzer is connected to a data communication system, and can acquire data transmitted by the system and received data from a line under the condition of not influencing the operation of the system, store, display and analyze the data, and realize the monitoring function of the protocol analyzer. Meanwhile, the protocol analyzer also has a simulation function, and when the protocol analyzer is directly connected with the tested equipment (such as a programmable logic device), the protocol analyzer communicates with the tested equipment according to a preset program to perform data sending, data receiving judgment and data response judgment, and check the correctness of the protocol implementation of the tested equipment.
Although the protocol analyzer can perform protocol analysis on a programmable logic device with complicated protocol design, if the protocol analyzer is used to assist debugging, a special protocol analyzer must be purchased, which increases the hardware cost of debugging. In summary, a scheme for debugging a programmable logic device is continuously provided to solve the problem of high cost of debugging hardware in the prior art.
Disclosure of Invention
The debugging method, the debugging system and the electronic design automation terminal of the programmable logic device provided by the embodiment of the invention mainly solve the technical problems that: the method solves the problem that a professional protocol analyzer is required to be purchased when the protocol of the programmable logic device is analyzed in the prior debugging process, so that the hardware cost for debugging the programmable logic device is high.
To solve the foregoing technical problem, an embodiment of the present invention provides a method for debugging a programmable logic device, including:
the electronic design automation terminal captures data to be analyzed of an input/output port of a debugged programmable logic device, and is used for performing a terminal corresponding to electronic design automation debugging on the debugged programmable logic device;
and the electronic design automation terminal performs protocol analysis on the data to be analyzed so as to debug the debugged programmable logic device.
Further, the electronic design automation terminal captures the data to be analyzed of the input/output port through a standard interface or a custom interface defined by a protocol on the debugged programmable logic device.
Further, before capturing the data to be analyzed of the input/output port of the debugged programmable logic device, the electronic design automation terminal includes: and the electronic design automation terminal determines the capture time for capturing the data to be analyzed.
Further, the capturing, by the electronic design automation terminal, data to be analyzed of the input/output port of the debugged programmable logic device includes:
the electronic design automation terminal captures data to be analyzed of an input/output port of a debugged programmable logic device and stores the data to be analyzed to an internal memory of the debugged programmable logic device;
the electronic design automation terminal receives the data to be analyzed transmitted from the internal memory.
Further, the capturing, by the electronic design automation terminal, data to be analyzed of the input/output port of the debugged programmable logic device includes:
the electronic design automation terminal captures data to be analyzed of an input/output port of a debugged programmable logic device and stores the data to be analyzed to an internal memory of the debugged programmable logic device;
the electronic design automation terminal controls the debugged programmable logic device to transmit the data to be analyzed on the internal memory to an off-chip memory;
and the electronic design automation terminal receives the data to be analyzed sent by the off-chip memory.
An embodiment of the present invention further provides an electronic design automation terminal, including:
the electronic design automation terminal is used for carrying out a terminal corresponding to electronic design automation debugging on the debugged programmable logic device;
and the analysis debugging module is used for carrying out protocol analysis on the data to be analyzed so as to debug the debugged programmable logic device.
Further, the data transmission module is configured to capture data to be analyzed at an input/output port of the debugged programmable logic device, store the data to be analyzed in an internal memory of the debugged programmable logic device, and receive the data to be analyzed transmitted from the internal memory.
Further, the data transmission module is configured to capture data to be analyzed at an input/output port of the debugged programmable logic device, store the data to be analyzed in an internal memory of the debugged programmable logic device, control the debugged programmable logic device to transmit the data to be analyzed in the internal memory to an off-chip memory, and receive the data to be analyzed transmitted from the internal memory.
The embodiment of the invention also provides a debugging system of the programmable logic device, which comprises the debugged programmable logic device and the electronic design automation terminal.
Further, the partial memory is a static random access memory inside the debugged programmable logic device; the off-chip memory is a dynamic random access memory outside the debugged programmable logic device.
An embodiment of the present invention further provides a computer storage medium, where a computer-executable instruction is stored in the computer storage medium, and the computer-executable instruction is used to execute the debugging method of any one of the foregoing programmable logic devices.
The invention has the beneficial effects that:
according to the debugging method and system for the programmable logic device, the electronic design automation terminal and the computer storage medium provided by the embodiment of the invention, the terminal for performing corresponding electronic design automation debugging on the debugged programmable logic device captures the data to be analyzed from the input/output port of the debugged programmable logic device, and performs protocol analysis on the data to be analyzed, so as to realize debugging on the debugged programmable logic device. In the scheme provided by the embodiment of the invention, the electronic design automation terminal not only carries out corresponding electronic design automation debugging on the debugged programmable logic device, but also can consider the protocol analysis function of the protocol analyzer, so that a professional protocol analyzer is not required to be purchased for the debugging work of the debugged programmable logic device, the hardware cost of debugging is reduced, meanwhile, in the process of debugging the debugged programmable logic device, a debugging person only needs to pay attention to the electronic design automation terminal, and the computer and the protocol analyzer do not need to be simultaneously monitored like the prior art, and the debugging process is simplified.
Drawings
Fig. 1 is a flowchart of a debugging method of a programmable logic device according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an EDA terminal debugging a debugged PLD according to various embodiments of the present invention;
fig. 3 is another schematic diagram of the EDA terminal debugging a debugged PLD according to various embodiments of the present invention;
fig. 4 is a schematic structural diagram of an EDA terminal according to a second embodiment of the present invention;
fig. 5 is another schematic structural diagram of an EDA terminal according to a second embodiment of the present invention;
fig. 6 is a schematic structural diagram of a debugging system of a programmable logic device according to a third embodiment of the present invention;
fig. 7 is a schematic diagram of a debugging system of a programmable logic device according to a third embodiment of the present invention.
Detailed Description
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
The first embodiment is as follows:
unlike a general digital chip, the PLD has internal digital circuits that can be programmed and determined after leaving the factory, some PLDs cannot be changed again after being reprogrammed and some circuits inside the PLD device support multiple programming and erasing. PLDs are classified into PROM (Programmable Read-Only Memory), EPROM (erasable Programmable Read-Only Memory), PLA (Programmable Logic Array), PAL (Programmable Array Logic), GAL (general Array Logic), and the like. In addition, based on PAL and GAL, CPLDs (Complex Programmable Logic devices) and FPGAs (Field-Programmable Gate arrays) with wider applications have been developed.
In the prior art, when a PLD device is debugged, a computer is basically used to run an EDA program corresponding to the debugged PLD device to perform electronic design automation debugging. When the protocol analysis is needed, a professional protocol analyzer may be connected to the PLD to be debugged, capture data of the input/output port of the PLD to be debugged, obtain a complete data packet from the captured data, analyze the data packet, and determine a protocol header and a packet tail of the data packet, so as to know behaviors of the PLD to be debugged and a data packet used by the outside during generation and transmission, and assist in performing the debugging operation. However, in this debugging scheme, a professional protocol analyzer is used, which not only increases the hardware cost of PLD debugging, but also makes the work of debugging the PLD more complicated, increasing the burden on the debugging staff. In order to solve the above problems, the present embodiment provides a debugging method of a programmable logic device, please refer to fig. 1:
s102, capturing data to be analyzed of the input/output port of the debugged PLD by the EDA terminal.
In this embodiment, the EDA terminal (i.e., an electronic design automation terminal) refers to a terminal capable of running an EDA program corresponding to a debugged PLD, and performing electronic design automation debugging on the debugged PLD, and in an actual debugging process, the EDA terminal is a computer capable of running the EDA program, and includes a notebook computer, a desktop computer, and the like.
When the EDA terminal captures the data to be analyzed of the input/output port of the debugged PLD, the data to be analyzed of the input/output port of the debugged PLD can be captured through the user-defined interface and stored in the internal memory of the debugged PLD. Of course, it will be understood by those skilled in the art that EDA terminals may also be captured via standard interfaces defined by the protocol. As shown in fig. 2, the PLD to be debugged is a Field Programmable Gate Array (FPGA)21, which is disposed on a PCB board 22. The EDA terminal 20, as an external terminal for debugging the field programmable gate array 21 to be debugged, may be connected to the field programmable gate array 21, capture data to be analyzed through a PIPE (PHY Interface for the PCI Express) Interface 211 of the field programmable gate array 21 standard, and store the data to be analyzed in the internal memory 212 of the field programmable gate array 21. When the capture operation is completed, the EDA terminal may receive the data to be analyzed transmitted from the internal memory 212. Of course, it will be understood by those skilled in the art that the EAD terminal may also capture the data to be analyzed, and receive the data to be analyzed transmitted by the debugged PLD.
It should be understood that "capture" in this embodiment is a process of collecting data to be analyzed, and therefore "capture" is not limited to the scope of this embodiment, and any words that characterize the data collection process can be used instead of "capture" in this embodiment. For example, instead of "capture", the words "capture", "grab", "capture", etc. may be used. Before capturing the data to be analyzed, the EDA terminal may further set a capture duration for capturing the data to be analyzed and a condition for starting capturing, and since a transmission rate of the custom interface or the standard interface for capturing the data to be analyzed by the EDA terminal is substantially determined, a size of capturing the data to be analyzed by the EDA terminal may be determined by a duration of capturing. In an example of this embodiment, the EDA terminal sets a capture duration before capturing the data to be analyzed, and the capture duration should generally ensure that the data to be analyzed captured by the EDA terminal includes at least one complete data packet. The capture duration can be set by a debugger in the EDA program in a self-defined manner, and of course, if the EDA terminal captures data to be analyzed of the PLD to be debugged by using the standard interface, the capture duration default in the EDA program may be used.
In this embodiment, the internal memory of the PLD to be debugged may include, but is not limited to, an SRAM (Static RAM), such as the debugged field programmable gate array 21 shown in fig. 2, where the internal memory 212 is an SRAM. Besides SRAM, if there is DRAM (Dynamic RAM) in the PLD to be debugged, DRAM can also be used as an internal memory of the debugged PLD.
Although the amount of data to be analyzed captured by the EDA terminal is directly limited by the capture duration, the amount of data to be analyzed is fundamentally limited by the storage capacity of the internal memory of the PLD to be debugged. Since the data captured by the EDA terminal needs to be stored in its internal memory, but the internal memory needs to store other resources of the PLD being debugged, in addition to serving the debug job. Therefore, generally speaking, the space for the internal memory of the PLD to be debugged to store the data to be analyzed in the debugging process is not very large. The limited storage space, when the existing protocol analyzer captures data under the control of the debugging computer, too much data cannot be captured at one time, which is also an important factor in the prior art that limits the free and flexible debugging of the PLD.
Therefore, in an example of the present embodiment, the FPGA debugging scheme illustrated in fig. 3 is based on the scheme illustrated in fig. 2, and an off-chip memory 23 is extended for the field programmable gate array 21 to be debugged. The EDA terminal 20 may first store the data to be analyzed in the internal memory 212 when capturing the data, and then control to transfer the data to be analyzed in the internal memory 212 to the off-chip memory 23 when the storage space in the internal memory 212 is insufficient. Since the off-chip memory 23 of the debugged fpga 21 is disposed on the PCB 22, the disposing space thereof is significantly larger than that of the internal memory 212, and further, the storage capacity of the off-chip memory 23 can be much larger than that of the internal memory 212. In this embodiment, the EDA terminal receives the data to be analyzed sent by the off-chip memory 23.
And S104, performing protocol analysis on the data to be analyzed by the EDA terminal to debug the debugged PLD.
After the captured data to be analyzed is transmitted to the EDA terminal, the EDA terminal may perform protocol analysis on the data to be analyzed, for example, in this embodiment, the EDA terminal may obtain a complete data packet from the data to be analyzed, then analyze the data packet, obtain a data packet header and a data packet trailer, determine a process of generating and transmitting the data packet, obtain a protocol analysis result, and thereby determine whether input and output of the PLD to be debugged are performed normally according to a design of a protocol.
In the debugging method of the programmable logic device provided in the embodiment of the present invention, the EDA terminal that performs the corresponding electronic design automation debugging on the debugged PLD captures the data to be analyzed from the input/output port of the debugged PLD, and then performs the protocol analysis on the captured data to be analyzed, so that the electronic design automation debugging of the debugged PLD is completed through the EDA terminal, and the protocol analysis on the data to be analyzed is realized by using the EDA terminal, so that a professional protocol analyzer is not required to be purchased for the debugging work of the debugged programmable logic device, the hardware cost of debugging is reduced, and the debugging process of a debugger is simplified.
On the other hand, in the embodiment of the present invention, the EDA terminal may further control to transfer captured data to be analyzed from the internal memory of the PLD to be debugged to the off-chip memory, and then obtain the data to be analyzed from the off-chip memory for protocol analysis, so that the amount of captured data to be analyzed and the capture duration are not limited by the internal storage resource of the PLD to be debugged by using the advantage of a large storage space of the off-chip memory, and the capture of the data to be analyzed can be performed freely according to the actual debugging requirement, thereby improving the flexibility of the debugging process to a great extent.
Example two:
in the prior art, when a PLD device is debugged, a computer is basically used to run an EDA program corresponding to the debugged PLD device to perform electronic design automation debugging. When the protocol analysis is needed, a professional protocol analyzer may be connected to the PLD to be debugged, capture data of the input/output port of the PLD to be debugged, obtain a complete data packet from the captured data, analyze the data packet, and determine a protocol header and a packet tail of the data packet, so as to know behaviors of the PLD to be debugged and a data packet used by the outside during generation and transmission, and assist in performing the debugging operation. However, in this debugging scheme, a professional protocol analyzer is used, which not only increases the hardware cost of PLD debugging, but also makes the work of debugging the PLD more complicated, increasing the burden on the debugging staff. In order to solve the above problem, the present embodiment provides an EDA terminal, which can execute the method for debugging a programmable logic device provided in the first embodiment, specifically, please refer to fig. 4:
In this embodiment, the EDA terminal 20 (i.e., an electronic design automation terminal) refers to a terminal capable of running an EDA program corresponding to a debugged PLD and performing electronic design automation debugging on the debugged PLD, and in an actual debugging process, the EDA terminal 20 is a computer capable of running the EDA program, and includes a notebook computer, a desktop computer, and the like.
When the data capture module 202 captures data to be analyzed at the input/output port of the PLD to be debugged, the data to be analyzed at the input/output port of the PLD to be debugged can be captured through the custom interface and stored in the internal memory of the PLD to be debugged. Of course, it will be understood by those skilled in the art that the data capture module 202 may also capture data via a standard interface defined by a protocol. As shown in fig. 2, the PLD to be debugged is a Field Programmable Gate Array (FPGA)21, which is disposed on a PCB board 22. The EDA terminal 20, as an external terminal for debugging the field programmable gate array 21 to be debugged, may be connected to the field programmable gate array 21, capture data to be analyzed through a PIPE (PHY Interface for the pci express, external device interconnect bus physical layer Interface) Interface 211 of the field programmable gate array 21 standard, and store the data to be analyzed in an internal memory 212 of the field programmable gate array 21. After the data to be analyzed is captured in the internal memory 212, the data capture module 202 may receive the data to be analyzed transmitted from the internal memory 212. Of course, it will be understood by those skilled in the art that the data capture module 202 may also capture the data to be analyzed while receiving the data to be analyzed transmitted from the internal memory of the PLD being debugged.
It should be understood that "capture" in this embodiment is a process of collecting data to be analyzed, and therefore "capture" is not limited to the scope of this embodiment, and any words that characterize the data collection process can be used instead of "capture" in this embodiment. For example, instead of "capture", the words "capture", "grab", "capture", etc. may be used. In an example of the embodiment, as shown in fig. 5, the EDA terminal 20 further includes a duration determination module 206, the duration determination module 206 is configured to set a duration of capturing the data to be analyzed before the data capturing module 202 captures the data to be analyzed, and since the transmission rate of the custom interface or the standard interface of the data capturing module 202 for capturing the data to be analyzed is substantially determined, the amount of capturing the data to be analyzed by the data capturing module 202 can be determined by the duration of capturing. In an example of the embodiment, the duration determination module 206 further sets a capture duration before the data capture module 202 captures the data to be analyzed, wherein the capture duration generally ensures that the data to be analyzed captured by the EDA terminal includes at least one complete data packet. The capture duration set by the duration determination module 206 may be set according to a user-defined setting of a debugger in the EDA program, and of course, if the data capture module 202 captures data to be analyzed of the PLD to be debugged using a standard interface, the duration determination module 206 may use a default duration in the EDA program as the capture duration.
In this embodiment, the internal memory of the PLD to be debugged may include, but is not limited to, an SRAM (Static RAM), such as the debugged field programmable gate array 21 shown in fig. 2, where the internal memory 212 is an SRAM. Besides SRAM, if there is DRAM (Dynamic RAM) in the PLD to be debugged, DRAM can also be used as an internal memory of the debugged PLD.
Although the amount of data to be analyzed captured by the data capture module 202 is directly limited by the capture duration, the amount of data to be analyzed is fundamentally limited by the internal memory storage capacity of the debugged PLD. Because the data captured by the data capture module 202 needs to be stored in its internal memory, the internal memory needs to store other resources of the PLD being debugged, in addition to serving the debug job. Therefore, generally speaking, the space for the internal memory of the PLD to be debugged to store the data to be analyzed in the debugging process is not very large. The limited storage space, the existing protocol analyzer cannot capture too much data in one data capture process, which is an important factor in the prior art that limits the free and flexible debugging of the PLD.
Therefore, in an example of the present embodiment, the FPGA debugging scheme illustrated in fig. 3 is based on the scheme illustrated in fig. 2, and an off-chip memory 23 is extended for the field programmable gate array 21 to be debugged. When the data capture module 202 captures data, the data to be analyzed may be stored in the internal memory 212, and when the storage space of the internal memory 212 is insufficient, the data capture module 202 controls to transfer the data to be analyzed in the internal memory 212 to the off-chip memory 23. Since the off-chip memory 23 of the debugged fpga 21 is disposed on the PCB 22, the disposing space thereof is significantly larger than that of the internal memory 212, and further, the storage capacity of the off-chip memory 23 can be much larger than that of the internal memory 212. After the analysis data is stored in the off-chip memory 23, the data capture module 202 may receive the data to be analyzed sent by the off-chip memory 23 for performing protocol analysis, so as to implement debugging on the debugged PLD.
After the data to be analyzed is captured by the data capture module 202, the analysis and debugging module 204 of the EDA terminal 20 may perform protocol analysis on the data to be analyzed, for example, in this embodiment, the analysis and debugging module 204 may obtain a complete data packet from the data to be analyzed, then analyze the data packet, obtain a header and a trailer of the data packet, determine a process of generating and transmitting the data packet, obtain a protocol analysis result, and thereby determine whether the input and output of the PLD to be debugged are performed normally according to the design of the protocol.
The functions of the duration determining module and the analyzing and debugging module in the EDA terminal of this embodiment may be completed by the controller, and the function of the data capturing module may be jointly implemented by the terminal controller and the communication device: the controller sets capture duration for capturing data to be analyzed according to instructions of debugging personnel, then sends the instructions to capture the data to be analyzed to the debugged PLD through the communication device, and after the data to be analyzed is obtained, protocol analysis can be carried out on the data to be analyzed, so that debugging of the debugged PLD is realized.
In the EDA terminal provided in the embodiment of the present invention, the EDA terminal that performs the corresponding electronic design automation debugging on the debugged PLD captures the data to be analyzed from the input/output port of the debugged PLD, and then performs the protocol analysis on the captured data to be analyzed, so that the electronic design automation debugging of the debugged PLD is completed through the EDA terminal, and the protocol analysis on the data to be analyzed is realized by using the EDA terminal, so that a professional protocol analyzer is not required to be purchased for the debugging work of the debugged programmable logic device, the hardware cost of the debugging is reduced, and the debugging process of a debugger is simplified.
On the other hand, in the embodiment of the present invention, the EDA terminal may further control to transfer captured data to be analyzed from the internal memory of the PLD to be debugged to the off-chip memory, and then obtain the data to be analyzed from the off-chip memory for protocol analysis, so that the amount of captured data to be analyzed and the capture duration are not limited by the internal storage resource of the PLD to be debugged by using the advantage of a large storage space of the off-chip memory, and the capture of the data to be analyzed can be performed freely according to the actual debugging requirement, thereby improving the flexibility of the debugging process to a great extent.
Example three:
the present embodiment provides a debugging system of a programmable logic device, and as shown in fig. 6, the debugging system 6 of a programmable logic device includes a debugged Programmable Logic Device (PLD)60 and EDA terminals 20 provided in the second embodiment.
As shown in fig. 7, in the debug system 6 of the debugged programmable logic device, the EDA terminal is a computer 62, and the computer 62 captures data to be analyzed of the I/O interface through a standard data interface 601 of the debugged programmable logic device 60 and stores the data to be analyzed on an internal memory 602.
In addition, the debugging system 6 of the debugged programmable logic device further includes an off-chip memory 61, the off-chip memory 61 and the debugged programmable logic device 60 are disposed on the PCB 63, and the internal memory 601 of the debugged programmable logic device 60, the off-chip memory 61 and the computer 62 are connected in a two-to-two communication manner. When the amount of data to be analyzed captured by the computer 62 is large, that is, the capturing time is long, the computer 62 may control to transfer the data to be analyzed stored in the internal memory 602 to the off-chip memory 61, and then obtain the data to be analyzed from the off-chip memory 61. When the amount of data to be analyzed captured by the computer 62 is small, i.e., the capturing time is short, the captured data to be analyzed can be directly transmitted from the internal memory 602 to the computer 62.
Of course, it is understood by those skilled in the art that in the above example, it is not necessary to ensure that the internal memory 601, the off-chip memory 61 and the computer 62 are in a two-by-two communication connection state at any time, and the specific connection status may be determined according to the capture duration set by the computer 62, when the capture duration is shorter, only the internal memory 601 and the computer 62 are connected, and when the capture duration is longer, the internal memory 601 and the off-chip memory 61 are connected, and the off-chip memory 61 and the computer 62 are connected.
Finally, since the electronic design automation debugging of the debugged PLD is realized by running the corresponding EDA program, an EDA terminal capable of running a computer program is required for both the existing debugging scheme and the debugging scheme in this embodiment. In this embodiment, the protocol analysis of the data to be analyzed of the debugged PLD may be implemented by running the corresponding protocol analysis program, so that the debugged PLD may be debugged by directly running the protocol analysis program corresponding to the debugged PLD using the EDA terminal. In terms of the actual debugging process, a professional protocol analyzer is not required to be purchased, and the cost for debugging the PLD is reduced.
It will be apparent to those skilled in the art that the modules or steps of the embodiments of the invention described above may be implemented in a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented in program code executable by a computing device, such that they may be stored on a computer storage medium (ROM/RAM, magnetic disk, optical disk) and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
The foregoing is a more detailed description of embodiments of the present invention, and the present invention is not to be considered limited to such descriptions. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A method for debugging a programmable logic device, comprising:
the electronic design automation terminal captures data to be analyzed of an input/output port of a debugged programmable logic device, and is used for performing a terminal corresponding to electronic design automation debugging on the debugged programmable logic device;
the protocol analysis of the data to be analyzed by the electronic design automation terminal is performed to realize the debugging of the debugged programmable logic device, and the protocol analysis of the data to be analyzed by the electronic design automation terminal is performed to realize the debugging of the debugged programmable logic device comprises the following steps: and the electronic design automation terminal obtains a complete data packet from the data to be analyzed, analyzes the data packet, obtains a data packet header and a data packet tail, determines the generation and transmission processes of the data packet, and obtains a protocol analysis result, thereby determining whether the input and output of the debugged programmable logic device are normally performed according to the design of a protocol.
2. The debugging method of the programmable logic device according to claim 1, wherein the electronic design automation terminal captures the data to be analyzed of the input/output port through a standard interface or a custom interface defined by a protocol on the debugged programmable logic device.
3. The debugging method of the programmable logic device of claim 1, wherein the capturing of the data to be analyzed of the input/output port of the debugged programmable logic device by the electronic design automation terminal comprises: and the electronic design automation terminal determines the capture time for capturing the data to be analyzed.
4. A debugging method for a programmable logic device according to any one of claims 1-3, wherein the capturing of data to be analyzed of the input/output port of the debugged programmable logic device by the electronic design automation terminal comprises:
the electronic design automation terminal captures data to be analyzed of an input/output port of a debugged programmable logic device and stores the data to be analyzed to an internal memory of the debugged programmable logic device;
the electronic design automation terminal receives the data to be analyzed transmitted from the internal memory.
5. A debugging method for a programmable logic device according to any one of claims 1-3, wherein the capturing of data to be analyzed of the input/output port of the debugged programmable logic device by the electronic design automation terminal comprises:
the electronic design automation terminal captures data to be analyzed of an input/output port of a debugged programmable logic device and stores the data to be analyzed to an internal memory of the debugged programmable logic device;
the electronic design automation terminal controls the debugged programmable logic device to transmit the data to be analyzed on the internal memory to an off-chip memory;
and the electronic design automation terminal receives the data to be analyzed sent by the off-chip memory.
6. An electronic design automation terminal, comprising:
the electronic design automation terminal is used for carrying out a terminal corresponding to electronic design automation debugging on the debugged programmable logic device;
the analysis and debugging module is used for performing protocol analysis on the data to be analyzed so as to debug the debugged programmable logic device, and the protocol analysis performed on the data to be analyzed by the electronic design automation terminal so as to debug the debugged programmable logic device comprises: and the electronic design automation terminal obtains a complete data packet from the data to be analyzed, analyzes the data packet, obtains a data packet header and a data packet tail, determines the generation and transmission processes of the data packet, and obtains a protocol analysis result, thereby determining whether the input and output of the debugged programmable logic device are normally performed according to the design of a protocol.
7. The electronic design automation terminal of claim 6, wherein the data transmission module is configured to capture data to be analyzed at an input/output port of a debugged programmable logic device, store the data to be analyzed in an internal memory of the debugged programmable logic device, and receive the data to be analyzed transmitted from the internal memory.
8. The electronic design automation terminal of claim 6, wherein the data transmission module is configured to capture data to be analyzed at an input/output port of a debugged programmable logic device and store the data to be analyzed in an internal memory of the debugged programmable logic device, and control the debugged programmable logic device to transmit the data to be analyzed on the internal memory to an off-chip memory, and receive the data to be analyzed transmitted from the internal memory.
9. A debugging system for a programmable logic device, comprising a debugged programmable logic device and an electronic design automation terminal according to any one of claims 6 to 8.
10. The debugging system of claim 9 wherein,
the data transmission module is used for capturing data to be analyzed of an input/output port of the debugged programmable logic device, storing the data to be analyzed to an internal memory of the debugged programmable logic device, and receiving the data to be analyzed transmitted from the internal memory;
the data transmission module is used for capturing data to be analyzed of an input/output port of the debugged programmable logic device, storing the data to be analyzed into an internal memory of the debugged programmable logic device, controlling the debugged programmable logic device to transmit the data to be analyzed on the internal memory to an off-chip memory, and receiving the data to be analyzed transmitted from the internal memory;
the internal memory is a static random access memory inside the debugged programmable logic device; the off-chip memory is a dynamic random access memory outside the debugged programmable logic device.
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