CN106648443B

CN106648443B - Valid data merging method, Memory Controller and memory storage apparatus

Info

Publication number: CN106648443B
Application number: CN201510719657.8A
Authority: CN
Inventors: 颜鸿圣
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2015-10-30
Filing date: 2015-10-30
Publication date: 2019-06-25
Anticipated expiration: 2035-10-30
Also published as: CN106648443A

Abstract

The present invention proposes a kind of valid data merging method, Memory Controller and memory storage apparatus.This method includes: that the physics erasing unit in data field is at least grouped to one first group and one second group, the sorting table for wherein recording the particular aspects data in the physics erasing unit of the first group is not stored in reproducible nonvolatile memorizer module, and the sorting table of the particular aspects data in the physics erasing unit of the second group of record has been stored in reproducible nonvolatile memorizer module；One first physics is selected to wipe unit from the second group；And the first physics is wiped into the valid data in unit and is copied to one second physics erasing unit, wherein the valid data do not include the particular aspects data in the first physics erasing unit.The present invention uses the storage that sorting table is reduced when executing valid data consolidation procedure, to solve the problems, such as continually to store sorting table in valid data consolidation procedure.

Description

Valid data merging method, Memory Controller and memory storage apparatus

Technical field

The invention relates to a kind of for the valid data merging method of type nonvolatile, memory Controller and memory storage apparatus.

Background technique

Digital camera, mobile phone and MP3 are very rapid in growth over the years, so that demand of the consumer to storage media Also rapidly increase.Since type nonvolatile (rewritable non-volatile memory) has data Non-volatile, power saving, it is small in size, without the characteristics such as mechanical structure, read or write speed be fast, be most suitable for portable electronic product, such as pen Remember this computer.Solid state hard disk is exactly a kind of memory storage apparatus using flash memory as storage media.Therefore, in recent years fastly Flash memory industry becomes a ring quite popular in electronic industry.

Flash memory module wipes unit with multiple physics and each physics erasing unit is programmed with multiple physics Unit must be sequentially written in data according to physical programming unit when wherein data are written in physics erasing unit.In addition, Be written into data physical programming unit need to first be wiped free of after can just be re-used for write-in data.In particular, physics wipes unit For the minimum unit of erasing, and physical programming unit is the minimum unit of programming (being also referred to as written).Therefore, in flash memory In the management of module, physics erasing unit can be divided into data field and idle area.

The physics erasing unit of data field is the data stored to host system.Specifically, memory is deposited The logic access address that host system is accessed can be converted to the logic of logical blocks by the memory management circuitry in storage device The page and the physical programming unit that the physics that the logical page (LPAGE) of logical blocks maps to data field is wiped to unit.Namely It says, the physics erasing unit of data field is regarded as the physics having been used erasing unit in the management of flash memory module (for example, data that host system is written).For example, memory management circuitry will use logical address-physical address Mapping table (logical address-physical address mapping table) records logical page (LPAGE) and data field Physical programming unit mapping relations.

The physics erasing unit in idle area is to wipe unit to the physics in alternation data field.Specifically, institute as above State, be written into data physics erasing unit must be wiped free of after can just be re-used for write-in data, therefore, leave unused area object Reason erasing unit is designed to write-in more new data to replace the physics of mapping logic block and wipe unit.Base this, in the spare time Setting the physics erasing unit in area is that physics that is empty or can be used for being written data wipes unit.

In general write operation, the wiping of the physics into idle area can be written in more new data by memory management circuitry Except (also referred to as, actuation physics wipes unit) in unit, and machine in due course, such as host system are in one section of standby time When, memory management circuitry can just be loaded into corresponding logical address-physical address mapping table to carry out logical page (LPAGE) and physics and compile The update of map information between Cheng Danyuan, and this actuation physics erasing unit is associated with to data field.

In particular, the sorting table can be used in recorded data zone in the memory storage apparatus with sorting table A corresponding informance between particular aspects data and logic access address (or logical page (LPAGE)).Specifically, each in data field The physical programming unit of a physics erasing unit can be used for storing the write-in data from host system, and said write data It can be general data or particular aspects data.

It is to be noted that in the above-mentioned memory storage apparatus with sorting table, when the hollow physics in idle area Wiping the number of unit is non-when being greater than pre-defined value, and memory management circuitry can execute valid data consolidation procedure.Specifically For, when the number of the physics erasing unit to leave unused in idle area be it is non-be greater than pre-defined value when, representing can use in idle area It is not enough in the physics erasing unit of write-in.At this point, memory management circuitry can first accordingly deposit the information in sorting table Storage is into reproducible nonvolatile memorizer module.Later, memory management circuitry can select one or more within a data area Physics wipes unit, and one or more selected physics are wiped the physics that the valid data in unit are copied to idle area It wipes in unit.Later, memory management circuitry executes one to the erasing unit of one or more physics selected in data field and wipes It is associated with except operation, and by these physics erasing unit to idle area, and the physics that would sit idle for having in area above-mentioned valid data is wiped Except unit is associated with to data field.

After having executed above-mentioned valid data consolidation procedure, if host system is intended to access the particular aspects data, deposit Reservoir manages circuit and can be looked for from reproducible nonvolatile memorizer module according to the logic access address from host system The word string arrangement mode of the particular aspects data is corresponded to out, and responds the word string arrangement mode of this particular aspects data to host System.The word string arrangement mode of particular aspects data is recorded in sorting table by above-mentioned, can allow particular aspects data not It is wiped in unit with physics is stored in, and then increases the space that can be used for storing other general datas in physics erasing unit.

However, in the above-mentioned memory storage apparatus with sorting table, while executing valid data consolidation procedure, Host system can execute write operation still more new data to be written in the erasing unit of the actuation physics into idle area.Tool For body, while host system executes write operation, memory management circuitry can be by particular aspects all in data field A corresponding informance between data and logic access address (or logical page (LPAGE)) is recorded into sorting table, and is selected from data field One or more physics wipe unit.Then, memory management circuitry can wipe one or more selected physics in unit Valid data are copied to the erasing unit of N number of physics in idle area.Then, memory management circuitry is to selected in data field One or more physics wipe unit and execute erasing operation, and these physics erasing unit is associated with to idle area.Finally, memory N number of physics erasing unit that management circuit can would sit idle for having in area the valid data is associated with to data field, effective to complete Data consolidation procedure.It must be noted that N is the positive integer of a non-zero, N is to represent executing above-mentioned valid data merging journey When sequence, idle Qu Zhongsuo required to which the minimum value of the number of the physics erasing unit of the valid data from data field is written, An additional empty physics erasing unit can to generate after valid data consolidation procedure in idle area.Namely It says, an actuation physics used in the write operation corresponding to host system wipes unit, and memory management circuitry can lead to It crosses and one or more physics selected in data field is wiped into N number of physics wiping that the valid data in unit are written into idle area Except unit, uses and generate an additional empty physics erasing unit after executing above-mentioned valid data consolidation procedure in idle area In, with the number for the physics erasing unit for maintaining idle area hollow.

That is, being represented in valid data consolidation procedure when N is smaller, wiped using physics less in idle area Except valid data of the unit storage from data field are that can produce an additional empty physics erasing unit in idle area.In other words It says, when N is smaller, represents effective in the physics erasing unit for being selected for executing valid data consolidation procedure in data field The number of data (valid data) is fewer, and memory management circuitry replicates the negligible amounts of valid data, for memory pipe It manages for the efficiency of circuit relatively preferably；On the contrary, representing in valid data consolidation procedure when N is bigger, using idle area In more physics erasing unit store the valid data from data field, could generate an additional sky physics wipe unit in In idle area.In other words, when N is bigger, the physics for being selected for executing valid data consolidation procedure in data field is represented The number for wiping the valid data in unit is more, and the quantity that memory management circuitry replicates valid data is more, for storage Device manages relatively poor for the efficiency of circuit.

However, memory management circuitry can be accordingly by institute in sorting table due to when executing valid data merging every time A corresponding informance between some particular aspects data and logic access address (or logical page (LPAGE)) stores non-easily to duplicative In the property lost memory, and when the value of N is smaller, it will cause continually store sorting table instead, and then reduce memory management electricity The problem of efficiency on road.Therefore, how when executing valid data consolidation procedure, the number for reducing storage sorting table is deposited with being promoted Reservoir manages the efficiency of circuit, is the target that those skilled in the art are endeavoured.

Summary of the invention

The present invention provides a kind of valid data merging method, Memory Controller and memory storage apparatus, can have Effect ground reduces the storage number of the sorting table when executing valid data consolidation procedure.

One example of the present invention embodiment proposes a kind of valid data merging method, and it is non-easily that the method is suitable for duplicative The property lost memory module, wherein there are reproducible nonvolatile memorizer module multiple physics to wipe unit, and each physics is wiped Except unit has multiple physical programming units, wherein physics erasing unit is at least partitioned into a data field and an idle area.Institute Stating valid data merging method includes: that the physics erasing unit in data field is at least grouped to one first group and one second group Group, wherein the sorting table for recording the particular aspects data in the physics erasing unit of the first group is not stored in duplicative In non-volatile memory module, and the physics for recording the second group has wiped a sorting table of the particular aspects data in unit It is stored in reproducible nonvolatile memorizer module；One first physics is selected to wipe unit from the second group；By Valid data in one physics erasing unit are copied to the one second physics erasing unit among the physics erasing unit in idle area, And erasing operation is carried out to the first physics erasing unit.

In one example of the present invention embodiment, in above-mentioned the step of selecting the first physics to wipe unit from the second group It include: to judge whether the number of the physics erasing unit of the second group is equal to 0；If the number of the physics erasing unit of the second group When mesh is equal to 0, the sorting table of the particular aspects data in the physics erasing unit for recording the first group is stored to duplicative In non-volatile memory module, and the physics erasing unit in the first group is grouped again to the second group；And if When the number of the physics erasing unit of second group is not equal to 0, one of physics erasing unit is selected to make from the second group Unit is wiped for the first physics.

In one example of the present invention embodiment, in above-mentioned the step of selecting the first physics to wipe unit from the second group It include: the invalid data number for recording each physics erasing unit in the second group；If each physics in the second group The invalid data number for wiping unit is all non-when being greater than a predetermined value, and it is special in the physics erasing unit of the first group to record The sorting table of aspect data is stored into reproducible nonvolatile memorizer module, and the physics in the first group is wiped list Member is grouped again to the second group；And if one of physics among the physics erasing unit in the second group wipes list When the invalid data number of member is greater than the predetermined value, selected from the second group the one of physics erasing unit as First physics wipes unit.

In one example of the present invention embodiment, above-mentioned valid data merging method further include: execute write operation to incite somebody to action The third physics that write-in data are written into physics erasing unit wipes unit；And third physics erasing unit is grouped To the first group.

In one example of the present invention embodiment, the predetermined value is the physical programming unit in each physics erasing unit Number 1/5th.

In one example of the present invention embodiment, each bit of the particular aspects data is zero.

An exemplary embodiment of the invention provides a kind of for controlling the memory of reproducible nonvolatile memorizer module Controller, wherein there are reproducible nonvolatile memorizer module multiple physics to wipe unit, each physics erasing unit tool There are multiple physical programming units, wherein physics erasing unit is at least partitioned into a data field and an idle area.This storage Device controller includes: the host interface for being electrically connected to host system；It is non-volatile to be electrically connected to duplicative The memory interface of memory module；And it is electrically connected to the memory management circuitry of host interface and memory interface.It deposits Reservoir manages circuit being at least grouped the physics erasing unit in data field to one first group and one second group, wherein Recording a sorting table of the particular aspects data in the physics erasing unit of the first group, not to be stored in duplicative non-volatile Property memory module in, and the sorting table of particular aspects data recorded in the physics erasing unit of the second group is stored In reproducible nonvolatile memorizer module.In addition, memory management circuitry is also to selection one the from the second group One physics wipes unit, and the first physics is wiped the valid data in unit and is copied among the physics erasing unit in idle area One second physics wipe unit, and to the first physics erasing unit carry out erasing operation.

In one example of the present invention embodiment, wherein selecting first from the second group in above-mentioned memory management circuitry Physics wipe unit running in, memory management circuitry also to judge the second group physics wipe unit number whether Equal to 0；If the number of the physics erasing unit of the second group is equal to 0, memory management circuitry will record the first group The sorting table of particular aspects data in physics erasing unit is stored into reproducible nonvolatile memorizer module, and by the Physics erasing unit in one group is grouped again to the second group；And if the number of the physics erasing unit of the second group When not equal to 0, memory management circuitry selects one of physics erasing unit to wipe as the first physics from the second group Unit.

In one example of the present invention embodiment, wherein selecting first from the second group in above-mentioned memory management circuitry Physics is wiped in the running of unit, and memory management circuitry records the invalid data of each physics erasing unit in the second group Number；If the invalid data number of each physics erasing unit in the second group is all non-when being greater than a predetermined value, memory Management circuit stores the sorting table of the particular aspects data in the physics erasing unit for recording the first group non-to duplicative In volatile, and the physics erasing unit in the first group is grouped again to the second group；And if The invalid data number of one of physics erasing unit among physics erasing unit in two groups is greater than the predetermined value When, it is single that memory management circuitry selects one of physics erasing unit to wipe as the first physics from the second group Member.

In one example of the present invention embodiment, memory management circuitry is also to execute write operation so that data will be written The third physics being written into physics erasing unit wipes unit, and third physics erasing unit is grouped to first group Group.

One example of the present invention embodiment provides a kind of memory storage apparatus comprising: it is electrically connected to host Connector, reproducible nonvolatile memorizer module and the Memory Controller of system.Type nonvolatile Module wipes unit with multiple physics and each physics erasing unit has multiple physical programming units.Memory Controller electricity Property be connected to connector and reproducible nonvolatile memorizer module, Memory Controller is to wipe the physics in data field Except unit is at least grouped to one first group and one second group, wherein record the first group physics erasing unit in it is special One sorting table of aspect data is not stored in reproducible nonvolatile memorizer module, and records the physics of the second group One sorting table of the particular aspects data in erasing unit has been stored in reproducible nonvolatile memorizer module.This Outside, Memory Controller also wipes unit to select one first physics to wipe unit from the second group, and by the first physics In valid data be copied to idle area physics erasing unit among one second physics erasing unit, and to the first physics wipe Except unit carries out erasing operation.

In one example of the present invention embodiment, wherein selecting the first object from the second group in above-mentioned Memory Controller In the running of reason erasing unit, Memory Controller judges whether the number of the physics erasing unit of the second group is equal to 0；If When the number of the physics erasing unit of second group is equal to 0, the physics for recording the first group is wiped unit by Memory Controller In the sorting tables of particular aspects data store into reproducible nonvolatile memorizer module, and by the object in the first group Reason erasing unit is grouped again to the second group；And if the second group physics erasing unit number be not equal to 0 when, deposit Memory controller selects one of physics erasing unit as the first physics from the second group and wipes unit.

In one example of the present invention embodiment, wherein selecting the first object from the second group in above-mentioned Memory Controller In the running of reason erasing unit, Memory Controller records the invalid data number of each physics erasing unit in the second group Mesh；If the invalid data number of each physics erasing unit in the second group is all non-when being greater than a predetermined value, memory control Device processed stores the sorting table of the particular aspects data in the physics erasing unit for recording the first group non-volatile to duplicative Property memory module in, and by the first group physics erasing unit be grouped again to the second group；And if second group When the invalid data number of one of physics erasing unit among physics erasing unit in group is greater than the predetermined value, deposit Memory controller selects one of physics erasing unit as the first physics from the second group and wipes unit.

In one example of the present invention embodiment, Memory Controller is also write to execute write operation with data will be written The third physics entered into physics erasing unit wipes unit, and third physics erasing unit is grouped to the first group.

Based on above-mentioned, of the invention focuses on, and Memory Controller (or memory management circuitry) will be in data field Physics erasing unit divides into the first group and the second group, wherein recording the special state in the physics erasing unit of the first group One sorting table of sample data is not stored in reproducible nonvolatile memorizer module, and the physics for recording the second group is wiped Except a sorting table of the particular aspects data in unit has been stored in reproducible nonvolatile memorizer module；When holding When row valid data consolidation procedure, Memory Controller (or memory management circuitry) is only selected from the second group for executing The physics of valid data consolidation procedure wipes unit, uses the storage that sorting table is reduced when executing valid data consolidation procedure, To solve the problems, such as continually to store sorting table in valid data consolidation procedure.

To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make Carefully it is described as follows.

Detailed description of the invention

Fig. 1 is host system shown by one example of the present invention embodiment, memory storage apparatus and input/output (I/O) schematic diagram of device；

Fig. 2 is host system shown by another example of the present invention embodiment, memory storage apparatus and I/O device Schematic diagram；

Fig. 3 is the schematic diagram of host system shown by another example of the present invention embodiment and memory storage apparatus；

Fig. 4 is the schematic block diagram of memory storage apparatus shown by one example of the present invention embodiment；

Fig. 5 is the schematic block diagram of the Memory Controller according to shown by an exemplary embodiment；

Fig. 6 and Fig. 7 is the example schematic of the management physics erasing unit according to shown by an exemplary embodiment；

Fig. 8 A~Fig. 9 B is the simplification example for showing data write-in with updating sorting table；

Figure 10 A~Figure 13 B is the simplification example for showing valid data consolidation procedure and storing sorting table；

Figure 14 is the flow chart of the valid data merging method according to shown by an exemplary embodiment.

Description of symbols:

10: memory storage apparatus；

11: host system；

110: system bus；

111: processor；

112: random access memory；

113: read-only memory；

114: data transmission interface；

12:I/O device；

20: motherboard；

201: Portable disk；

202: memory card；

203: solid state hard disk；

204: radio memory storage device；

205: GPS module；

206: network interface card；

207: radio transmitting device；

208: keyboard；

209: screen；

210: loudspeaker；

30: memory storage apparatus；

31: host system；

32:SD card；

33:CF card；

34: embedded storage device；

341: embedded multi-media card；

342: embedded type multi-core piece sealed storage device；

102: connector；

104: Memory Controller；

106: reproducible nonvolatile memorizer module；

202: memory management circuitry；

204: host interface；

206: memory interface；

208: buffer storage；

210: electric power management circuit；

212: error checking and correcting circuit；

410 (0)~410 (N): physics wipes unit；

502: data field；

502a: the first group；

502b: the second group；

504: idle area；

506: system area；

508: replacing area；

LBA (0)~LBA (H): logic unit；

LZ (0)~LZ (M): logic region；

600: logic-sorting table；

SD1~SD3: particular aspects data；

ID1~ID6: general data；

S1401, S1403, S1405, S1407, S1409, S1411, S1413: step.

Specific embodiment

In general, memory storage apparatus (also referred to as, storage system) includes duplicative non-volatile memories Device module and controller (also referred to as, control circuit).Being commonly stored device storage device is used together with host system, so that host System can write data into memory storage apparatus or read from memory storage apparatus data.

Fig. 1 is host system shown by one example of the present invention embodiment, memory storage apparatus and input/output (I/O) schematic diagram of device.Fig. 2 is host system shown by another example of the present invention embodiment, memory storage apparatus And the schematic diagram of I/O device.

Fig. 1 and Fig. 2 are please referred to, host system 11 generally comprises processor 111, random access memory (random Access memory, referred to as: RAM) 112, read-only memory (read only memory, referred to as: ROM) 113 and data transmission Interface 114.Processor 111, random access memory 112, read-only memory 113 and data transmission interface 114 are all electrically connected To system bus (system bus) 110.

In this exemplary embodiment, host system 11 is by 10 electricity of data transmission interface 114 and memory storage apparatus Property connection.For example, host system 11 can be write data into memory storage apparatus 10 by data transmission interface 114 or from depositing Data are read in reservoir storage device 10.In addition, host system 11 is electrically connected by system bus 110 and I/O device 12. For example, output signal can be sent to I/O device 12 by system bus 110 or received from I/O device 12 defeated by host system 11 Enter signal.

In this exemplary embodiment, processor 111, random access memory 112, read-only memory 113 and data transmission Interface 114 may be provided on the motherboard 20 of host system 11.The number of data transmission interface 114 can be one or more.It is logical Data transmission interface 114 is crossed, motherboard 20 can be electrically connected to memory storage apparatus 10 by wired or wireless way.It deposits Reservoir storage device 10 can be for example Portable disk 201, memory card 202, solid state hard disk (Solid State Drive, referred to as: SSD) 203 or radio memory storage device 204.Radio memory storage device 204 can be for example wireless near field communication (Near Field Communication, referred to as: NFC) memory storage apparatus, Wireless Fidelity (WiFi) memory storage dress Set, bluetooth (Bluetooth) memory storage apparatus or low-power consumption bluetooth memory storage apparatus (for example, iBeacon) etc. with Memory storage apparatus based on various wireless communication technique.In addition, motherboard 20 can also be by system bus 110 electrically Be connected to global positioning system (Global Positioning System, referred to as: GPS) module 205, network interface card 206, The various I/O device such as radio transmitting device 207, keyboard 208, screen 209, loudspeaker 210.For example, in an exemplary embodiment, it is main Machine plate 20 can pass through 207 access wireless memory storage apparatus 204 of radio transmitting device.

In an exemplary embodiment, mentioned host system is substantially to cooperate with memory storage apparatus to store The arbitrary system of data.Although host system is explained with computer system, however, this hair in the above-mentioned exemplary embodiment It is bright without being limited thereto.Fig. 3 is the signal of host system shown by another example of the present invention embodiment and memory storage apparatus Figure.Referring to figure 3., in another exemplary embodiment, host system 31 is also possible to digital camera, video camera, communication device, sound The systems such as frequency player, video player or tablet computer, and memory storage apparatus 30 can be its used SD card 32, CF Block the various non-volatile memory storage device such as 33 or embedded storage device 34.Embedded storage device 34 includes embedded Multimedia card (embedded MMC, referred to as: eMMC) 341 and/or embedded type multi-core piece sealed storage device (embedded Multi Chip Package, referred to as: eMCP) 342 etc. all types of memory module is directly electrically connected at host system Embedded storage device on substrate.

Fig. 4 is the schematic block diagram of memory storage apparatus shown by one example of the present invention embodiment.

Referring to figure 4., memory storage apparatus 10 includes that connector 102, Memory Controller 104 and duplicative are non-easily The property lost memory module 106.

In this exemplary embodiment, connector 102 is compatible with Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, referred to as: SATA) standard.However, it is necessary to be appreciated that, the invention is not limited thereto, connector 102 be also possible to meet parallel advanced technology annex (Parallel Advanced Technology Attachment, referred to as: PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, referred to as: IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, referred to as: PCI Express) standard, universal serial bus (Universal Serial Bus, Referred to as: USB) standard, secure digital (Secure Digital, referred to as: SD) interface standard, a ultrahigh speed generation (Ultra High Speed-I, referred to as: UHS-I) interface standard, two generation of ultrahigh speed (Ultra High Speed-II, referred to as: UHS-II) interface mark Quasi-, memory stick (Memory Stick, referred to as: MS) interface standard, multi-chip package (Multi-Chip Package) interface mark Quasi-, multimedia storage card (Multi Media Card, referred to as: MMC) interface standard, built-in multimedia storage card (Embedded Multimedia Card, abbreviation eMMC) interface standard, general flash memory (Universal Flash Storage, referred to as: UFS) interface standard, embedded type multi-core piece encapsulation (embedded Multi Chip Package, referred to as: EMCP) interface standard, compact flash (Compact Flash, referred to as: CF) interface standard, integrated form drive electrical interface (Integrated Device Electronics, referred to as: IDE) standard or other suitable standards.Connector 102 can with deposit Memory controller 104 be encapsulated in a chip or connector 102 be laid in one include Memory Controller 104 core Outside piece.

Memory Controller 104 to execute in the form of hardware multiple logic gates of software form implementation or control refer to It enables, and carries out write-in, the reading of data in reproducible nonvolatile memorizer module 106 according to the instruction of host system 11 It takes and the runnings such as erasing.

Reproducible nonvolatile memorizer module 106 is electrically connected to Memory Controller 104, and to store The data that host system 11 is written.Reproducible nonvolatile memorizer module 106 have physics erasing unit 410 (0)~ 410(N).For example, physics erasing unit 410 (0)~410 (N) can belong to the same memory crystal grain (die) or belong to difference Memory crystal grain.Each physics erasing unit is respectively provided with a plurality of physical programming units, wipes wherein belonging to the same physics Except the physical programming unit of unit can be written independently and simultaneously be wiped.However, it is necessary to be appreciated that, the present invention is unlimited In this, each physics erasing unit is can be by 64 physical programming units, 256 physical programming units or any other a physics Programming unit is formed.

In more detail, physics erasing unit is the minimum unit of erasing.That is, each physics erasing unit contains minimum The storage unit of number being wiped free of together.Physical programming unit is the minimum unit of programming.That is, physical programming unit is write-in The minimum unit of data.Each physical programming unit generally includes data bit area and redundancy ratio special zone.Data bit area includes Data of multiple physics access addresses to store user, and redundancy ratio special zone to storage system data (for example, control Information and error correcting code).It can include 4 in the data bit area of each physical programming unit in this exemplary embodiment Physics access address, and the size of a physics access address is 512 bytes (byte).However, in other exemplary embodiments, It also may include the more or fewer physics access addresses of number in data bit area, the present invention is not intended to limit physics access address Size and number.For example, it is physical blocks that physics, which wipes unit, and physical programming unit is in an exemplary embodiment Physical page or physical sector, but invention is not limited thereto.

In this exemplary embodiment, reproducible nonvolatile memorizer module 106 is multi-level cell memory (Multi Level Cell, referred to as: MLC) NAND type flash memory module be (that is, can store 2 bit datas in a storage unit Flash memory module).However, the invention is not limited thereto, reproducible nonvolatile memorizer module 106 can also be single-order and deposit Storage unit (Single Level Cell, referred to as: SLC) NAND type flash memory module in a storage unit (that is, can deposit Store up the flash memory module of 1 bit data), Complex Order storage unit (Trinary Level Cell, referred to as: TLC) NAND type flash memory module (that is, flash memory module that 3 bit datas can be stored in a storage unit), other Flash memory module or other memory modules with the same characteristics.

Fig. 5 is the schematic block diagram of the Memory Controller according to shown by an exemplary embodiment.

Referring to figure 5., Memory Controller 104 connects including memory management circuitry 202, host interface 204 with memory Mouth 206.

Overall operation of the memory management circuitry 202 to control Memory Controller 104.Specifically, memory pipe Manage circuit 202 have multiple control instructions, and memory storage apparatus 10 operate when, these control instructions can be performed with Carry out the running such as write-in, reading and erasing of data.

In this exemplary embodiment, the control instruction of memory management circuitry 202 is to carry out implementation in a software form.For example, Memory management circuitry 202 has microprocessor unit (not shown) and read-only memory (not shown), and these controls refer to Order is programmed in so far read-only memory.When memory storage apparatus 10 operates, these control instructions can be by microprocessor Unit come execute with carry out the write-in of data, reading and erasing etc. running.

In another exemplary embodiment of the present invention, the control instruction of memory management circuitry 202 can also be in the form of procedure code The specific region of reproducible nonvolatile memorizer module 106 is stored in (for example, being exclusively used in storage system in memory module The system area of data) in.In addition, memory management circuitry 202 has microprocessor unit (not shown), read-only memory (not Show) and random access memory (not shown).In particular, this read-only memory has driving code, and when memory controls When device 104 is enabled, microprocessor unit, which can first carry out this driving code section, will be stored in type nonvolatile Control instruction in module 106 is loaded into the random access memory of memory management circuitry 202.Later, microprocessor list The running such as write-in, reading and erasing that member can operate these control instructions to carry out data.

In addition, the control instruction of memory management circuitry 202 can also be with a hardware in another exemplary embodiment of the present invention Form carrys out implementation.For example, memory management circuitry 202 includes microcontroller, Storage Unit Management circuit, memory write-in electricity Road, memory reading circuitry, memory erasing circuit and data processing circuit.Storage Unit Management circuit, memory write-in electricity Road, memory reading circuitry, memory erasing circuit and data processing circuit are electrically connected to microcontroller.Wherein, it stores Single Component Management circuit wipes unit to manage the physics of reproducible nonvolatile memorizer module 106；Memory write-in electricity Road writes data into non-volatile to duplicative to assign write instruction to reproducible nonvolatile memorizer module 106 In property memory module 106；Memory reading circuitry refers to assign reading to reproducible nonvolatile memorizer module 106 It enables to read data from reproducible nonvolatile memorizer module 106；Memory erasing circuit is to non-to duplicative Volatile 106 assigns erasing instruction to wipe data from reproducible nonvolatile memorizer module 106； And data processing circuit is intended to be written data to reproducible nonvolatile memorizer module 106 and from can make carbon copies to handle The data read in formula non-volatile memory module 106.

Host interface 204 is electrically connected to memory management circuitry 202 and to receive and identification host system 11 The instruction and data transmitted.That is, the instruction that host system 11 is transmitted can be passed with data by host interface 204 It send to memory management circuitry 202.In this exemplary embodiment, host interface 204 is compatible with SATA standard.However, it is necessary to It is appreciated that the invention is not limited thereto, host interface 204 is also possible to be compatible with PATA standard, 1394 standard of IEEE, PCI Express standard, USB standard, UHS-I interface standard, UHS-II interface standard, SD standard, MS standard, MMC standard, CF mark Quasi-, IDE standard or other suitable data transmission standards.

Memory interface 206 is electrically connected to memory management circuitry 202 and non-volatile to access duplicative Property memory module 106.It can be by depositing to the data of reproducible nonvolatile memorizer module 106 that is, being intended to be written Memory interface 206 is converted to the 106 receptible format of institute of reproducible nonvolatile memorizer module.

In an exemplary embodiment of the invention, Memory Controller 104 further includes buffer storage 208, power management electricity Road 210 and error checking and correcting circuit 212.

Buffer storage 208 is electrically connected to memory management circuitry 202 and is configured to temporarily store from host system 11 data and instruction or the data from reproducible nonvolatile memorizer module 106.

Electric power management circuit 210 is electrically connected to memory management circuitry 202 and to control memory storage dress Set 10 power supply.

Error checking and correcting circuit 212 are electrically connected to memory management circuitry 202 and to execute wrong inspection It looks into and correction program is to ensure the correctness of data.Specifically, when memory management circuitry 202 is received from host system 11 When to write instruction, error checking can be the corresponding error checking of data generation of this corresponding write instruction with correcting circuit 212 With correcting code (Error Checking and Correcting Code, referred to as: ECC Code), and memory management circuitry 202 the data of this corresponding write instruction can be written with corresponding error checking and correcting code to duplicative non-volatile memories In device module 106.Later, when memory management circuitry 202 reads data from reproducible nonvolatile memorizer module 106 When can read the corresponding error checking of this data and correcting code simultaneously, and error checking and correcting circuit 212 can be according to this mistakes Erroneous detection, which is looked into, executes error checking and correction program to read data with correcting code.

Fig. 6 and Fig. 7 is the example schematic of the management physics erasing unit according to shown by an exemplary embodiment.

Fig. 6 is please referred to, physics can be wiped unit 410 (0) by Memory Controller 104 (or memory management circuitry 202) ~410 (N) are logically grouped into data field 502, idle area 504, system area 506 and replace area 508.

The physics erasing unit for logically belonging to data field 502 and idle area 504 is to store from host system 11 data.Specifically, the physics erasing unit of data field 502 is regarded as the physics erasing unit of storing data, and The physics erasing unit in idle area 504 is the physics erasing unit to replacement data area 502.That is, working as from host system When system 11 receives write instruction and the data to be written, memory management circuitry 202 extracts physical can be wiped from idle area 504 It except unit, and writes data into extracted physics erasing unit, unit is wiped with the physics in replacement data area 502.

The physics erasing unit for logically belonging to system area 506 is to record system data.For example, system data includes Physics about the manufacturer of reproducible nonvolatile memorizer module and model, reproducible nonvolatile memorizer module Wipe unit number, physical programming unit number of each physics erasing unit etc..

Logically belonging to replace the physics erasing unit in area 508 is to replace program for bad physics erasing unit, to take The physics of generation damage wipes unit.Specifically, still there are normal physics erasing unit and data in area 508 if replacing When the physics erasing unit damage in area 502, memory management circuitry 202 can extract normal physics erasing from replacing in area 508 Unit wipes unit to replace the physics of damage.

In particular, the quantity meeting of data field 502, idle area 504, system area 506 and the physics erasing unit for replacing area 508 It is different according to different memory specifications.Further, it is necessary to be appreciated that, in the running of memory storage apparatus 10, Physics erasing unit is associated with to data field 502, idle area 504, system area 506 and replaces the grouping relationship in area 508 can be dynamically It changes.For example, when the physics erasing unit that the physics erasing unit damage in idle area 504 is substituted area 508 replaces, then Originally idle area 504 can be associated to by replacing the physics erasing unit in area 508.

Please refer to Fig. 7, Memory Controller 104 (or memory management circuitry 202) can configuration logic unit LBA (0)~ LBA (H) wipes unit with the physics for mapping data field 502, wherein each logic unit has multiple logical page (LPAGE)s to map pair The physical programming unit for the physics erasing unit answered.Also, when the logic unit to be write data to of host system 10 or update are deposited When the data being stored in logic unit, Memory Controller 104 (or memory management circuitry 202) can be mentioned from idle area 504 A physics erasing unit is taken to wipe unit as actuation physics wiped with the physics of alternation data field 502 for data to be written Except unit.

In exemplary embodiment of the invention, a sorting table is configured in buffer storage 208.Wherein, this sorting table It can be used for logical page (LPAGE) (or the logic in the particular aspects data in recorded data zone and logic unit LBA (0)~LBA (H) Address) between a corresponding informance.Specifically, each physics in data field 502 wipes unit 410 (0)~410 (F-1) Physical programming unit can be used for storing the write-in data from host write-in, and said write data can be general data Or particular aspects data, wherein the particular aspects data may, for example, be the word string that each bit is zero.In due course Machine, such as host system 11 are in one section of standby time or when sorting table is fully written, Memory Controller 104 (or memory pipe Manage circuit 202) it can be by the system area of the deposit reproducible nonvolatile memorizer module 106 of content recorded in this sorting table In 506, to remove the space of sorting table in buffer storage 208.

In addition, in order to solve the problems, such as continually to store sorting table previously with regard in valid data consolidation procedure, at this In the exemplary embodiment of invention, Memory Controller 104 (or memory management circuitry 202) can also be by the object in data field 502 Reason erasing unit 410 (0)~410 (F-1) at least grouping is used efficiently to the first group and the second group from data field The physics erasing unit for executing valid data consolidation procedure is selected in 502, is stored sorting table to duplicative with reducing The number of non-volatile memory module 106.Specifically, it is wiped about the physics being grouped in data field 502 to the first group Except unit, the sorting table for representing the particular aspects data in the physics erasing unit of the first group of record is not yet stored in and can answer It writes in formula non-volatile memory module 106；On the contrary, about being grouped in data field 502 to the physics erasing of the second group Unit, the sorting table for representing the particular aspects data in the physics erasing unit of the second group of record have been stored in duplicative In non-volatile memory module 106, and Memory Controller 104 (or memory management circuitry 202) can be from the second group Select for executing valid data consolidation procedure physics erasing unit, use reduced when executing valid data consolidation procedure it is whole Manage the storage number of table.

Fig. 8 A~Fig. 9 B is the simplification example for showing data write-in with updating sorting table.

It include the first group in data field 502 in exemplary embodiment of the invention referring to Fig. 8 A and Fig. 8 B 502a and the second group 502b.For convenience of description, it is assumed that in the state of the memory storage apparatus 10 of Fig. 8 A, data field 502 In not yet store the write-in data from host system 11, and logic unit LBA (0)~LBA (2) logical page (LPAGE) not yet maps Unit is wiped to any physics.And idle area 504 have 5 physics erasing units be respectively physics erasing unit 410 (0)~ 410(4).Wherein, each physics erasing unit has 3 physical programming units, and Memory Controller 104 (or memory Management circuit 202) judge when the number of the physics erasing unit to leave unused in idle area 504 is non-be greater than pre-defined value when, deposit Memory controller 104 (or memory management circuitry 202) can execute valid data consolidation procedure, empty to discharge more storages Between.In this exemplary embodiment, the pre-defined value is 2, that is to say, that when only remaining two empty physics in idle area 504 When wiping unit, Memory Controller 104 (or memory management circuitry 202) can execute above-mentioned data consolidation procedure.

In the state of the memory storage apparatus 10 of Fig. 8 A, it is assumed that the particular aspects data SD1 to be written of host system 11 To logic unit LBA (0) the 0th logical page (LPAGE) when, Memory Controller 104 (or memory management circuitry 202) can be from the spare time It sets and extracts such as physics erasing unit 410 (0) in area 504 as actuation physics erasing unit, and assign write instruction to incite somebody to action This particular aspects data SD1 is written to the 0th physical programming unit of physics erasing unit 410 (0).Memory Controller 104 (or memory management circuitry 202) can record physics erasing unit 410 (0) in one physical address-logical address mapping table The map information of 0th logical page (LPAGE) of the 0th physical programming unit and logic unit LBA (0).Then, Memory Controller 104 (or memory management circuitries 202) will record the 0th logical page (LPAGE) of this particular aspects data SD1 Yu logic unit LBA (0) Corresponding informance between face is in logic-sorting table 600 of buffer storage 208.Specifically, as shown in Figure 8 B, it is assumed that special Different aspect data SD1 is the word string (also known as, the first kind) that each bit is zero, then Memory Controller 104 (or is deposited Reservoir manages circuit 202) the particular aspects data type of particular aspects data SD1 can be recorded in logic-sorting table 600 is the 0th logical page (LPAGE) of one type (that is, information " 1 ") and particular aspects data SD1 mapped logic unit LBA (0) The corresponding informance of (that is, information " LBA (0) -0 ").

Then, it is assumed that general data ID1 and general data ID2 is respectively written to logic unit in host system 11 again later When the 1st logical page (LPAGE) of LBA (0) and the 2nd logical page (LPAGE) of logic unit LBA (0), Memory Controller 104 (or storage Device manages circuit 202) write instruction can be assigned continuing to write to this general data ID1 and general data ID2 to physics erasing 2nd physical programming unit of the 1st physical programming unit and the physics erasing unit 410 (0) of unit 410 (0).Then, it deposits It is single that memory controller 104 (or memory management circuitry 202) can record physics erasing in physical address-logical address mapping table The map information of 1st logical page (LPAGE) of the 1st physical programming unit and logic unit LBA (0) of first 410 (0), and record Physics wipes the 2nd physical programming unit of unit 410 (0) and the mapping of the 2nd logical page (LPAGE) of logic unit LBA (0) is believed Breath.

Referring to Fig. 9 A and Fig. 9 B, hookup 8A and Fig. 8 B, it is assumed herein that the standby time of host system 11 be more than When one preset value, Memory Controller 104 (or memory management circuitry 202) can be mapped according to physical address-logical address Table is loaded into the logical address-physical address map of logic unit LBA (0) from reproducible nonvolatile memorizer module 106 Table is into buffer storage 208.Then, Memory Controller 104 (or memory management circuitry 202) will be updated logic unit Mapping relations between LBA (0) and physics erasing unit 410 (0).Wherein, Memory Controller 104 (or memory management electricity Road 202) the 0th logical page (LPAGE) of logic unit LBA (0) can be mapped into physics according to physical address-logical address mapping table It wipes the 0th physical programming unit of unit 410 (0), the 1st logical page (LPAGE) of logic unit LBA (0) is mapped to physics wiping Physics is mapped to except the 1st physical programming unit of unit 410 (0) and by the 2nd logical page (LPAGE) of logic unit LBA (0) Wipe the 2nd physical programming unit of unit 410 (0).Later, Memory Controller 104 (or memory management circuitry 202) meeting The first group 502a that physics erasing unit 410 (0) is associated with and is grouped into data field 502, as shown in Figure 9 A.It should be noted It is that Memory Controller 104 (or memory management circuitry 202) is not yet to reproducible nonvolatile memorizer module at this time Physics erasing unit in 106 executes valid data consolidation procedure, and is stored in logic-sorting table in buffer storage 208 600 are also not yet stored in reproducible nonvolatile memorizer module 106, as shown in Figure 9 B.

Figure 10 A~Figure 13 B is the simplification example for showing valid data consolidation procedure and storing sorting table.

Referring to Figure 10 A and Figure 10 B, hookup 9A and Fig. 9 B, it is assumed herein that host system 11 passes through above-mentioned data Writing mode, by particular aspects data SD2, particular aspects data SD3 and general data ID3 be respectively written into physics wipe 0th~2 physical programming unit of unit 410 (1), and Memory Controller 104 (or memory management circuitry 202) loading pair Logical address-the physical address mapping table answered is to be respectively mapped to physics for the 0th~2 logical page (LPAGE) of logic unit LBA (1) The 0th~2 physical programming unit of unit 410 (1) is wiped, and physics erasing unit 410 (1) is associated with and is grouped to data field The first group 502a in 502.In addition, Memory Controller 104 (or memory management circuitry 202) can store particular aspects number According to the corresponding informance between the 0th logical page (LPAGE) of SD2 and logic unit LBA (1) in logic-arrangement of buffer storage 208 In table 600, and storage particular aspects data SD3 logic unit LBA (1) the 1st logical page (LPAGE) between corresponding informance in In logic-sorting table 600 of buffer storage 208.Specifically, as shown in Figure 10 B, it is assumed that particular aspects data SD2 is The word string (also known as, Second Type) of " 01 " repeated arrangement, then Memory Controller 104 (or memory management circuitry 202) meeting The particular aspects data type that particular aspects data SD2 is recorded in logic-sorting table 600 is Second Type (that is, information " 2 ") And the 0th logical page (LPAGE) (that is, information " LBA (1) -0 ") of particular aspects data SD2 mapped logic unit LBA (1) Corresponding informance.Likewise, it is assumed that particular aspects data SD3 is the word string (also known as, the first kind) that each bit is zero, Then Memory Controller 104 (or memory management circuitry 202) can record particular aspects data SD3 in logic-sorting table 600 Particular aspects data type be the first kind (that is, information " 1 ") and particular aspects data SD3 mapped logic unit The corresponding informance of the 1st logical page (LPAGE) (that is, information " LBA (1) -1 ") of LBA (1).

Later, it is assumed that host system 11 also by above-mentioned data writing mode, by general data ID4, general data ID5 And general data ID6 is respectively written into the 0th~2 physical programming unit of physics erasing unit 410 (2), and memory control Device 104 (or memory management circuitry 202) processed is loaded into logical address-physical address mapping table accordingly with by logic unit LBA (2) the 0th~2 logical page (LPAGE) is respectively mapped to the 0th~2 physical programming unit of physics erasing unit 410 (2), and will The first group 502a that physics erasing unit 410 (2) is associated with and is grouped into data field 502.

It is noted that at this point, since Memory Controller 104 (or memory management circuitry 202) judges idle area The number of 504 hollow physics erasing units is non-to be worth greater than pre-defined, Memory Controller 104 (or memory management electricity Road 202) valid data consolidation procedure can be executed, to discharge more memory spaces.And in this exemplary embodiment, it is described preparatory Definition value is 2, that is to say, that in the state of memory storage apparatus 10 of Figure 10 A, due to being only left object in idle area 504 Reason erasing unit 410 (3) and the empty physics of physics erasing unit 410 (4) two wipe units, Memory Controller 104 (or Memory management circuitry 202) valid data consolidation procedure of the invention can be executed.

In the state of executing valid data consolidation procedure, Memory Controller 104 (or memory management circuitry 202) is first Whether the number for first judging the physics erasing unit in the second group 502b of data field 502 is equal to 0.That is, storage Whether the second group 502b that device controller 104 (or memory management circuitry 202) judges data field 502 first is empty.

Referring to Figure 11 A and Figure 11 B, hookup 10A and Figure 10 B, if Memory Controller 104 (or memory Management circuit 202) when judging that the number of the physics erasing unit of the second group 502b is equal to 0 in Figure 10 A and Figure 10 B, storage The physics for recording the first group 502a is wiped unit 410 (0)~410 by device controller 104 (or memory management circuitry 202) (2) logic-sorting table 600 of particular aspects data SD1~SD3 in stores non-easily to duplicative from buffer storage 208 In the property lost memory module 106, and the information (as shown in Figure 11 B) in flushing logic-sorting table 600.Later, memory controls Physics erasing unit 410 (0)~410 (2) in first group 502a is grouped extremely by device 104 (or memory management circuitry 202) Second group 502b (as shown in Figure 11 A).

Then, Memory Controller 104 (or memory management circuitry 202) can be from the second group 502b of data field 502 Middle selection is for executing the physics erasing unit (also referred to as, the first physics erasing unit) of valid data merging.

Referring to Figure 12 A and Figure 12 B, hookup 11A and Figure 11 B, in this exemplary embodiment, it is assumed that memory control Device 104 (or memory management circuitry 202) processed can select physics erasing unit 410 (0) with physics erasing unit 410 (1) to hold Row valid data consolidation procedure.It will be appreciated that the present invention is not to the object selected for carrying out valid data consolidation procedure The method of reason erasing unit is restricted.For example, in an exemplary embodiment, Memory Controller 104 (or memory management circuitry 202) it can recorde an invalid data number of each physics erasing unit in the second group 502b, and judge the second group Whether there is the invalid data number of physics erasing unit to be greater than predetermined value in 502b, wherein the predetermined value is, for example, each Physics wipes 1/5th of the number of the physical programming unit in unit.In an exemplary embodiment, if the second group When the invalid data number of one of physics erasing unit among physics erasing unit in 502b is greater than the predetermined value, Memory Controller 104 (or memory management circuitry 202) can select invalid data number big from the second group 502b Unit is wiped as the physics for executing valid data consolidation procedure in the physics erasing unit of the predetermined value.

However, in another embodiment, if the invalid data number of each physics erasing unit in the second group 502b Mesh is all non-when being greater than the predetermined value, and Memory Controller 104 (or memory management circuitry 202) can will record first group again Logic-sorting table 600 of particular aspects data in the physics erasing unit of group 502a is stored from buffer storage 208 to can answer It writes in formula non-volatile memory module 106, and the information in flushing logic-sorting table 600.Later, Memory Controller 104 Physics erasing unit in first group 502a can be grouped to the second group 502b by (or memory management circuitry 202).Later Memory Controller 104 (or memory management circuitry 202) can be selected from the second group 502b for executing significant figure again Unit is wiped according to the physics of consolidation procedure.

In this exemplary embodiment, wiped since Memory Controller 104 (or memory management circuitry 202) selected physics Except unit 410 (0) and physics wipe unit 410 (1) Lai Zhihang valid data consolidation procedure, and due in logic-sorting table 600 Information related with the particular aspects data in physics erasing unit 410 (1) with physics erasing unit 410 (0) has been stored to In reproducible nonvolatile memorizer module 106, therefore it is originally used for the physics erasing unit of storage particular aspects data SD1 0th physical programming unit of 410 (0), be originally used for storage particular aspects data SD2 physics erasing unit 410 (1) the 0 physical programming unit and the physics for being originally used for storage particular aspects data SD3 wipe the 1st physics of unit 410 (0) Programming unit can all be stored by controller 104 (or memory management circuitry 202) and be identified as invalid data.That is, When carrying out valid data consolidation procedure, particular aspects data SD1~SD3 is not to be regarded as valid data, therefore particular aspects data SD1~SD3 will not be replicated.Therefore, Memory Controller 104 (or memory management circuitry 202) can wipe current physics Except the valid data (that is, general data ID1 and general data ID2) in unit 410 (0), it is copied in idle area 504 respectively Such as in the 0th~1 physical programming unit of physics erasing unit 410 (3) (also referred to as, the second physics wipes unit), and Physics is wiped into the 2nd that the valid data (that is, general data ID3) in unit 410 (1) are copied to physics erasing unit 504 In physical programming unit.Then, Memory Controller 104 (or memory management circuitry 202) can be accordingly by logic unit LBA (0) the 1st logical page (LPAGE) remaps to the 0th physical programming unit of physics erasing unit 410 (3), by logic unit The 2nd logical page (LPAGE) of LBA (0) is to remap to the 1st physical programming unit of physics erasing unit 410 (3) and incite somebody to action The 2nd logical page (LPAGE) of logic unit LBA (1) remaps to the 2nd physical programming unit of physics erasing unit 410 (3). At this point, Memory Controller 104 (or memory management circuitry 202) can will be stored in originally physics erasing unit 410 (0) and All data in physics erasing unit 410 (1) are all considered as invalid data.

Referring to Figure 13 A and Figure 13 B, hookup 12A and Figure 12 B, due to (or the memory of Memory Controller 104 Management circuit 202) it will can be stored in originally all numbers in physics erasing unit 410 (0) and physics erasing unit 410 (1) According to being all considered as invalid data, therefore Memory Controller 104 (or memory management circuitry 202) can wipe unit 410 (0) to physics And physics erasing unit 410 (0) carries out erasing operation, and unit 410 is wiped in physics erasing unit 410 (0) and physics (0) it is associated with again into idle area 504.Merge further, since having been stored in physics erasing unit 410 (3) and having executed valid data Valid data after program, and do not include particular aspects data in physics erasing unit 410 (3), therefore physics wipes unit 410 (3) it can be grouped to the second group 502b of data field 502.

By above-mentioned valid data consolidation procedure, the quantity of physics erasing unit in idle area 504 can be increased, and effectively Reduce the storage number of logic-sorting table 600.Specifically, when Memory Controller 104 (or memory management circuitry 202) Write operation is executed being written a write-in data into the physics erasing unit of reproducible nonvolatile memorizer module 106 One of (also referred to as, third physics wipe unit) when, the third physics for being just written into this write-in data is wiped single For member, due in this third physics erasing unit about the particular aspects data and logical page (LPAGE) of write-in data (or logically Location) between corresponding informance only store into logic-sorting table 600 of buffer storage 208 and be not yet stored to duplicative In non-volatile memory module 106, so third physics erasing unit can be grouped the first group into data field 502 502a.And about the data stored in the second group 502b for, particular aspects data and logical page (LPAGE) are (or logically Location) between corresponding informance be stored in reproducible nonvolatile memorizer module 106, therefore execute valid data merge When program, Memory Controller 104 (or memory management circuitry 202) only can select to be used to execute from the second group 502 The physics of valid data consolidation procedure wipes unit, uses reduction logic-sorting table 600 storage number.

Figure 14 is please referred to, the physics erasing unit in the data field is at least grouped to the first group and second group first Group, wherein the sorting table for recording the particular aspects data in the physics erasing unit of the first group is not stored in duplicative In non-volatile memory module, and the physics for recording the second group has wiped a sorting table of the particular aspects data in unit (step S1401) is stored in reproducible nonvolatile memorizer module also, when executing valid data consolidation procedure, Judge whether the number of the physics erasing unit of the second group is equal to 0 (step S1403).If the physics of the second group is wiped single When the number of member is equal to 0, the sorting table of the particular aspects data in the physics erasing unit for recording the first group is stored to can In manifolding formula non-volatile memory module (step S1405), and by the first group physics erasing unit be grouped again to Second group (step S1407), and execute step S1409.

In addition, then directly executing step S1409 when if the number of the physics erasing unit in the second group is not equal to 0.

Then, an invalid data number (step S1409) of each physics erasing unit in the second group is recorded, and is sentenced Whether there is the invalid data number of physics erasing unit to be greater than predetermined value (step S1411) in disconnected second group.If second The invalid data number of each physics erasing unit in group is all non-to be greater than the predetermined value, then returns to step S1405. If the invalid data number of one of physics erasing unit among physics erasing unit in the second group is greater than described Predetermined value then selects invalid data number to be greater than the physics erasing unit of the predetermined value (hereinafter referred to as from the second group First physics wipes unit), and this first physics is wiped into the physics wiping that multiple valid data in unit are copied to idle area Except the second physics among unit wipes unit, and erasing operation (step S1413) is carried out to the first physics erasing unit, wherein The valid data do not include the particular aspects data in the first physics erasing unit.

In conclusion the present invention divides into the first group and the second group by the way that the physics in data field is wiped unit, Wherein record the first group physics erasing unit in particular aspects data sorting table be not stored in duplicative it is non-easily In the property lost memory module, and a sorting table of the particular aspects data in the physics erasing unit of the second group of record is deposited It is stored in reproducible nonvolatile memorizer module.In addition, when executing valid data consolidation procedure, Memory Controller (or memory management circuitry) only selects the erasing unit of the physics for executing valid data consolidation procedure from the second group, by To reduce the storage of sorting table when executing valid data consolidation procedure, to solve continually to deposit in valid data consolidation procedure The problem of storing up sorting table.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution The range of scheme.

Claims

1. a kind of valid data merging method, be used for a reproducible nonvolatile memorizer module, which is characterized in that it is described can There are manifolding formula non-volatile memory module multiple physics to wipe unit, and each of physics erasing unit has multiple physics Programming unit, wherein those physics erasing unit is at least partitioned into a data field and an idle area, and the valid data merge Method includes:

Those physics erasing unit in the data field is at least grouped to one first group and one second group, wherein recording One sorting table of at least particular aspects data in those physics erasing unit of first group is not stored in described In reproducible nonvolatile memorizer module, and those physics for recording second group wipe at least one spy in unit One sorting table of different aspect data has been stored in the reproducible nonvolatile memorizer module；

One first physics is selected to wipe unit from second group；

First physics is wiped into those physics erasing unit that multiple valid data in unit are copied to the idle area Among one second physics wipe unit, and to first physics erasing unit carry out an erasing operation.

2. valid data merging method according to claim 1, which is characterized in that selected from second group above-mentioned Selecting the step of first physics wipes unit includes:

Judge whether the number of the physics erasing unit of second group is equal to 0；

If the number of the physics erasing unit of second group is equal to 0, those physics of first group will be recorded The sorting table of an at least particular aspects data in erasing unit is stored to the duplicative non-volatile memories In device module, and those physics erasing unit in first group is grouped again to second group；And

If the number of the physics erasing unit of second group is not equal to 0, wherein one is selected from second group A physics erasing unit wipes unit as first physics.

3. valid data merging method according to claim 1, which is characterized in that selected from second group above-mentioned Selecting the step of first physics wipes unit includes:

Record an invalid data number of each physics erasing unit in second group；

If the invalid data number of each of physics erasing unit in second group is all non-, to be greater than one predetermined When value, by record first group those physics erasing unit in described in an at least particular aspects data the arrangement Table is stored into the reproducible nonvolatile memorizer module, and those physics in first group are wiped unit Again it is grouped to second group；And

If one of physics among those physics erasing unit in second group wipes the described invalid of unit When data number is greater than the predetermined value, select one of physics erasing unit as described in from second group First physics wipes unit.

4. valid data merging method according to claim 1, which is characterized in that further include:

It executes a write operation and unit is wiped with the third physics that a write-in data are written into those physics erasing unit； And

Third physics erasing unit is grouped to first group.

5. valid data merging method according to claim 3, which is characterized in that the predetermined value is each of physics Wipe 1/5th of the number of those physical programming units in unit.

6. valid data merging method according to claim 1, which is characterized in that each of the particular aspects data Bit is all zero.

7. a kind of Memory Controller, for controlling a reproducible nonvolatile memorizer module, which is characterized in that described to deposit Memory controller includes:

One host interface is electrically connected to a host system；

One memory interface is electrically connected to the reproducible nonvolatile memorizer module, wherein described can make carbon copies There are formula non-volatile memory module multiple physics to wipe unit, and each of physics erasing unit is programmed with multiple physics Unit, wherein those physics erasing unit is at least partitioned into a data field and an idle area；And

One memory management circuitry is electrically connected to the host interface and the memory interface,

Wherein the memory management circuitry is being at least grouped those physics erasing unit in the data field to one the One group and one second group, wherein recording at least particular aspects number in those physics erasing unit of first group According to a sorting table be not stored in the reproducible nonvolatile memorizer module, and record second group should It is non-volatile that one sorting table of at least particular aspects data in a little physics erasing units has been stored in the duplicative In memory module,

Wherein the memory management circuitry also to from second group select one first physics wipe unit,

Wherein the memory management circuitry is also copied to first physics is wiped multiple valid data in unit One second physics among those physics erasing unit in the idle area wipes unit, and wipes unit to first physics Carry out an erasing operation.

8. Memory Controller according to claim 7, which is characterized in that in memory management circuitry described above from institute It states in the running for selecting the first physics erasing unit in the second group,

The memory management circuitry also to judge second group physics wipe unit number whether be equal to 0,

If the number of the physics erasing unit of second group is equal to 0, the memory management circuitry will be described in record First group those physics erasing unit in an at least particular aspects data the sorting table store to it is described can In manifolding formula non-volatile memory module, and those physics erasing unit in first group is grouped again to described Second group,

If the number of the physics erasing unit of second group is not equal to 0, the memory management circuitry is from described the One of physics erasing unit is selected in two groups as first physics wipes unit.

9. Memory Controller according to claim 7, which is characterized in that in memory management circuitry described above from institute It states in the running for selecting the first physics erasing unit in the second group,

The memory management circuitry records an invalid data number of the erasing unit of each physics in second group,

If the invalid data number of each of physics erasing unit in second group is all non-, to be greater than one predetermined When value, the memory management circuitry will be at least one special described in those physics erasing unit for recording first group The sorting table of aspect data is stored into the reproducible nonvolatile memorizer module, and will be in first group Those physics erasing unit be grouped again to second group,

If one of physics among those physics erasing unit in second group wipes the described invalid of unit When data number is greater than the predetermined value, the memory management circuitry selects one of object from second group Reason erasing unit wipes unit as first physics.

10. Memory Controller according to claim 7, which is characterized in that the memory management circuitry is also to hold One write operation of row wipes unit with the third physics that a write-in data are written into those physics erasing unit, described to deposit Reservoir management circuit is also being grouped third physics erasing unit to first group.

11. Memory Controller according to claim 9, which is characterized in that the predetermined value is the wiping of each of physics Except 1/5th of the number of those physical programming units in unit.

12. Memory Controller according to claim 7, which is characterized in that each ratio of the particular aspects data Spy is zero.

13. a kind of memory storage apparatus characterized by comprising

A connector is electrically connected to a host system；

There are one reproducible nonvolatile memorizer module multiple physics to wipe unit, each of physics erasing unit tool There are multiple physical programming units, wherein those physics erasing unit is at least partitioned into a data field and an idle area；And

One Memory Controller is electrically connected to the connector and the reproducible nonvolatile memorizer module,

Wherein the Memory Controller is also being at least grouped those physics erasing unit in the data field to one the One group and one second group, wherein recording at least particular aspects number in those physics erasing unit of first group According to a sorting table be not stored in the reproducible nonvolatile memorizer module, and record second group should It is non-volatile that one sorting table of at least particular aspects data in a little physics erasing units has been stored in the duplicative In memory module,

Wherein the Memory Controller also to from second group select one first physics wipe unit,

Wherein the Memory Controller is also copied to institute first physics is wiped multiple valid data in unit State idle area those physics erasing unit among one second physics erasing unit, and to first physics wipe unit into One erasing operation of row.

14. memory storage apparatus according to claim 13, which is characterized in that Memory Controller described above from In the running for selecting the first physics erasing unit in second group,

The Memory Controller also to judge second group physics wipe unit number whether be equal to 0,

If the number of the physics erasing unit of second group is equal to 0, the Memory Controller will record described the The sorting table of an at least particular aspects data in those physics erasing unit of one group, which is stored to described, answers It writes in formula non-volatile memory module, and those physics erasing unit in first group is grouped again to described the Two groups,

If the number of the physics erasing unit of second group is not equal to 0, the Memory Controller is from described second One of physics erasing unit is selected in group as first physics wipes unit.

15. memory storage apparatus according to claim 13, which is characterized in that Memory Controller described above from In the running for selecting the first physics erasing unit in second group,

The Memory Controller records an invalid data number of the erasing unit of each physics in second group,

If the invalid data number of each of physics erasing unit in second group is all non-, to be greater than one predetermined When value, the Memory Controller by record first group those physics erasing unit in described at least one special state The sorting table of sample data is stored into the reproducible nonvolatile memorizer module, and will be in first group Those physics erasing unit is grouped again to second group,

If one of physics among those physics erasing unit in second group wipes the described invalid of unit When data number is greater than the predetermined value, the Memory Controller selects one of physics from second group Unit is wiped as first physics and wipes unit.

16. memory storage apparatus according to claim 13, which is characterized in that the Memory Controller is also to hold One write operation of row wipes unit with the third physics that a write-in data are written into those physics erasing unit, described to deposit Reservoir management circuit is also being grouped third physics erasing unit to first group.

17. memory storage apparatus according to claim 15, which is characterized in that the predetermined value is each of physics Wipe 1/5th of the number of those physical programming units in unit.

18. memory storage apparatus according to claim 13, which is characterized in that each of the particular aspects data Bit is all zero.