CN106611739A - Substrate and manufacturing method thereof - Google Patents
Substrate and manufacturing method thereof Download PDFInfo
- Publication number
- CN106611739A CN106611739A CN201510708519.XA CN201510708519A CN106611739A CN 106611739 A CN106611739 A CN 106611739A CN 201510708519 A CN201510708519 A CN 201510708519A CN 106611739 A CN106611739 A CN 106611739A
- Authority
- CN
- China
- Prior art keywords
- substrate
- layer
- epitaxial layer
- oxide
- epitaxial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a substrate and a manufacturing method thereof. The method comprises steps: an auxiliary substrate and a supporting substrate are provided, wherein at least a defect elimination structure, an epitaxial layer above the defect elimination structure and a passivation layer above the epitaxial layer are arranged on the auxiliary substrate, and at least a buried dielectric layer is arranged on the supporting substrate; the auxiliary substrate is bonded on the supporting substrate; the auxiliary substrate is removed; and chemical-mechanical planarization (CMP) is carried out until the epitaxial layer reaches a specified thickness. As defects of the epitaxial layer can be reduced by the defect elimination structure and damages of the epitaxial layer during the bonding process can be effectively reduced by the passivation layer, a large amount of defects can be prevented from being generated in the epitaxial layer, and the performance and the reliability of using the epitaxial layer to manufacture a device can be enhanced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of substrate and its manufacture method.
Background technology
As IC industry constantly advances, how to reduce substrate leakage current and increasingly become people
The emphasis studied.Wherein, by using silicon-on-insulator (SOI) substrate, so that what is formed partly leads
Body device is located on insulator, it is to avoid the leakage current between semiconductor device and substrate is to generally acknowledge effect most
Good approach.
Additionally, with the continuous reduction of dimensions of semiconductor devices, needing to move by strengthening channel carrier
Shifting rate carrys out boost device performance, for example, by using SiGe, germanium etc. with high carrier mobility
Semi-conducting material replaces silicon, to strengthen channel carrier mobility.Have been proposed that in insulator
The structure of semiconductor device is manufactured on upper germanium (GOI) substrate, the semiconductor device of the structure is in operation
The aspects such as speed are substantially better than in SOI substrate the structure for manufacturing semiconductor device.
Oxonium ion is formed by ion implanting during Semiconductor substrate is typically employed in prior art to bury
Layer, then forms oxide buried layer by way of annealing in the semiconductors；Or by injecting oxygen
Ions binding stripping technology etc. forms oxide buried layer in the semiconductors；But these methods are in manufacture
During, damage easily to be brought to the material of top layer and defect is introduced, still further aspect is multiple due to technique
It is miscellaneous to cause with high costs and less efficient, it is not particularly suited in the production of extensive germanium on insulator.Additionally,
Oxide buried layer is formed in the semiconductor substrate also by bonding technology, is generally included：At one
Semiconductor epitaxial layers are formed on silicon substrate, then oxide insulating layer are formed on another silicon substrate,
Then the upper surface of above-mentioned two substrate is bonded, then by polishing or the method for chemical attack
Oxide buried layer and epitaxial layer thereon are formed in the semiconductor substrate.But, have to be formed
Generally there is larger lattice mismatch with the substrate in the epitaxial layer of high carrier mobility, the epitaxial layer
Degree, conventional cushion elimination defect method can achieve the effect that；Additionally,
During oxide buried layer is formed by the method, the epitaxial layer at bond contact face can bear very
Long High Temperature High Pressure process so that produce substantial amounts of defect, these defects can affect germanium layer performance and
Reliability.
The content of the invention
The invention provides a kind of substrate and its manufacture method, with solve to be difficult in prior art it is relatively low into
This forms the problem of high-quality oxide buried layer and its upper semiconductor layer on a semiconductor substrate.
The invention provides a kind of substrate manufacture method, including：
Provided auxiliary substrate and support substrate, in the additional substrate at least include defect expressivity structure,
Passivation layer on the upper epitaxial layer and the epitaxial layer of the defect expressivity structure, the support substrate
On at least include buried dielectric layer；
The additional substrate is bonded in the support substrate；
Remove the additional substrate；
Chemical-mechanical planarization CMP is carried out until the epitaxial layer reaches appointed thickness.
Preferably, forming the defect expressivity structure includes：
Formed with the dielectric layer no less than an opening, the depth of the opening in the additional substrate
Wide ratio is：8:1 >=depth-to-width ratio >=1:1, the cycle of the opening is 0.5-1 μm；
Carry out epitaxial growth.
Preferably, forming the defect expressivity structure includes：
Formed with the dielectric layer no less than an opening in the additional substrate；
Perform etching to form 8:1 >=depth-to-width ratio >=1:1 groove is performed etching and to form 9:1 >=depth-to-width ratio
≥2:1 groove simultaneously removes the dielectric layer, and the cycle of the groove is 0.5-1 μm；
Carry out epitaxial growth.
Preferably, the epitaxial layer includes：Germanium layer, germanium-silicon layer, germanium tin layers, III-V compound half
Conductor layer, silicon layer and its lamination.
Preferably, the passivation layer be high-k dielectric layer, including it is following any one or more：Three oxygen
Change two aluminum, hafnium oxide, hafnium silicon oxide, lanthana, aluminium oxide lanthanum, zirconium oxide, silicon oxide zirconium, oxygen
Change tantalum, titanium oxide, strontium titanium oxides barium, titanium oxide barium, strontium titanium oxides, yittrium oxide, tantalum oxide scandium lead
And its lamination.
Preferably, the high-k dielectric layer is the aluminium sesquioxide thin film that thickness is 5-10nm.
Preferably, the additional substrate is silicon substrate, and the removal additional substrate includes：
Mechanical lapping is carried out to the back side of the additional substrate until the thickness of the additional substrate is less than 50
μm；
Corroded using the Tetramethylammonium hydroxide TMAH solution of dilution, removed remaining auxiliary lining
Bottom.
Preferably, it is described that the bonding technology that the additional substrate is bonded in the support substrate is included：
Chamber maximum temperature range：200-550℃；
Bonding maximum pressure scope：1-60KN；
Bonding time scope：0.5-4 hours；
Bonding Chamber vacuum degree scope：1×10-5Mbar to 1atm.
Preferably, the bonding technology is：
Chamber maximum temperature：500℃；
Bonding maximum pressure scope：10-30KN；
Bonding time：2 hours；
Bonding Chamber vacuum degree：5×10-4Mbar to 1 × 10-5mbar。
A kind of substrate, including：
Support substrate；
Buried dielectric layer on the support substrate；
Passivation layer on the buried dielectric layer；
The epitaxial layer of appointed thickness on the passivation layer.
Preferably, the passivation layer is the aluminium sesquioxide thin film that thickness is 5-10nm.
The invention provides substrate and its manufacture method, wherein, there is provided additional substrate at least include lacking
The passivation layer fallen on elimination structure, the upper epitaxial layer of the defect expressivity structure and the epitaxial layer,
When the lattice paprmeter of the epitaxial film materials differs larger with the lattice paprmeter of the backing material, example
When such as differing 2%, the defect expressivity structure can effectively reduce epitaxial layer defects quantity, improve epitaxial layer matter
Amount；The passivation layer can be effectively protected the epitaxial layer；Then the additional substrate is bonded to into described
On support substrate, the buried dielectric layer and passivation layer in the support substrate can stop epitaxial layer with the support
Leakage current between substrate；Then the additional substrate and unnecessary epitaxial layer are removed.It is heterogeneous due to carrying out
When there is larger mismatch in the lattice paprmeter of outer time delay, especially epitaxial film materials and backing material, example
Such as epitaxial germanium layer on a silicon substrate, in epitaxial layer, can there is substantial amounts of defect, the defect expressivity structure
The a large amount of defects produced because of lattice mismatch in epitaxial process can be effectively reduced, high-quality extension is formed
Layer；Additionally, the passivation layer damaging of can effectively reducing that the epitaxial layer is subject in bonding process, it is to avoid
Substantial amounts of defect is produced in epitaxial layer, performance and reliability using the epitaxial layer manufacture device is lifted.
Further, for forming depth-to-width ratio >=1 of the opening or groove of the defect expressivity structure:1,
Should have the opening or groove of high-aspect-ratio, and when epitaxial growth is carried out, effectively can suppress to lose because of lattice
Grow up with the epitaxy defect for causing contact interface to produce, obtain the epitaxial layer with high lattice quality.
Further, the passivation layer be high K medium material, the current blocking effect of high K medium material
The current blocking effect of the oxide layer adopted in being substantially better than the traditional SOI substrate such as silicon dioxide, can have
Effect avoids substrate leakage flow phenomenon.
Further, the passivation layer is the aluminium sesquioxide thin film that thickness is 5-10nm, aluminium sesquioxide
It is a kind of highly heat-conductive material compared to silicon dioxide, in semiconductor integrated circuit, the quality of radiating is straight
Connecing affects the performance and reliability of device, using silica membrane as oxidation in traditional SOI substrate
Thing buried layer, its heat conductivility are poor, are unfavorable for that device radiates；The present invention adopts thickness for 5-10nm
Aluminium sesquioxide thin film damaging of can reducing that the epitaxial layer is subject in bonding process, while can increase
Heavy current blocking effect, with reduce it is existing by bonding technology formed in the semiconductor substrate oxide burial
The thickness of layer, is easy to device to radiate, the performance and reliability of boost device.
Further, the epitaxial layer can be with the high quasiconductor of the carrier mobility than silicon materials
The epitaxial layer that the material such as material, such as germanium, SiGe is formed, enhancing is using the device of substrate manufacture
Channel carrier mobility, with boost device performance.
Further, the invention provides bonding technology parameter, has on a semiconductor substrate to prepare
There are high-quality oxide buried layer and its upper epitaxial layer.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present application or technical scheme of the prior art, below will be to implementing
Accompanying drawing to be used needed for example is briefly described, it should be apparent that, drawings in the following description are only
Some embodiments described in the present invention, for those of ordinary skill in the art, can be with according to these
Accompanying drawing obtains other accompanying drawings.
Figure 1A to Fig. 1 D is a kind of semiconductor-on-insulator SeOI based on bonding technology in prior art
Cross section structure schematic diagram in substrate fabrication process；
Fig. 2 is the flow chart of the substrate manufacture method according to the embodiment of the present invention；
Fig. 3 A to Fig. 3 G are that the cross section structure in the substrate fabrication process according to the embodiment of the present invention one shows
It is intended to；
Fig. 4 A to Fig. 4 G are that the cross section structure in the substrate fabrication process according to the embodiment of the present invention two shows
It is intended to；
Fig. 5 A to Fig. 5 F are that the cross section structure in the substrate fabrication process according to the embodiment of the present invention three shows
It is intended to；
Fig. 6 is a kind of cross section structure of the semiconductor device manufactured using substrate provided in an embodiment of the present invention
Schematic diagram.
Specific embodiment
Embodiments of the invention are described below in detail, the example of the embodiment is shown in the drawings, its
In from start to finish same or similar label represent same or similar element or have same or like work(
The element of energy.It is exemplary below with reference to the embodiment of Description of Drawings, is only used for explaining this
It is bright, and be not construed as limiting the claims.
Semiconductor-on-insulator (Semiconductor on insulator, SeOI) is due to shape in the substrate
Into there is oxide buried layer, the oxide buried layer can effectively prevent the leakage current between device and substrate,
The problems such as improving latch-up.The manufacture of existing SeOI substrates generally adopts three kinds of methods：1. adopt
In the semiconductor substrate by ion implanting formed oxonium ion buried layer, then annealing by way of
The method that oxide buried layer is formed in quasiconductor, this is the method for most generally adopting at present, but should
Method is due to forming oxide buried layer, depth and thickness of buried layer etc. by way of ion implanting
Parameter is wayward；2. oxide is formed in the semiconductors with reference to stripping technology etc. by injecting oxonium ion
Buried layer, the method equally exist the problems referred to above, and ion implantation technology is relatively costly；3 pass through key
Close technique and form oxide buried layer in the semiconductor substrate, the method is by preformed oxide skin(coating)
It is placed in substrate by bonding technology, generally includes following steps：First, formed on one substrate
The epitaxial layer of given category material, as shown in Figure 1A, and forms as oxide on another substrate
The sull of buried layer, as shown in Figure 1B；Then, by by the upper surface of above-mentioned two substrate
It is bonded, as shown in Figure 1 C；Finally, removed with extension by the method for polishing or chemical attack
The substrate of layer, to leak cruelly epitaxial layer, as shown in figure ip.Particularly, when the epitaxial layer is germanium extension
During layer, when there is larger mismatch due to the lattice paprmeter of germanium and backing material, can exist in epitaxial layer
Substantial amounts of defect, additionally, epitaxially grown germanium layer in atmosphere easily the moisture absorption and go bad, and be bonded
During, the epitaxial layer at bond contact face can bear very long High Temperature High Pressure process, so that producing
Substantial amounts of defect, these defects can affect germanium layer performance and reliability.
Substrate and its manufacture method that the present invention is provided, due in the defect expressivity structure of additional substrate
After forming high-quality epitaxial layer, passivation layer is formed on the epitaxial layer to reduce bonding process to institute
State the impact of epitaxial layer.When the epitaxial layer is high-k dielectric layer, the surface of germanium can be passivated
And strengthen leakage current blocking effect, improve device performance and reliability.
In order to be better understood from technical scheme and technique effect, below with reference to flow chart and specifically
Embodiment be described in detail, flow chart as shown in Fig. 2 manufacture substrate process with reference to Fig. 3 A extremely
Shown in Fig. 5 F.
In embodiments of the present invention, the selection of the material of the additional substrate 100 and the epitaxial film materials
Etching ratio answers >=5:1, to ensure to reduce during the additional substrate 100 is subsequently removed to described outer
Prolong the impact of layer 101.The additional substrate 100 can be Semiconductor substrate, for example Si substrates, Ge lining
Bottom, SiGe substrate etc..In other embodiments, the Semiconductor substrate can also be to include other elements
Substrate of quasiconductor or compound semiconductor, such as GaAs, InP, GaP or SiC etc., can be with
For laminated construction, such as Si/SiGe etc..Due to needing to form epitaxial layer in the additional substrate 100
101, the lattice paprmeter of the lattice paprmeter of the epitaxial film materials and the additional substrate 100 is closer to institute
The quality for stating epitaxial layer 101 is better, contributes to the reliability of boost device.Preferably, the substrate
For relatively low and close with the lattice paprmeter of the targeted epitaxial layer material Semiconductor substrate of the prices such as silicon substrate,
With reference to shown in Fig. 3 A.
The support substrate 200 should have higher heat stability and chemical stability, additionally, should also
With higher mechanical strength, in order to realize the processing steps such as follow-up bonding；Preferably, the support
Substrate 200 should also be beneficial to device with higher pyroconductivity and radiate in the course of the work.Specifically,
The additional substrate 100 can be Semiconductor substrate, such as Si substrates, Ge substrates, SiGe substrate etc..
In other embodiments, the Semiconductor substrate can also be to include other elements quasiconductor or compound half
Substrate of conductor, such as GaAs, InP or SiC etc., can also be laminated construction, such as Si/SiGe
Deng；Additionally, the additional substrate 100 can also be the oxide crystal substrates such as Sapphire Substrate,
This no longer enumerates.
The defect expressivity structure 110 is by having 8:1 >=depth-to-width ratio >=1:1 opening or groove, make
The epitaxial layer portion in the defect expressivity structure 110 is obtained, as the opening or groove effectively can suppress
Because lattice mismatch causes the epitaxy defect that contact interface is produced to grow up, in the defect expressivity structure 110
Surface formed with high lattice quality epitaxial layer.Wherein, the opening can be cuboid, pros
Body, cylinder, cone, round platform, triangular prism etc. and its combination in any constitute the array of stereochemical structure；Should
Opening can be made up of dielectric layer or be formed in substrate, it is also possible to by dielectric layer and the common structure of substrate
Into.The dielectric layer can be the typical media thin film such as silicon dioxide, silicon oxynitride, silicon nitride.
The epitaxial layer 101 is included but is not limited to：Germanium layer, germanium-silicon layer, germanium tin layers, III-V chemical combination
Thing semiconductor layer, silicon layer and its lamination.The epitaxy technique of the epitaxial layer 101 can be hetero-epitaxy,
For example, epitaxial Germanium, SiGe, iii v compound semiconductor etc. on a silicon substrate；Can certainly be
Homoepitaxy, for example, the epitaxial Germanium in defect expressivity structure of the surface for germanium is the scarce of germanium on surface
Fall into and eliminate extension gallium arsenic etc. in structure.In addition the epitaxial layer 101 can be various epitaxial layers 101
Lamination：Silicon/SiGe/germanium lamination, gallium arsenic/aluminum arsenic/gallium arsenic lamination etc..Preferably, the epitaxial film materials
Carrier mobility more than silicon carrier mobility, for example the material such as germanium, SiGe, gallium arsenic prepare
Epitaxial layer 101, strengthen the channel carrier mobility of the device using substrate manufacture, to be lifted
Device performance.
The passivation layer 102 can be to deposit unadulterated silicon oxide using methods such as CVD, PVD
(SiO2), doping silicon oxide (such as Pyrex, boron-phosphorosilicate glass etc.) and silicon nitride (Si3N4)
Deng dielectric material, or the sull formed by hot oxygen method, further, in order to carry
The insulation effect of high oxide buried layer, the passivation layer 102 can also be to be formed by ALD
High-k dielectric layer, can include it is following any one or more：Aluminium sesquioxide, hafnium oxide, oxidation
Silicon-hafnium, lanthana, aluminium oxide lanthanum, zirconium oxide, silicon oxide zirconium, tantalum oxide, titanium oxide, titanium oxide
Strontium barium, titanium oxide barium, strontium titanium oxides, yittrium oxide, tantalum oxide scandium lead and its lamination.
The buried dielectric layer 201 can be silica membrane conventional in traditional SOI substrate, also
Can be the typical media thin film such as silicon oxynitride film, silicon nitride film.
Embodiment one
In the present embodiment, the additional substrate 100 and the support substrate 200 are body silicon substrate,
The opening depth-to-width ratio of the defect expressivity structure 110 is 5:1, the opening runs through whole substrate for length
The cuboid on surface, the width of the opening is 100nm, the opening cycle be 0.5 μm to 1 μm,
110 surface of defect expressivity structure is germanium；The epitaxial layer 101 be germanium layer, the passivation layer 102
For hafnia film, the buried dielectric layer 201 is silica membrane, with reference to shown in Fig. 3 G, should
Method includes：
Step S01, there is provided additional substrate 100 and support substrate 200, the additional substrate 100 is up to
Include defect expressivity structure 110, the upper epitaxial layer 101 of the defect expressivity structure 110 and described less
Passivation layer 102 on epitaxial layer 101, at least includes buried dielectric layer in the support substrate 200
201, as described in Fig. 3 A to Fig. 3 C.
In the present embodiment, the additional substrate 100 and the support substrate 200 are body silicon substrate,
The opening depth-to-width ratio of the defect expressivity structure 110 is 5:1, the opening runs through whole substrate for length
The cuboid on surface, the width of the opening is 100nm, and 110 surface of defect expressivity structure is
Germanium；The epitaxial layer 101 is the germanium layer of high carrier mobility to manufacture high speed device；The passivation
Layer 102 is hafnium oxide high-K medium film；The buried dielectric layer 201 is silica membrane.Its
In, forming the defect expressivity structure 110 includes：Formed to have in the additional substrate and be no less than
The dielectric layer of one opening, the depth-to-width ratio of the opening is 5:1；Carry out epitaxial growth.
In a specific embodiment, there is provided the body silicon substrate of two same specifications, one of them is used as auxiliary
Substrate 100 is helped, another is used as support substrate 200.By low-pressure chemical vapor deposition LPCVD methods
The silica membrane of about 500nm is deposited on an auxiliary substrate, then by photoetching process, etching work
Skill forms the opening that width is 100nm on the silica membrane, and the cycle of opening is 500nm,
Expose the additional substrate；By reduced pressure epitaxy method (RP Epi) shape in the additional substrate 100
Into the germanium layer of 1 to 3 μ m-thick, as shown in Figure 3A, then by ald on the germanium layer
It is the thick hafnia films of 5 to 10nm that ALD forms thickness, as shown in Figure 3 B.It is described to support lining
Form the silicon dioxide layer of 0.2 to 1 μ m-thick on bottom 200 by thermal oxide CVD on the germanium layer,
As shown in Figure 3 C.
It should be noted that as epitaxial thickness is far longer than the depth of the opening or groove, being formed
The flatness of epi-layer surface can meet the requirement of subsequent technique, certainly, if the epitaxial layer for being formed
Surface smoothness be unsatisfactory for bonding technology requirement, the surface of the epitaxial layer can be caused by CMP methods
Flatness meets bonding technology requirement；The hafnia film can effectively reduce bonding technology to the germanium layer
Impact, meanwhile, the hafnia film be high-K medium film, can be reached preferably with relatively thin thin film
Current blocking effect so that the thickness of the silicon dioxide layer can be less, but the silicon dioxide layer
Current barrier layer is used not only for, while the key stratum to lift bonding effect, the silicon dioxide layer is not
Can be excessively thin.
Step S02, the additional substrate 100 is bonded in the support substrate 200, such as Fig. 3 D institutes
Show.
In the present embodiment, by bonding apparatus by the buried dielectric layer 201 of shown additional substrate 100
Face is bonded in the support substrate 200, and bonding technology scope includes：
Chamber maximum temperature range：200-550℃；
Bonding maximum pressure scope：1-60KN；
Bonding time scope：0.5-4 hours；
Bonding Chamber vacuum degree scope：1×10-5Mbar to 1atm.
In a specific embodiment, the bonding technology is：
Chamber maximum temperature：500℃；
Bonding maximum pressure scope：10-30KN；
Bonding time：2 hours；
Bonding Chamber vacuum degree：5×10-4Mbar to 1 × 10-5mbar。
It should be noted that in order to lift bonding effect, the pressurization of the bonding technology and/or heated
Journey can be that segmentation carries out ground, for example, set the step-length of bonding pressure increase as 10 minutes, each step
It is long to increase 2KN pressure, until it reaches the pressure value of setting, then pressure is kept until bonding technology is tied
Beam；Certainly can also be linearly to be pressurizeed, for example, be set within 3 minutes and reach the pressure of setting
Force value, then keeps pressure until bonding technology terminates；Additionally, at the end of bonding technology is fast, also may be used
Reduced pressure with stepping or the method for linear decompression reduces pressure up to external pressure is no longer applied, specifically regarding using effect
Depending on.
Additionally, above-mentioned such as bonding technology scope is the feasible technique for groping out by many experiments
Window, such as when chamber temp is less than 200 DEG C, the additional substrate 100 and the support substrate
200 just cannot be bonded well, if too high, are greater than 800 DEG C, just have and cause germanium layer to melt
And/or evaporation；In the same manner, when bonding pressure value is less than 1KN, it is impossible to by two substrate bondings to
Rise, when bonding pressure is more than 60KN, substrate fragmentation may be caused, and can be remained in the substrate
Excessive internal stress, causes the reliability of the epitaxial layer 101 to reduce, therefore, above-mentioned bonding technology
Scope is feasible processing range.
Further, in order to lift bonding effect, can before bonding to the additional substrate 100 and
The support substrate 200 carries out pretreatment, for example, carry out the change such as the techniques such as standard cleaning and/or isopropanol
Learn agent treated, form the substrate surface of cleaning, then before bonding to the additional substrate 100 and
The support substrate 200 carries out the prebake conditions of low temperature, removes the steam on surface, improves the quality of bonding.
Furthermore, it is possible to carry out low temperature annealing process to completing the substrate being bonded, formed in being released in bonding process
Stress in substrate.
Step S03, removes the additional substrate 100, as shown in Fig. 3 E to Fig. 3 F.
In the present embodiment, the additional substrate 100 that removes includes：To the additional substrate 100
The back side carry out mechanical lapping grinding until the thickness of the additional substrate 100 becomes smaller than 50 μ
M, as shown in FIGURE 3 E；Corroded using the Tetramethylammonium hydroxide TMAH solution of dilution, gone
Except remaining additional substrate 100, as illustrated in Figure 3 F.
It should be noted that due to for formed the dielectric layer material of defect expressivity structure 110 with it is described
The selective etching of epitaxial layer is than larger, such as selection quarter of silicon dioxide and germanium relative to hydrofluoric acid solution
Erosion can remove exposed dielectric layer using hydrofluoric acid solution than larger.It is of course also possible to follow-up
Directly remove during CMP, here is not limited.
In a specific embodiment, by mechanical lapping by the additional substrate 100 from grinding back surface
To being less than 50 μm, then the TMAH solution by diluting is performed etching to the additional substrate 100,
Then exposed silicon dioxide is removed using hydrofluoric acid solution.Wherein, from finite concentration dilution
TMAH solution corrodes remaining silicon substrate, and advantage is that corrosion rate is controllable and uniformity is good.Certainly,
Needed before performing etching by the back-protective of the support substrate 200, such as at described
One layer of the backside coating photoresist or deposition of support substrate 200 thin film not with TMAH solution reaction,
To reduce impact of the TMAH solution to support substrate 200.
It should be noted that during the removal additional substrate 100 that provides of the present embodiment, leading to
The TMAH solution that there is high selection etching ratio to the silicon substrate is crossed, is removed and the epitaxial layer 101
100 part of additional substrate of contact, therefore, when being ground to the back side of the additional substrate 100,
Efficiency can be paid the utmost attention to, you can improve production efficiency is ground with speed faster.
Step S04, carries out chemical-mechanical planarization CMP until the epitaxial layer 101 reaches specifies thickness
Degree, as shown in Figure 3 G.
In the present embodiment, planarization process is carried out to exposed epitaxial layer 101 by CMP, until
101 thickness of the epitaxial layer reaches appointed thickness.Can be formed with precise thickness by CMP
And the epitaxial layer 101 with flat surface.
It should be noted that due to epitaxial film materials lattice paprmeter generally with the lattice paprmeter of substrate not
Unanimously so that initial epitaxial layer 101 is of low quality, the CMP step for being provided by the present invention
The not high epitaxial layer portion of these epitaxial qualities can be removed so that the substrate system provided using the present invention
The device made is formed in high-quality epitaxial layer 101, to improve the performance and reliability of device.
In the embodiment that the present invention is provided, at least included by being formed on two individual silicon substrates respectively
The lamination and buried dielectric layer 201 of epitaxial layer 101 and passivation layer 102, due to 102 energy of passivation layer
Impact of the High Temperature High Pressure to the epitaxial layer 101 when effectively long in reduction bonding process, in lining
High-quality oxide buried layer and its upper semiconductor layer are formed on bottom, to be lifted using the epitaxial layer 101
The performance and reliability of manufacture device.
Embodiment two
Substrate manufacture method, as described in embodiment one, except that, it is in the present embodiment, described
Additional substrate 100 is silicon-Germanium substrate；The opening of the defect expressivity structure 110 is formed in substrate,
Epitaxial layer on cushion and cushion are formed with the opening；The opening is a diameter of
The array of the cylinder composition of 100nm, the depth-to-width ratio of the opening is 3:1, the cycle of the opening is
0.5μm-1μm；The dielectric layer is silicon nitride film；It is 5-10nm that the passivation layer 102 is thickness
Aluminium sesquioxide thin film；The buried dielectric layer 201 is formed by hot oxygen method, and such as Fig. 4 A are to figure
Shown in 4G.
Step S11, there is provided additional substrate 100 and support substrate 200, the additional substrate 100 is up to
Include defect expressivity structure 110, the upper epitaxial layer 101 of the defect expressivity structure 110 and described less
Passivation layer 102 on epitaxial layer 101, at least includes buried dielectric layer in the support substrate 200
201, as shown in Fig. 4 A to Fig. 4 C.
In the present embodiment, the additional substrate 100 is silicon-Germanium substrate, and the support substrate 200 is
Body silicon substrate, cushion and cushion are formed with the opening on epitaxial layer；Form described lacking
Falling into elimination structure includes：Formed in the additional substrate with the dielectric layer no less than an opening,
Perform etching to form 9:1 >=depth-to-width ratio >=2:1 groove simultaneously removes the dielectric layer, carries out epitaxial growth；
The passivation layer 102 is the aluminium sesquioxide thin film that thickness is 5-10nm；The buried dielectric layer 201
It is the silica membrane formed by hot oxygen method.
Wherein, the cushion in the present embodiment, can adopt epitaxial growth technology, in dielectric film
Opening in epitaxial growth content gradually variational GexSi1-xLayer, wherein 0<x<1, initial epitaxial layer 101
X closes on when epitaxial growth finishes x closer to 1 closer to 0, and the thickness of the epitaxial layer 101 can be
1-500nm, it is concrete depending on practical effect.The cushion further can improve because of epitaxial layer material
The not high problem of material lattice paprmeter epitaxial quality different and caused from backing material lattice paprmeter, and
The cushion can be removed by techniques such as subsequent CMPs.
It should be noted that the passivation layer 102 is the aluminium sesquioxide thin film that thickness is 5-10nm,
When the passivation layer 102 be more thermally conductive than the buried dielectric layer 201 heat conductivity when, or more specifically
Ground is said, when the heat conductivity of the passivation layer 102 is more than 10Wcm at ambient temperature-1·K-1When, it is described blunt
Change layer 102 and can just be considered to have high-termal conductivity.With the continuous development of integrated circuit technique, unit plane
The exponential growth of device number integrated in product, thing followed problem is exactly device heat dissipation problem, and which is direct
Affect the performance and reliability of final manufacture device.Thickness is adopted in the present embodiment for 5-10nm three oxidations
Two aluminium films can effectively reduce what bonding technology was affected on the epitaxial layer 101 as passivation layer 102
Simultaneously as aluminium sesquioxide has more than 10Wcm-1·K-1Thermal conductivity, and aluminium sesquioxide for height
K media, can strengthening electric current blocking effect while, reduce it is existing by bonding technology in Semiconductor substrate
The thickness of the oxide buried layer with low heat conductivity of middle formation, is easy to device to radiate, boost device
Performance and reliability.
In a specific embodiment, there is provided two substrates with size, wherein silicon-Germanium substrate is used as auxiliary
Substrate 100 is helped, body silicon substrate is used as support substrate 200.By PECVD in the additional substrate
Surface deposit 450nm silicon nitride films as dielectric layer, then by photoetching process and etching technics
The circular array figure of a diameter of 100nm is formed on the dielectric layer, and with the dielectric layer as mask
The substrate is performed etching to form array of cylinders, and removes the silicon nitride film, etching depth is
300nm, it is outer in the additional substrate 100 followed by molecular beam epitaxy MBE or reduced pressure epitaxy method
The Ge of epitaxial growth content gradually variationalxSi1-xLayer as cushion, wherein 0<x<1, initial epitaxial layer 101
Closer to 0, closer to 1, its buffer layer thickness is 1-500nm to x to close on x when epitaxial growth finishes,
Then epitaxial growth thickness is 0.2-1 μm of germanium layer, as shown in Figure 4 A；Then on the germanium layer
It is the thick aluminium sesquioxide thin film of 5 to 10nm that thickness is formed by ald ALD, is such as schemed
Shown in 4B.The dioxy that thickness is 0.2 to 1 μm is formed by hot oxygen method in the support substrate 200
SiClx thin film, as shown in Figure 4 C.
It should be noted that the silica membrane that can form densification by hot oxygen method lifts insulation effect
Really.Before epitaxial growth is carried out, the additional substrate 100 can also be carried out using TMAH solution
Pre-etching, to improve the quality of epitaxial layer 101.
Step S12, the additional substrate 100 is bonded in the support substrate 200, such as Fig. 4 D
It is shown.
Specifically, the bonding technology is：
Chamber maximum temperature：550℃；
Bonding maximum pressure scope：8-20KN；
Bonding time：1 hour；
Bonding Chamber vacuum degree：1×10-4Mbar to 1 × 10-5mbar。
Step S13 to step S14, with S03 the step of embodiment one to step S04, such as Fig. 4 E extremely
Shown in Fig. 4 G, will not be described in detail herein.
Substrate manufacture method provided in an embodiment of the present invention, by forming thick on the epitaxial layer 101
The aluminium sesquioxide thin film for 5-10nm is spent as passivation layer 102, as the passivation layer 102 is in room temperature
Under the conditions of be more than 10Wcm-1·K-1, with higher heat conductivity, can not only reduce bonding technology to described outer
Prolong the impact of layer 101, can also reduce existing by having that bonding technology is formed in the semiconductor substrate
The thickness of the oxide buried layer of low heat conductivity, is easy to device to radiate, the performance and reliability of boost device
Property.
Embodiment three
Substrate manufacture method, as described in embodiment one, except that, the epitaxial layer 101 is germanium
Tin layers；Include the passivation on epitaxial layer 101, the epitaxial layer 101 in the additional substrate 100
Oxidation material layer 103 on layer 102 and the passivation layer 102；The support substrate 200 is
Sapphire Substrate；The opening of the defect expressivity structure 110 is collectively forming by dielectric layer and substrate, institute
State the epitaxial layer on cushion and cushion being formed with opening；The opening is 100nm for the length of side
Square composition array, the depth-to-width ratio of the opening is 7:1；The passivation layer 102 for thickness is
The aluminium sesquioxide thin film of 5-10nm, as shown in Fig. 5 A to Fig. 5 F.
Step S21, there is provided additional substrate 100 and support substrate 200, the additional substrate 100 is up to
Include defect expressivity structure 110, the upper epitaxial layer 101 of the defect expressivity structure 110 and described less
Passivation layer 102 on epitaxial layer 101, at least includes buried dielectric layer in the support substrate 200
201, as shown in Fig. 5 A to Fig. 5 B.
In the present embodiment, different from embodiment one, in the additional substrate 100, at least include defect
Eliminate structure 110, the upper epitaxial layer 101 of the defect expressivity structure 110 and the epitaxial layer 101
On passivation layer 102 outside, the oxidation material layer 103 being also formed with passivation layer 102, institute
The opening for stating defect expressivity structure 110 is collectively forming by dielectric layer and substrate, forms the defect expressivity
Structure 110 includes：Formed in the additional substrate 100 with the dielectric layer no less than an opening,
Perform etching to form 8:1 >=depth-to-width ratio >=1:1 groove, carries out epitaxial growth, wherein, the groove
Cycle be 0.5 μm -1 μm.Epitaxial layer on cushion and cushion are formed with the opening；
The array that the opening is constituted for the square that the length of side is 100nm, the depth-to-width ratio of the opening is 7:1,
With reference to shown in Fig. 5 A；The material of the oxidation material layer 103 can be identical with the buried dielectric layer 201
Or it is different, it is preferable that the material of the oxidation material layer 103 is identical with the buried dielectric layer 201,
And the oxidation material layer 103 is equal to presetting oxidation with the thickness sum of the buried dielectric layer 201
The thickness of thing buried layer.Wherein, the oxidation material layer 103 on the passivation layer 102 can be further
Reduce impact of the bonding technology to the epitaxial layer 101, device on the epitaxial layer 101 is formed to improve
The performance and reliability of part.It should be noted that the oxidation material layer 103 and the buried dielectric layer
201 thickness sum is equal to the thickness of presetting oxide buried layer, i.e., described support substrate
Can not also form buried dielectric layer 201 on 200, and the oxidation material thickness degree of assisted epitaxy layer 101
Equal to the thickness of presetting oxide buried layer, but in actual applications, need in view of protection
The thickness of the cleanliness factor on 200 surface of support substrate and single film on substrate lamination is crossed conference and brings thin
The problems such as film uniformity is deteriorated, does not all only manufacture all laminations in a substrate as far as possible.
Epitaxial layer on cushion and cushion are formed with the opening.Wherein, the cushion
Material component can be identical or different with the material component of the useful layer 1012, for example, the present embodiment
Middle additional substrate 100 is body silicon substrate, and useful layer 1012 is germanium stannum epitaxial layer, and cushion is outside SiGe
Prolonging layer causes useful layer 1012 with silicon materials lattice constant mismatch is larger to alleviate germanium tin material lattice paprmeter
The not high problem of epitaxial quality.
The buried dielectric layer 201 can be the sull formed by techniques such as PECVD,
As shown in Figure 5 B, can also be certainly lamination of the typical media thin film such as silicon dioxide, silicon oxynitride etc..
The passivation layer 102 is thickness for the concrete serving as reference embodiment of aluminium sesquioxide thin film two of 5-10nm
Relevant portion content, no longer describes in detail.
The support substrate 200 is Sapphire Substrate, due to sapphire heat conductivity it is higher and blue
The extreme hardness of gem, can be used for manufacturing the chip of high mechanical properties.Further, since sapphire material
Differ greatly with selective etching ratio of the silicon materials relative to TMHA solution, subsequently removing the auxiliary
During substrate 100, can be without carrying out to the silicon substrate in silicon substrate backside coating photoresist etc.
Step is protecting support substrate 200 unaffected.
In a specific embodiment, by low-pressure chemical vapor deposition LPCVD methods in additional substrate
The silica membrane of upper deposition about 200nm, then by photoetching process, etching technics in the dioxy
Array of the length of side for the square bodily form of 100nm is formed on SiClx thin film, the additional substrate is exposed；Connect
And the etching additional substrate is continued by dry or wet etch, etching depth is for about 500nm；No
The remainder for removing the silica membrane directly passes through ultra-high vacuum CVD
UHVCVD methods and/or reaction and plasma body chemical vapor phase growing RPCVD methods are formed epitaxially one after the other thickness
Germanium-silicon layer and thickness for 200nm is 2 μm of germanium tin layers；Then forming thickness by ALD is
The aluminium sesquioxide thin film of 5-10nm；Then pass through low-pressure chemical vapor deposition LPCVD methods and form thickness
Spend the silica membrane for 0.2 μm.Pass through high-density plasma chemical gas on a sapphire substrate
Mutually deposit HDPCVD methods and form the silica membrane that thickness is 0.3 μm.
Step S22, the additional substrate 100 is bonded in the support substrate 200, such as Fig. 5 C
It is shown.
Specifically, the bonding technology is：
Chamber maximum temperature：500℃；
Bonding maximum pressure scope：8-20KN；
Bonding time：3 hours；
Bonding Chamber vacuum degree：1×10-4Mbar to 1 × 10-5mbar。
, into step S24, the such as Fig. 5 D of the cross section structure schematic diagram in substrate fabrication process are to figure for step S23
Shown in 5F, detailed content reference implementation example two will not be described in detail herein.
In the present embodiment, by three oxidations of the thickness for 5-10nm are formed on the epitaxial layer 101
Then two aluminium films form the oxidation of appointed thickness on the passivation layer 102 as passivation layer 102
Material layer 103, can utilize the passivation layer 102 and the oxidation material layer 103 to reduce bonding technology to described outer
Prolong the impact of layer 101, be lifted on the epitaxial layer 101 and form the performance and reliability of device.
Correspondingly, present invention also offers according to said method manufacture substrate, with reference to shown in Fig. 3 G,
Including：
Support substrate 200；
Buried dielectric layer 201 on the support substrate 200；
Passivation layer 102 on the buried dielectric layer 201；
The epitaxial layer 101 of appointed thickness on the passivation layer 102.
Wherein, the passivation layer 102 is the aluminium sesquioxide thin film that thickness is 5-10nm.
The substrate that the present invention is provided can be used to manufacture semiconductor device structure, it may for example comprise：As described above
Substrate described in embodiment, and the device architecture at the epitaxial layer, the device architecture can be with
Including：Gate dielectric layer 303 on the epitaxial layer 101, and it is located at the gate dielectric layer
Grid 304 on 303, positioned at the source/drain region 302 of 304 both sides of the grid, and for isolating
The isolation 301 of the source/drain region 302, as shown in Figure 6.Wherein, the grid 304 can be many
Crystal silicon grid, or metal gate；When grid 304 is metal gate, the gate dielectric layer 303 is most
It is good to use the high k dielectric materials such as hafnium oxide, tantalum oxide, aluminium sesquioxide, zirconium oxide.Certainly,
The epitaxial layer 101 can be also used for forming fin, to manufacture fin formula field effect transistor.However, this
Invention is not limited to this, and can also form other quasiconductors such as transistor, diode, LSI
Device.
Although the present invention is disclosed as above with preferred embodiment, but is not limited to the present invention.Appoint
What those of ordinary skill in the art, under without departing from technical solution of the present invention ambit, all can profit
Many possible variations are made to technical solution of the present invention with the methods and techniques content of the disclosure above and is repaiied
Decorations, or the Equivalent embodiments for being revised as equivalent variations.Therefore, it is every without departing from technical solution of the present invention
Content, according to the present invention technical spirit to any simple modification made for any of the above embodiments, equivalent
Change and modification, still fall within the range of technical solution of the present invention protection.
Claims (11)
1. a kind of substrate manufacture method, it is characterised in that include：
Provided auxiliary substrate and support substrate, in the additional substrate at least include defect expressivity structure,
Passivation layer on the upper epitaxial layer and the epitaxial layer of the defect expressivity structure, the support substrate
On at least include buried dielectric layer；
The additional substrate is bonded in the support substrate；
Remove the additional substrate；
Chemical-mechanical planarization CMP is carried out until the epitaxial layer reaches appointed thickness.
2. method according to claim 1, it is characterised in that form the defect expressivity structure
Including：
Formed with the dielectric layer no less than an opening, the depth of the opening in the additional substrate
Wide ratio is：8:1 >=depth-to-width ratio >=1:1, the cycle of the opening is 0.5-1 μm；
Carry out epitaxial growth.
3. method according to claim 1, it is characterised in that form the defect expressivity structure
Including：
Formed with the dielectric layer no less than an opening in the additional substrate；
Perform etching to form 8:1 >=depth-to-width ratio >=1:1 groove is performed etching and to form 9:1 >=depth-to-width ratio
≥2:1 groove simultaneously removes the dielectric layer, and the cycle of the groove is 0.5-1 μm；
Carry out epitaxial growth.
4. method according to claim 1, it is characterised in that the epitaxial layer includes：Germanium layer,
Germanium-silicon layer, germanium tin layers, iii v compound semiconductor layer, silicon layer and its lamination.
5. method according to claim 1, it is characterised in that the passivation layer is high K medium
Layer, including it is following any one or more：Aluminium sesquioxide, hafnium oxide, hafnium silicon oxide, lanthana,
Aluminium oxide lanthanum, zirconium oxide, silicon oxide zirconium, tantalum oxide, titanium oxide, strontium titanium oxides barium, titanium oxide barium,
Strontium titanium oxides, yittrium oxide, tantalum oxide scandium lead and its lamination.
6. method according to claim 5, it is characterised in that the high-k dielectric layer is thickness
For the aluminium sesquioxide thin film of 5-10nm.
7. method according to claim 1, it is characterised in that the additional substrate is silicon substrate,
It is described to remove the additional substrate and include：
Mechanical lapping is carried out to the back side of the additional substrate until the thickness of the additional substrate is less than 50
μm；
Corroded using the Tetramethylammonium hydroxide TMAH solution of dilution, removed remaining auxiliary lining
Bottom.
8. the method according to any one of claim 1 to 6, it is characterised in that it is described will be described
The bonding technology that additional substrate is bonded in the support substrate includes：
Chamber maximum temperature range：200-550℃；
Bonding maximum pressure scope：1-60KN；
Bonding time scope：0.5-4 hours；
Bonding Chamber vacuum degree scope：1×10-5Mbar to 1atm.
9. method according to claim 8, it is characterised in that the bonding technology is：
Chamber maximum temperature：500℃；
Bonding maximum pressure scope：10-30KN；
Bonding time：2 hours；
Bonding Chamber vacuum degree：5×10-4Mbar to 1 × 10-5mbar。
10. a kind of substrate, it is characterised in that include：
Support substrate；
Buried dielectric layer on the support substrate；
Passivation layer on the buried dielectric layer；
The epitaxial layer of appointed thickness on the passivation layer.
11. substrates according to claim 10, it is characterised in that the passivation layer for thickness is
The aluminium sesquioxide thin film of 5-10nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510708519.XA CN106611739B (en) | 2015-10-27 | 2015-10-27 | Substrate and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510708519.XA CN106611739B (en) | 2015-10-27 | 2015-10-27 | Substrate and method for manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106611739A true CN106611739A (en) | 2017-05-03 |
| CN106611739B CN106611739B (en) | 2019-12-10 |
Family
ID=58614407
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510708519.XA Active CN106611739B (en) | 2015-10-27 | 2015-10-27 | Substrate and method for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106611739B (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109686658A (en) * | 2018-12-13 | 2019-04-26 | 中国科学院微电子研究所 | Semiconductor devices and its production method |
| CN109950153A (en) * | 2019-03-08 | 2019-06-28 | 中国科学院微电子研究所 | Semiconductor structure and its production method |
| CN111564533A (en) * | 2020-04-07 | 2020-08-21 | 中国科学院上海微系统与信息技术研究所 | Preparation method of 1550nm waveband single photon source, single photon source and optical device |
| CN112635492A (en) * | 2020-12-02 | 2021-04-09 | 广东省大湾区集成电路与系统应用研究院 | Strain GeSiOI substrate and manufacturing method thereof |
| CN113314395A (en) * | 2021-04-16 | 2021-08-27 | 中国科学院微电子研究所 | Semiconductor substrate and preparation method of semiconductor structure |
| CN113314397A (en) * | 2021-04-16 | 2021-08-27 | 中国科学院微电子研究所 | Semiconductor substrate and preparation method of semiconductor structure |
| CN113314394A (en) * | 2021-04-16 | 2021-08-27 | 中国科学院微电子研究所 | Semiconductor substrate and preparation method of semiconductor structure |
| CN113314396A (en) * | 2021-04-16 | 2021-08-27 | 中国科学院微电子研究所 | Semiconductor substrate and preparation method of semiconductor structure |
| CN113380876A (en) * | 2021-06-10 | 2021-09-10 | 四川美阔电子科技有限公司 | Gallium nitride power device structure and preparation method |
| WO2024093982A1 (en) * | 2022-11-03 | 2024-05-10 | 华为技术有限公司 | Heterogeneous bonded structure and preparation method therefor, and electronic device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6252261B1 (en) * | 1998-09-30 | 2001-06-26 | Nec Corporation | GaN crystal film, a group III element nitride semiconductor wafer and a manufacturing process therefor |
| CN103378236A (en) * | 2012-04-25 | 2013-10-30 | 清华大学 | Epitaxy structural body with microstructure |
| US20150279725A1 (en) * | 2014-03-28 | 2015-10-01 | Imec Vzw | Semiconductor-on-insulator device and method of fabricating the same |
-
2015
- 2015-10-27 CN CN201510708519.XA patent/CN106611739B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6252261B1 (en) * | 1998-09-30 | 2001-06-26 | Nec Corporation | GaN crystal film, a group III element nitride semiconductor wafer and a manufacturing process therefor |
| CN103378236A (en) * | 2012-04-25 | 2013-10-30 | 清华大学 | Epitaxy structural body with microstructure |
| US20150279725A1 (en) * | 2014-03-28 | 2015-10-01 | Imec Vzw | Semiconductor-on-insulator device and method of fabricating the same |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109686658B (en) * | 2018-12-13 | 2021-03-09 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| CN109686658A (en) * | 2018-12-13 | 2019-04-26 | 中国科学院微电子研究所 | Semiconductor devices and its production method |
| CN109950153B (en) * | 2019-03-08 | 2022-03-04 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN109950153A (en) * | 2019-03-08 | 2019-06-28 | 中国科学院微电子研究所 | Semiconductor structure and its production method |
| CN111564533A (en) * | 2020-04-07 | 2020-08-21 | 中国科学院上海微系统与信息技术研究所 | Preparation method of 1550nm waveband single photon source, single photon source and optical device |
| CN111564533B (en) * | 2020-04-07 | 2021-06-22 | 中国科学院上海微系统与信息技术研究所 | Preparation method of 1550nm waveband single photon source, single photon source and optical device |
| CN112635492A (en) * | 2020-12-02 | 2021-04-09 | 广东省大湾区集成电路与系统应用研究院 | Strain GeSiOI substrate and manufacturing method thereof |
| CN113314395A (en) * | 2021-04-16 | 2021-08-27 | 中国科学院微电子研究所 | Semiconductor substrate and preparation method of semiconductor structure |
| CN113314394A (en) * | 2021-04-16 | 2021-08-27 | 中国科学院微电子研究所 | Semiconductor substrate and preparation method of semiconductor structure |
| CN113314396A (en) * | 2021-04-16 | 2021-08-27 | 中国科学院微电子研究所 | Semiconductor substrate and preparation method of semiconductor structure |
| CN113314397A (en) * | 2021-04-16 | 2021-08-27 | 中国科学院微电子研究所 | Semiconductor substrate and preparation method of semiconductor structure |
| CN113380876A (en) * | 2021-06-10 | 2021-09-10 | 四川美阔电子科技有限公司 | Gallium nitride power device structure and preparation method |
| WO2024093982A1 (en) * | 2022-11-03 | 2024-05-10 | 华为技术有限公司 | Heterogeneous bonded structure and preparation method therefor, and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106611739B (en) | 2019-12-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106611739A (en) | Substrate and manufacturing method thereof | |
| US10964535B2 (en) | Polycrystalline ceramic substrate and method of manufacture | |
| CN109844184B (en) | Engineered substrate structures for power and radio frequency applications | |
| JP7105239B2 (en) | Gallium nitride epitaxial structure for power devices | |
| JP7190244B2 (en) | RF device integrated on the processed substrate | |
| US10755986B2 (en) | Aluminum nitride based Silicon-on-Insulator substrate structure | |
| US7402477B2 (en) | Method of making a multiple crystal orientation semiconductor device | |
| JP6511516B2 (en) | Method of manufacturing germanium on insulator substrate | |
| JP2010535419A (en) | Ultra-thin single crystal semiconductor TFT and its manufacturing process | |
| KR20100080777A (en) | Semiconductor wafer re-use in an exfoliation process using heat treatment | |
| US20140273480A1 (en) | Method for producing a substrate provided with edge protection | |
| CN106611740A (en) | Substrate and manufacturing method thereof | |
| KR102327330B1 (en) | SOI Wafer Manufacturing Method | |
| US20130140576A1 (en) | Semiconductor device and method for manufacturing the same | |
| JP2010141263A (en) | Semiconductor device | |
| US20090004825A1 (en) | Method of manufacturing semiconductor substrate | |
| JP2006173354A (en) | Manufacturing method of soi substrate | |
| US20120126310A1 (en) | Method for forming channel material | |
| JP2011029594A (en) | Method of manufacturing soi wafer, and soi wafer | |
| CN113841223B (en) | Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device | |
| KR102317552B1 (en) | Method of manufacturing bonded SOI wafer | |
| US20130189821A1 (en) | Methods for fabricating semiconductor devices with reduced damage to shallow trench isolation (sti) regions |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |