CN106598810A - Multi-CPU airborne data processing unit BIT monitoring architecture - Google Patents
Multi-CPU airborne data processing unit BIT monitoring architecture Download PDFInfo
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- CN106598810A CN106598810A CN201611163612.8A CN201611163612A CN106598810A CN 106598810 A CN106598810 A CN 106598810A CN 201611163612 A CN201611163612 A CN 201611163612A CN 106598810 A CN106598810 A CN 106598810A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3058—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
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- Quality & Reliability (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
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- Photometry And Measurement Of Optical Pulse Characteristics (AREA)
Abstract
The present invention provides a multi-CPU airborne data processing unit BIT monitoring architecture. To realize different functions, a whole module is divided into a data processing functional area, a power conversion functional area, a photoelectric conversion functional area, and a BIT monitoring functional area. The BIT monitoring functional area is responsible for collecting junction temperature information of each CPU in the data processing functional area, secondary voltage information of the power conversion functional area, inforamtion about a power DC/DC state of a PSM, and optical power detection information and so on of an optical module of the photoelectric conversion functional area. The BIT monitoring functional area stores the collected information in a shared memory. Each CPU of the data processing functional area accesses the shared memory of the BIT monitoring functional area by using a local bus, so as to acquire BIT information of the whole module. Through adoption of the multi-CPU airborne data processing unit BIT monitoring architecture, each CPU can be managed to acquire the BIT monitoring information of the module, so that each CPU can acquire the overall health state of the whole module, and then top application software running on the CPU adjusts task division reasonably according to the current health state of the module.
Description
Technical field
The invention belongs to avionics technical field, specially a kind of multi -CPU on-board data processing unit BIT monitoring framework.
Background technology
As the development in epoch, the self-contained number of sensors of modern opportunity of combat are more and more, bearing for task is also more next
More complicated, the operand for bringing on-board data is presented the growth of geometry level, due to aircraft space and the limit of single cpu operational capability
System, in individual module integrated multiple CPU to be cooperateed with, the situation of concurrent computing it is universal all the more, each CPU is required for comprehensively
The health status of whole module is controlled, then by the top layer application software operated on CPU according to the current health status of module
Reasonable adjustment task is divided the work.
How the BIT monitoring informations of the whole module of each CPU acquisitions of high-efficiency tissue are a problem demanding prompt solutions.
The content of the invention
For the situation of the integrated multiple CPU of current individual module, it is an object of the invention to provide one kind can effectively be managed, shared
The framework of whole module BIT information.
To achieve these goals, the present invention proposes that a kind of multi -CPU on-board data processing unit BIT monitors framework, never
Congenerous angle set out by whole Module Division be data processing function area, power source conversion function area, photoelectric converting function area and
BIT monitoring functions area;Wherein BIT monitoring functions area is responsible for junction temperature information, the Power convert of each CPU in gathered data processing function area
The information such as the secondary voltage information of functional areas, the power supply DC/DC states of PSM, the optical module luminous power detection of photoelectric converting function area,
BIT monitoring functions area will collect these information and be saved in shared drive, and each CPU in data processing function area passes through local bus
The shared drive in BIT monitoring functions area is accessed, so as to get the BIT information of whole module.
The technical scheme is that:
A kind of multi -CPU on-board data processing unit BIT monitors framework, it is characterised in that:By data processing function area,
Power source conversion function area, photoelectric converting function area and BIT monitoring functions district's groups into;
Data processing function area by on-board data processing unit in multiple CPU constitute;
The junction temperature information of each CPU in gathered data processing function area of BIT monitoring functions area, the secondary electricity in power source conversion function area
Pressure information, photoelectric converting function area optical module luminous power detection information;
BIT monitoring functions area is saved in the information for collecting in shared drive;BIT monitoring functions area carry is at data
On the local bus of each CPU in reason functional areas, each CPU accesses shared memory space by local bus addressing.
A kind of further preferred version, multi -CPU on-board data processing unit BIT monitors framework, it is characterised in that:
The logic function unit in BIT monitoring functions area includes cpu temperature collecting unit, power supply secondary voltage collecting unit, luminous power inspection
Survey unit and address decoding unit.
A kind of further preferred version, multi -CPU on-board data processing unit BIT monitors framework, it is characterised in that:
Cpu temperature collecting unit reads the temperature data in temperature sensor by I2C buses with 1S as loop cycle, then will read
To data be filled in corresponding BIT data structures;Power supply secondary voltage collecting unit controls AD conversion core with 1S as cycle
Piece collection power source conversion function area magnitude of voltage, reads the data in AD conversion chip and is charged to corresponding BIT numbers by I2C buses
According in structure;Luminous power detector unit to read discrete magnitude in the way of read photoelectric converting function area's luminous power and be charged to corresponding
In BIT data structures;Address decoding unit carries out address decoding to the read operation that each CPU is initiated, according to decoding ground out
Location control CPU accesses different BIT data.
A kind of further preferred version, multi -CPU on-board data processing unit BIT monitors framework, it is characterised in that:
The information of BIT monitoring functions area collection also includes PSM power state informations, rotation speed of the fan information;The logic in BIT monitoring functions area
Functional unit also includes PSM power supply status monitoring unit and rotation speed of the fan monitoring unit;PSM power supply status monitoring unit and fan
Monitor speed unit to read discrete magnitude in the way of read PSM power supply status and rotation speed of the fan information and be charged to corresponding BIT numbers
According in structure.
Beneficial effect
The present invention can effectively organize each CPU acquisition module BIT monitoring information so that each CPU can be slapped comprehensively
The health status of whole module is controlled, is then closed according to the current health status of module by the top layer application software operated on CPU
The reason adjustment task division of labor.
The additional aspect and advantage of the present invention will be set forth in part in the description, and partly will become from the following description
Obtain substantially, or recognized by the practice of the present invention.
Description of the drawings
The above-mentioned and/or additional aspect and advantage of the present invention will become from the description with reference to accompanying drawings below to embodiment
It is substantially and easy to understand, wherein:
Fig. 1:Functions of modules Division schematic diagram.
Specific embodiment
Embodiments of the invention are described below in detail, the embodiment is exemplary, it is intended to for explaining the present invention, and
It is not considered as limiting the invention.
The purpose of the present invention is the situation for the integrated multiple CPU of current individual module, there is provided one kind can effectively be managed, divided
Enjoy the framework of whole module BIT information.
To achieve these goals, the present invention proposes that a kind of multi -CPU on-board data processing unit BIT monitors framework, never
Congenerous angle set out by whole Module Division be data processing function area, power source conversion function area, photoelectric converting function area and
BIT monitoring functions area;Wherein BIT monitoring functions area is responsible for junction temperature information, the Power convert of each CPU in gathered data processing function area
The information such as the secondary voltage information of functional areas, the power supply DC/DC states of PSM, the optical module luminous power detection of photoelectric converting function area,
BIT monitoring functions area will collect these information and be saved in shared drive, and each CPU in data processing function area passes through local bus
The shared drive in BIT monitoring functions area is accessed, so as to get the BIT information of whole module.
As shown in figure 1, multi -CPU on-board data processing unit BIT monitoring frameworks, are turned by data processing function area, power supply
Change functional areas, photoelectric converting function area and BIT monitoring functions district's groups into.
Data processing function area is made up of four CPU in on-board data processing unit.;
Associated control logic, the peripheral core of control are write by Verilog language with FPGA as core in BIT monitoring functions area
Piece completes the collection of BIT information.As shown in figure 1, the information of collection includes the junction temperature information of each CPU in data processing function area, electricity
The secondary voltage information in source translation function area, photoelectric converting function area optical module luminous power detection information;Also include PSM power supply shapes
State information, rotation speed of the fan information.
BIT monitoring functions area is saved in the information for collecting in the shared drive opened up inside FPGA;BIT monitoring functions
FPGA is mapped to CPU by area's carry on the local bus of each CPU in data processing function area by way of Address space mappinD
In addressable space, each CPU accesses shared memory space by local bus addressing.
Each BIT information data structures are specifically defined and see the table below in BIT monitoring functions area:
BIT monitoring functions area adopts Verilog language development logic function units, including cpu temperature collecting unit, power supply
Secondary voltage collecting unit, luminous power detector unit and address decoding unit, also including PSM power supply status monitoring unit and wind
Fan monitor speed unit.
Cpu temperature collecting unit reads the temperature data in temperature sensor by I2C buses with 1S as loop cycle, so
The data for reading are filled in corresponding BIT data structures afterwards.
With 1S as cycle, control AD conversion chip gathers power source conversion function area voltage to power supply secondary voltage collecting unit
Value, after waiting A/D chip collection to finish, reads the data in AD conversion chip and is charged to corresponding BIT data by I2C buses
In structure.
Luminous power detector unit to read discrete magnitude in the way of read photoelectric converting function area's luminous power and be charged to corresponding
In BIT data structures.
Address decoding unit carries out address decoding to the read operation that each CPU is initiated, according to decoding address control out
CPU accesses different BIT data.
PSM power supply status monitoring unit and rotation speed of the fan monitoring unit to read discrete magnitude in the way of read PSM power supply shapes
State and rotation speed of the fan information are simultaneously charged in corresponding BIT data structures.
Although embodiments of the invention have been shown and described above, it is to be understood that above-described embodiment is example
Property, it is impossible to limitation of the present invention is interpreted as, one of ordinary skill in the art is in the principle and objective without departing from the present invention
In the case of above-described embodiment can be changed within the scope of the invention, change, replace and modification.
Claims (4)
1. a kind of multi -CPU on-board data processing unit BIT monitors framework, it is characterised in that:Turned by data processing function area, power supply
Change functional areas, photoelectric converting function area and BIT monitoring functions district's groups into;
Data processing function area by on-board data processing unit in multiple CPU constitute;
The junction temperature information of each CPU in gathered data processing function area of BIT monitoring functions area, the secondary voltage letter in power source conversion function area
Breath, photoelectric converting function area optical module luminous power detection information;
BIT monitoring functions area is saved in the information for collecting in shared drive;BIT monitoring functions area's carry is in data processing work(
On the local bus of each CPU in energy area, each CPU accesses shared memory space by local bus addressing.
2. according to claim 1 a kind of multi -CPU on-board data processing unit BIT monitors framework, it is characterised in that:BIT is supervised
The logic function unit of control functional areas includes cpu temperature collecting unit, power supply secondary voltage collecting unit, luminous power detector unit
And address decoding unit.
3. according to claim 2 a kind of multi -CPU on-board data processing unit BIT monitors framework, it is characterised in that:CPU temperature
Degree collecting unit reads the temperature data in temperature sensor by I2C buses with 1S as loop cycle, then will read
Data are filled in corresponding BIT data structures;Power supply secondary voltage collecting unit with 1S as cycle, adopt by control AD conversion chip
Collection power source conversion function area magnitude of voltage, reads the data in AD conversion chip and is charged to corresponding BIT data knot by I2C buses
In structure;Luminous power detector unit to read discrete magnitude in the way of read photoelectric converting function area's luminous power and be charged to corresponding BIT
In data structure;Address decoding unit carries out address decoding to the read operation that each CPU is initiated, according to decoding address control out
CPU processed accesses different BIT data.
4. according to claim 2 a kind of multi -CPU on-board data processing unit BIT monitors framework, it is characterised in that:BIT is supervised
The information of control functional areas collection also includes PSM power state informations, rotation speed of the fan information;The logic function in BIT monitoring functions area
Unit also includes PSM power supply status monitoring unit and rotation speed of the fan monitoring unit;PSM power supply status monitoring unit and rotation speed of the fan
Monitoring unit to read discrete magnitude in the way of read PSM power supply status and rotation speed of the fan information and be charged to corresponding BIT data knot
In structure.
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112506746A (en) * | 2020-12-16 | 2021-03-16 | 杭州迪普科技股份有限公司 | Temperature monitoring method and system for multiple central processing units |
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CN103625647A (en) * | 2013-11-29 | 2014-03-12 | 中国航空无线电电子研究所 | Onboard novel comprehensive data loading and transmitting device |
CN204242172U (en) * | 2014-12-11 | 2015-04-01 | 南京长峰航天电子科技有限公司 | A kind of on-board data pen recorder |
CN105426286A (en) * | 2015-11-05 | 2016-03-23 | 浪潮(北京)电子信息产业有限公司 | System for monitoring whole rack server |
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2016
- 2016-12-16 CN CN201611163612.8A patent/CN106598810A/en active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH0736719A (en) * | 1993-07-20 | 1995-02-07 | Nippondenso Co Ltd | Runaway monitoring device for multi-cpu system |
CN101055556A (en) * | 2006-04-10 | 2007-10-17 | 中国科学院研究生院 | Multiple CPU system and method for passing information between CPU |
CN202230375U (en) * | 2011-09-30 | 2012-05-23 | 华自科技股份有限公司 | Data acquisition measurement control device based on FlexRay bus |
CN103625647A (en) * | 2013-11-29 | 2014-03-12 | 中国航空无线电电子研究所 | Onboard novel comprehensive data loading and transmitting device |
CN204242172U (en) * | 2014-12-11 | 2015-04-01 | 南京长峰航天电子科技有限公司 | A kind of on-board data pen recorder |
CN105426286A (en) * | 2015-11-05 | 2016-03-23 | 浪潮(北京)电子信息产业有限公司 | System for monitoring whole rack server |
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CN112506746A (en) * | 2020-12-16 | 2021-03-16 | 杭州迪普科技股份有限公司 | Temperature monitoring method and system for multiple central processing units |
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