CN106557432B - Buffer storage supervisory method, memorizer control circuit unit and storage device - Google Patents

Abstract

The present invention provides a kind of buffer storage supervisory method, memorizer control circuit unit and memory storage apparatus.The method includes: to mark off the mapping table area with first area and second area in buffer storage；Multiple logical addresses-physical address mapping table is kept in first area or second area；And receive instruction and write first data into the first write instruction of the first logical address, wherein the first logical address-physical address mapping table belonging to the first logical address is temporarily stored in the first cache unit of second area.The method further include: update the first logical address-physical address mapping table；Updated first logical address-physical address mapping table is moved to the second cache unit of first area；And the second cache unit is denoted as more new state, the time that logical address-physical address mapping table is restored to type nonvolatile can be effectively saved, the operational paradigm of total system is promoted.

Description

Buffer storage supervisory method, memorizer control circuit unit and storage device

Technical field

The invention relates to a kind of buffer storage supervisory methods, and in particular to a kind of buffer storage supervisory Method, memorizer control circuit unit and memory storage apparatus.

Background technique

Digital camera, mobile phone and MP3 player are very rapid in growth over the years, so that consumer is to storage The demand of media also rapidly increases.Since reproducible nonvolatile memorizer module (for example, flash memory) has data It is non-volatile, power saving, small in size, and without characteristics such as mechanical structures, so being very suitable to be built into above-mentioned illustrated various In portable multimedia device.

In general, in using memory storage apparatus of the type nonvolatile as storage media, Buffer storage can be generally also configured, procedure code, data are configured to temporarily store or is executing background for memory storage apparatus (background) staging area of work hours evidence.For example, the controller of memory storage apparatus can be by logical address-entity Address mapping table is loaded into buffer storage and accesses data with benefit.And when receiving write instruction and execute write operation, it deposits The controller of reservoir storage device will be updated the logical address-physical address mapping table being temporarily stored in buffer storage.And work as When having kept in the logical address-physical address mapping table being largely updated in buffer storage, memory storage apparatus Controller can that physical address mapping table restores to duplicative be non-volatile by the logical address being updated in buffer storage- In memory.Since the logical address-physical address mapping table being updated is possible to not be to be temporarily stored in buffer storage to connect In continuous cache unit, and type nonvolatile is with entity program unit for minimum write-in unit, because This, it is necessary to the logical address being updated-physical address mapping table is first copied into the staging area in buffer storage, with collection It is middle just to restore to type nonvolatile at the size for being equivalent to an entity program unit.However, a large amount of Duplication operation to will lead to system load overweight, restore overlong time, decline overall performance.Therefore, how to be promoted logic Address-physical address mapping table restores to the efficiency of type nonvolatile from buffer storage, thus field skill Art personnel subject under discussion of concern.

Summary of the invention

The present invention provides a kind of buffer storage supervisory method, memorizer control circuit unit and memory storage apparatus, It can promote the effect that logical address-physical address mapping table is restored to type nonvolatile from buffer storage Rate.

One example of the present invention embodiment proposes a kind of buffer storage supervisory method, for the slow of memory storage apparatus Rush memory.This memory storage apparatus has reproducible nonvolatile memorizer module.This buffer storage supervisory method It is included in buffer storage and marks off mapping table area, and mapping table zoning is divided into first area and second area, and first Region and second area respectively have continuous multiple cache units.This buffer storage supervisory method also includes from can make carbon copies Multiple logical addresses-physical address mapping table to first area and second area is loaded into formula non-volatile memory module, and Each logical address-physical address mapping table can be temporarily stored in one of cache unit of first area or second area One of cache unit.This buffer storage supervisory method further includes receiving the first write instruction from host system, this The instruction of one write instruction writes first data into the first logical address, and belonging to the first logical address first logically Location-physical address mapping table is temporarily stored in the first cache unit among the cache unit of second area.This buffer storage Management method further includes updating the first logical address-physical address mapping table, by updated first logical address-physical address Mapping table is moved into the second cache unit among the cache unit of first area.Also, by updated first logic After address-physical address mapping table is moved into the second cache unit among the cache unit of first area, second is delayed Memory cell is denoted as more new state.In addition, when if all cache units of first area are all denoted as more new state, It will be temporarily stored in the logical address in all cache units of first area-physical address mapping table restore to duplicative and is non-volatile In property memory module.

In one example of the present invention embodiment, above-mentioned buffer storage supervisory method further includes that will be temporarily stored in the firstth area Another logical address-physical address mapping table in second cache unit in domain moves the first cache unit into second area In.

In one example of the present invention embodiment, above-mentioned buffer storage supervisory method further includes receiving from host system The second data are written to the second logical address, and the second logical address for second write instruction, the instruction of this second write instruction Affiliated the second logical address-physical address mapping table is temporarily stored in the third cache unit among the cache unit of first area In.Furthermore the second logical address-physical address mapping table is updated, third cache unit is denoted as more new state.

In one example of the present invention embodiment, above-mentioned buffer storage supervisory method further includes receiving from host system Third data are written to third logical address, and third logical address for third write instruction, the instruction of this third write instruction Affiliated third logical address-physical address mapping table is not yet loaded into mapping table area.Furthermore it is non-volatile from duplicative Third logical address-physical address mapping table is loaded into memory module to mapping table area, wherein third logical address-is physically Location mapping table is temporarily stored in the 4th cache unit among the cache unit of first area.In addition, updating third logical address- 4th cache unit is denoted as more new state by physical address mapping table.

In one example of the present invention embodiment, above-mentioned buffer storage supervisory method further includes according in first area Cache unit sequence, choose first cache unit as the second cache unit, and set the first index to be directed toward second slow Memory cell.In addition, the first index of setting is directed toward the slow of first area after the second cache unit is denoted as more new state Another cache unit among memory cell, this another cache unit are that the latter of the second cache unit is not to have updated shape The cache unit of state.

In one example of the present invention embodiment, above-mentioned buffer storage supervisory method further includes receiving from host system First reads instruction, and the 4th data of the 4th logical address, and the 4th logical address institute are read in this first reading instruction instruction Four logical addresses-physical address the mapping table belonged to is not yet loaded into mapping table area.Furthermore it is deposited from duplicative is non-volatile Four logical addresses-physical address mapping table is loaded into memory modules to mapping table area, and four logical addresses-physical address Mapping table is temporarily stored in the 5th cache unit among the cache unit of second area.

In one example of the present invention embodiment, above-mentioned buffer storage supervisory method further includes according in second area Cache unit sequence, choose the last one cache unit as the 5th cache unit, and set the second index and be directed toward the 5th Cache unit.In addition, after four logical addresses-physical address mapping table is temporarily stored in the 5th cache unit, setting the Two indexs are directed toward the previous cache unit of the 5th cache unit in second area.

One example of the present invention embodiment proposes a kind of memorizer control circuit unit, non-volatile for controlling duplicative Property memory module.This memorizer control circuit unit includes host interface, memory interface, buffer storage and memory pipe Manage circuit.Host interface is coupled to a host system, and memory interface is coupled to reproducible nonvolatile memorizer module, delays Rush memory and be coupled to host interface and memory interface, memory management circuitry be coupled to host interface, memory interface with Buffer storage.Memory management circuitry can mark off mapping table area in buffer storage, and mapping table zoning is divided into One region and second area, and first area and second area respectively have continuous multiple cache units.Furthermore memory Management circuit is also loaded into multiple logical addresses-physical address mapping table to first from reproducible nonvolatile memorizer module Region and second area, and each logical address-physical address mapping table can be temporarily stored in its of the cache unit of first area One of or one of the cache unit of second area.In addition, memory management circuitry also receives first from host system Write instruction, the instruction of this first write instruction write first data into the first logical address, and belonging to the first logical address The first logical address-physical address mapping table be temporarily stored in the first cache unit among the cache unit of second area. Also, memory management circuitry updates the first logical address-physical address mapping table, by updated first logical address-entity Address mapping table is moved into the second cache unit among the cache unit of first area.Also, by updated first After logical address-physical address mapping table is moved into the second cache unit among the cache unit of first area, storage Second cache unit can be denoted as more new state by device management circuit.In addition, if all cache units of first area are all When being denoted as more new state, memory management circuitry will be temporarily stored in all cache units of first area logically Location-physical address mapping table restores in reproducible nonvolatile memorizer module.

In one example of the present invention embodiment, above-mentioned memory management circuitry will also be temporarily stored in the second of first area and delay Unused logical address-physical address mapping table in memory cell is moved in the first cache unit into second area.

In one example of the present invention embodiment, above-mentioned memory management circuitry also receives the second write-in from host system and refers to It enables, the second data are written to the second logical address the instruction of this second write instruction, and second belonging to the second logical address Logical address-physical address mapping table is temporarily stored in the third cache unit among the cache unit of first area.On in addition, It states memory management circuitry and also updates the second logical address-physical address mapping table, and third cache unit has been denoted as this More new state.

In one example of the present invention embodiment, above-mentioned memory management circuitry also receives third write-in from host system and refers to It enables, third data are written to third logical address, and third belonging to third logical address the instruction of this third write instruction Logical address-physical address mapping table is not yet loaded into mapping table area.Furthermore above-mentioned memory management circuitry is also from can make carbon copies Third logical address-physical address mapping table is loaded into formula non-volatile memory module to mapping table area, and third is logically Location-physical address mapping table is temporarily stored in the 4th cache unit among the cache unit of first area.In addition, the memory Management circuit also updates third logical address-physical address mapping table, and the 4th cache unit is denoted as more new state.

In one example of the present invention embodiment, above-mentioned memory management circuitry is also according to the cache unit in first area Sequence, choose first cache unit as the second cache unit, and set the first index and be directed toward the second cache unit.This Outside, after the second cache unit is denoted as more new state, memory management circuitry also sets the first index and is directed toward first Another cache unit among the cache unit in region, this another cache unit are that the next of the second cache unit is not The cache unit of more new state.

In one example of the present invention embodiment, above-mentioned memory management circuitry also receives first and read from host system to be referred to It enables, this first reads instruction instruction and read the 4th data of the 4th logical address, and the 4th patrols belonging to the 4th logical address Address-physical address mapping table is collected not yet to be loaded into mapping table area.In addition, above-mentioned memory management circuitry is also from duplicative Four logical addresses-physical address mapping table is loaded into non-volatile memory module, and four logical addresses-physical address reflects Firing table is temporarily stored in the 5th cache unit among the cache unit of second area.

In one embodiment of this invention, above-mentioned memory management circuitry is also according to the suitable of the cache unit in second area Sequence chooses the last one cache unit as the 5th cache unit, and sets the second index and be directed toward the 5th cache unit.In addition, After four logical addresses-physical address mapping table is temporarily stored in the 5th cache unit, above-mentioned memory management circuitry is also Set the previous cache unit for the 5th cache unit that the second index is directed toward in second area.

One example of the present invention embodiment proposes a kind of memory storage apparatus comprising connecting interface unit can be made carbon copies Formula non-volatile memory module and above-mentioned memorizer control circuit unit.Connecting interface unit is coupled to host system, deposits Memory control circuit unit is coupled to connecting interface unit and deposits with reproducible nonvolatile memorizer module and including buffering Reservoir.

Based on above-mentioned, memorizer control circuit unit that exemplary embodiment of the present invention is proposed, memory storage apparatus and Its buffer storage supervisory method used, which can be saved effectively, restores to duplicative for logical address-physical address mapping table The time of nonvolatile memory promotes the operational paradigm of total system.

To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make Carefully it is described as follows.

Detailed description of the invention

Fig. 1 is the schematic diagram of the host system according to shown by an exemplary embodiment and memory storage apparatus；

Fig. 2 is the signal of the computer according to shown by an exemplary embodiment, input/output device and memory storage apparatus Figure；

Fig. 3 is the schematic diagram of host system and memory storage apparatus shown by exemplary embodiment according to the present invention；

Fig. 4 is the schematic block diagram of the memory storage apparatus according to shown by an exemplary embodiment；

Fig. 5 is the schematic block diagram of the memorizer control circuit unit according to shown by an exemplary embodiment；

Fig. 6 and Fig. 7 is the example schematic of the management entity erased cell according to shown by an exemplary embodiment；

Fig. 8 is the schematic diagram of the buffer storage according to shown by an exemplary embodiment；

Fig. 9 A~9F is the schematic diagram of the buffer storage supervisory method according to shown by an exemplary embodiment；

Figure 10 is the flow chart of the buffer storage supervisory method according to shown by an exemplary embodiment.

Description of symbols:

10: memory storage apparatus；

11: host system；

12: computer；

13: input/output device；

122: microprocessor；

124: random access memory (RAM)；

126: system bus；

128: data transmission interface；

21: mouse；

22: keyboard；

23: display；

24: printer；

25: mobile hard disk；

26: storage card；

27: solid state hard disk；

31: digital camera

32:SD card；

33:MMC card；

34: memory stick；

35:CF card；

36: embedded storage device；

402: connecting interface unit；

404: memorizer control circuit unit；

406: reproducible nonvolatile memorizer module；

410 (0)~410 (N): entity erased cell；

502: memory management circuitry；

504: host interface；

506: memory interface；

508: buffer storage；

510: electric power management circuit；

512: error checking and correcting circuit；

602: data field；

604: idle area；

606: system area；

608: replacing area；

LBA (0)~LBA (H): logic unit；

LZ (0)~LZ (M): logic region；

810 (1-0)~810 (1-n), 810 (2-0)~810 (2-n): cache unit；

MTZ: mapping table area；

Z1: first area；

Z2: second area；

MT (0)~MT (2n), MT (k), MT (s): logical address-physical address mapping table；

S1001, S1003, S1005, S1007, S1009, S1011, S1013, S1015, S1017: buffer storage supervisory The step of method.

Specific embodiment

In general, memory storage apparatus (also referred to as, storage system) includes duplicative non-volatile memories Device module and controller (also referred to as, control circuit unit).Be commonly stored device storage device be used together with host system so that Host system can write data into memory storage apparatus or read from memory storage apparatus data.

Fig. 1 is the schematic diagram of the host system according to shown by an exemplary embodiment and memory storage apparatus, and Fig. 2 is According to the schematic diagram of computer shown by an exemplary embodiment, input/output device and memory storage apparatus.

Fig. 1 is please referred to, host system 11 generally comprises computer 12 and input/output (Input/Output, abbreviation I/O) is filled Set 13.Computer 12 includes microprocessor 122, random access memory (Random Access Memory, abbreviation RAM) 124, is Bus 126 of uniting and data transmission interface 128.Input/output device 13 include as Fig. 2 mouse 21, keyboard 22, display 23 with Printer 24.It will be appreciated that the unrestricted input/output device 13 of device shown in Fig. 2, input/output device 13 can be also Including other devices.

In this exemplary embodiment, memory storage apparatus 10 is by data transmission interface 128 and host system 11 Other elements are electrically connected.It can be incited somebody to action by the running of microprocessor 122, random access memory 124 and input/output device 13 Data are written to memory storage apparatus 10 or read data from memory storage apparatus 10.For example, memory storage apparatus 10 can be mobile hard disk 25 as shown in Figure 2, storage card 26 or solid state hard disk (Solid State Drive, abbreviation SSD) 27 Deng type nonvolatile storage device.

Fig. 3 is the schematic diagram of the host system according to shown by an exemplary embodiment and memory storage apparatus.

In general, host system 11 is substantially to cooperate with memory storage apparatus 10 with any system of storing data System.Although host system 11 is explained with computer system, however, in another exemplary embodiment in this exemplary embodiment Middle host system 11 can be the systems such as digital camera, video camera, communication device, audio player or video player.For example, When host system is the digital camera (video camera) 31 in Fig. 3, type nonvolatile storage device is then it Used SD card 32, mmc card 33, memory stick (memory stick) 34,36 (such as Fig. 3 of CF card 35 or embedded storage device It is shown).Embedded storage device 36 includes embedded multi-media card (embedded MMC, abbreviation eMMC), general flash Device (Universal Flash Storage, abbreviation UFS).It is noted that embedded multi-media card or general flash Device is directly electrically connected on the substrate of host system.

Fig. 4 is the schematic block diagram of the memory storage apparatus according to shown by an exemplary embodiment.

Referring to figure 4., memory storage apparatus 10 include connecting interface unit 402, memorizer control circuit unit 404 with Reproducible nonvolatile memorizer module 406.

In this exemplary embodiment, connecting interface unit 402 is compliant serial Advanced Technology Attachment (Serial Advanced Technology Attachment, abbreviation SATA) standard.However, it is necessary to be appreciated that, the present invention is not limited to This, connecting interface unit 402 is also possible to meet parallel advanced technology annex (Parellel Advanced Technology Attachment, abbreviation PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, abbreviation IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, abbreviation PCI Express) standard, universal serial bus (Universal Serial Bus, abbreviation USB) standard, a ultrahigh speed generation (Ultra High Speed-I, abbreviation UHS-I) interface standard, superelevation Fast two generations (Ultra High Speed-II, abbreviation UHS-II) interface standard, secure digital (Secure Digital, abbreviation SD) interface standard, memory stick (Memory Stick, abbreviation MS) interface standard, multimedia storage card (Multi Media Card, abbreviation MMC) interface standard, compact flash (Compact Flash, abbreviation CF) interface standard, integrated driving electrical interface (Integrated Device Electronics, abbreviation IDE) standard or other suitable standards.In this exemplary embodiment, Connecting interface unit can be encapsulated in a chip with memorizer control circuit unit, or is laid in one and is included memory control electricity Outside the chip of road unit.

Memorizer control circuit unit 404 is to execute in the form of hardware or the multiple logic gates or control of form of firmware implementation System instruction, and writing for data is carried out in reproducible nonvolatile memorizer module 406 according to the instruction of host system 11 The running such as enter, read and erase.

Reproducible nonvolatile memorizer module 406 is coupled to memorizer control circuit unit 404, and to deposit The data that storage host system 11 is written.Reproducible nonvolatile memorizer module 406 has entity erased cell 410 (0) ~410 (N).For example, entity erased cell 410 (0)~410 (N) can belong to the same memory crystal grain (die) or belong to not Same memory crystal grain.Each entity erased cell is respectively provided with a plurality of entity program units, wherein belonging to the same reality The entity program unit of body erased cell can be written independently and simultaneously be erased.However, it is necessary to be appreciated that, this hair It is bright without being limited thereto, each entity erased cell be can by 64 entity program units, 256 entity program units or other Any entity program unit is formed.

In more detail, entity erased cell is the minimum unit erased.That is, each entity erased cell contains minimum The storage unit of number being erased together.Entity program unit is the minimum unit of sequencing.That is, entity program unit For the minimum unit that data are written.Each entity program unit generally includes data bit area and redundancy ratio special zone.Data ratio Special zone includes data of multiple entity access addresses to store user, and data of the redundancy ratio special zone to storage system (for example, control information and error correcting code).In this exemplary embodiment, the data bit area of each entity program unit Middle can include 8 entity access addresses, and the size of an entity access address is 512 bytes (byte).However, in other models It also may include the more or fewer entity access addresses of number in data bit area, the present invention is not intended to limit reality in example embodiment The size and number of body access address.For example, entity erased cell is physical blocks, and real in an exemplary embodiment Body programmed cell is physical page or entity sector, but invention is not limited thereto.

In this exemplary embodiment, reproducible nonvolatile memorizer module 406 is multi-level cell memory (Multi Level Cell, abbreviation MLC) NAND type flash memory module be (that is, can store 2 data bit elements in a storage unit Flash memory module).However, the invention is not limited thereto, reproducible nonvolatile memorizer module 406 can also be single-order and deposit Storage unit (Single Level Cell, abbreviation SLC) NAND type flash memory module in a storage unit (that is, can store The flash memory module of 1 data bit element), Complex Order storage unit (Trinary Level Cell, abbreviation TLC) NAND type Flash memory module (that is, flash memory module that 3 data bits can be stored in a storage unit), other flash memories Memory modules or other memory modules with the same characteristics.

Fig. 5 is the schematic block diagram of the memorizer control circuit unit according to shown by an exemplary embodiment.

Referring to figure 5., memorizer control circuit unit 404 includes memory management circuitry 502, host interface 504 and deposits Memory interface 506, buffer storage 508, electric power management circuit 510 and error checking and correcting circuit 512.

Overall operation of the memory management circuitry 502 to control memorizer control circuit unit 404.Specifically, it deposits Reservoir, which manages circuit 502, has multiple control instructions, and when memory storage apparatus 10 operates, these control instructions can quilt It executes the running such as to carry out the write-in of data, read and erase.

In this exemplary embodiment, the control instruction of memory management circuitry 502 is to carry out implementation with form of firmware.For example, Memory management circuitry 502 has microprocessor unit (not shown) and read-only memory (not shown), and these controls refer to Order is programmed in so far read-only memory.When memory storage apparatus 10 operates, these control instructions can be by microprocessor Unit is executed the running such as to carry out the write-in of data, read and erase.

Fig. 6 and Fig. 7 is the example schematic of the management entity erased cell according to shown by an exemplary embodiment.

It will be appreciated that being described herein the fortune of the entity erased cell of reproducible nonvolatile memorizer module 406 When making, carrying out application entity erased cell with the words such as " extraction ", " grouping ", " division ", " association " is concept in logic.Namely It says, the physical location of the entity erased cell of reproducible nonvolatile memorizer module is not changed, but in logic to can The entity erased cell of manifolding formula non-volatile memory module is operated.

Fig. 6 is please referred to, memorizer control circuit unit 404 (or memory management circuitry 502) can be by entity erased cell 410 (0)~410 (N) are logically grouped into data field 602, idle area 604, system area 606 and replace area 608.

The entity erased cell for logically belonging to data field 602 and idle area 604 is to store from host system 11 data.Specifically, the entity erased cell of data field 602 is regarded as the entity erased cell of storing data, and The entity erased cell in idle area 604 is the entity erased cell to replacement data area 602.That is, working as from host system When system 11 receives write instruction and the data to be written, memory management circuitry 502 can extract entity from idle area 604 and smear It except unit, and writes data into extracted entity erased cell, with the entity erased cell in replacement data area 602.

The entity erased cell for logically belonging to system area 606 is to record system data.For example, system data includes Entity about the manufacturer of reproducible nonvolatile memorizer module and model, reproducible nonvolatile memorizer module Erased cell number, entity program unit number of each entity erased cell etc..

Logically belonging to replace the entity erased cell in area 608 is to replace program for bad entity erased cell, to take The entity erased cell of generation damage.Specifically, still there are normal entity erased cell and data if replacing in area 608 When the entity erased cell damage in area 602, memory management circuitry 502 can extract normal entity from substitution area 608 and erase Unit replaces the entity erased cell of damage.

In particular, the quantity meeting of data field 602, idle area 604, system area 606 and the entity erased cell for replacing area 608 It is different according to different memory specifications.Further, it is necessary to be appreciated that, in the running of memory storage apparatus 10, Entity erased cell is associated with to data field 602, idle area 604, system area 606 and replaces the grouping relationship in area 608 can be dynamically It changes.For example, when the entity erased cell that the entity erased cell damage in idle area 604 is substituted area 608 replaces, then Replace the entity erased cell in area 608 that can be associated to idle area 604 originally.

Fig. 7 is please referred to, memorizer control circuit unit 404 (or memory management circuitry 502) can configuration logic unit LBA (0)~LBA (H) to map the entity erased cell of data field 602, wherein each logic unit have multiple logical subunits with Map the entity program unit of corresponding entity erased cell.Also, work as the logic unit to be write data to of host system 11 Or when updating storage the data in logic unit, memorizer control circuit unit 404 (or memory management circuitry 502) can be from An entity erased cell is extracted data are written, with the entity erased cell in replacement data area 602 in idle area 604.At this In exemplary embodiment, logical subunit can be logical page (LPAGE) or logic sector.

In order to identify which entity erased cell is the data of each logic unit be stored in, in this exemplary embodiment, Memorizer control circuit unit 404 (or memory management circuitry 502) will record between logic unit and entity erased cell Mapping.Also, when host system 11 is intended to access data in logical subunit, memorizer control circuit unit 404 (or storage Device manages circuit 502) it can confirm logic unit belonging to this logical subunit, and smeared in this logic unit mapped entity Except accessing data in unit.For example, in this exemplary embodiment, memorizer control circuit unit 404 (or memory management electricity Road 502) logical address-physical address mapping table can be stored in reproducible nonvolatile memorizer module 406 to record often One logic unit mapped entity erased cell, and when data to be accessed memorizer control circuit unit 404 (or storage Device manages circuit 502) logical address-physical address mapping table can be loaded into buffer storage 508 to safeguard.

Reflecting for all logic units is recorded it is noted that can not store since the capacity of buffer storage 508 is limited The mapping table of relationship is penetrated, therefore, in this exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) logic unit LBA (0)~LBA (H) can be grouped into multiple logic region LZ (0)~LZ (M), and be each logic area One logical address of configuration of territory-physical address mapping table.In particular, when (or the memory management of memorizer control circuit unit 404 Circuit 502) when being intended to update the mapping of some logic unit, logical address-reality of logic region belonging to this corresponding logic unit Body address mapping table can be loaded on buffer storage 508 to be updated.

In another exemplary embodiment of the present invention, the control instruction of memory management circuitry 502 can also be in the form of procedure code The specific region of reproducible nonvolatile memorizer module 406 is stored in (for example, being exclusively used in storage system in memory module The system area of data) in.In addition, memory management circuitry 502 has microprocessor unit (not shown), read-only memory (not Show) and random access memory (not shown).In particular, this read-only memory has driving code, and when memory controls When circuit unit 404 is enabled, microprocessor unit can first carry out this driving code section, and will to be stored in duplicative non-volatile Control instruction in memory module 406 is loaded into the random access memory of memory management circuitry 502.Later, micro- place Reason device unit such as can operate these control instructions to carry out the write-in of data, read and erase at the running.

In addition, the control instruction of memory management circuitry 502 can also be with a hardware in another exemplary embodiment of the present invention Form carrys out implementation.For example, memory management circuitry 502 includes microcontroller, Storage Unit Management circuit, memory write-in electricity Road, memory reading circuitry, memory are erased circuit and data processing circuit.Storage Unit Management circuit, memory write-in electricity Circuit is erased on road, memory reading circuitry, memory and data processing circuit is coupled to microcontroller.Wherein, storage unit Manage entity erased cell of the circuit to manage reproducible nonvolatile memorizer module 406；Memory write circuit is used It writes data into duplicative is non-volatile and deposits to assign write instruction to reproducible nonvolatile memorizer module 406 In memory modules 406；Memory reading circuitry to reproducible nonvolatile memorizer module 406 assign reading instruction with Data are read from reproducible nonvolatile memorizer module 406；Memory erases circuit to non-volatile to duplicative Property memory module 406 assign erase instruction data to be erased from reproducible nonvolatile memorizer module 406；And it counts According to processing circuit to handle be intended to be written data to reproducible nonvolatile memorizer module 406 and from duplicative it is non- The data read in volatile 406.

Referring again to Fig. 5, host interface 504 is coupled to memory management circuitry 502 and connects to be coupled to connection Mouthful unit 402, to receive and identify instruction and data that host system 11 is transmitted.That is, host system 11 is transmitted Instruction and data memory management circuitry 502 can be sent to by host interface 504.In this exemplary embodiment, host Interface 504 is compatible SATA standard.However, it is necessary to be appreciated that the invention is not limited thereto, host interface 504 is also possible to be compatible with PATA standard, 1394 standard of IEEE, PCI Express standard, USB standard, UHS-I interface standard, UHS-II interface standard, SD standard, MS standard, MMC standard, CF standard, IDE standard or other suitable data transmission standards.

Memory interface 506 is coupled to memory management circuitry 502 and duplicative is non-volatile to be deposited to access Memory modules 406.That is, memory can be passed through by being intended to be written to the data of reproducible nonvolatile memorizer module 406 Interface 506 is converted to the 406 receptible format of institute of reproducible nonvolatile memorizer module.

Buffer storage 508 is coupled to memory management circuitry 502 and is configured to temporarily store from host system 11 Data and instruction or the data from reproducible nonvolatile memorizer module 406.

Electric power management circuit 510 is coupled to memory management circuitry 502 and to control memory storage apparatus 10 Power supply.

Error checking and correcting circuit 512 be coupled to memory management circuitry 502 and to execute error checking with Correction program is to ensure the correctness of data.Specifically, it is write when memory management circuitry 502 is received from host system 11 When entering to instruct, error checking can generate corresponding error checking and school with correcting circuit 512 for the data of this corresponding write instruction Code (Error Checking and Correcting Code, abbreviation ECC Code), and 502 meeting of memory management circuitry The data of this corresponding write instruction are written with corresponding error checking and correcting code to type nonvolatile mould In block 406.Later, meeting when reading data from reproducible nonvolatile memorizer module 406 when memory management circuitry 502 The corresponding error checking of this data and correcting code are read simultaneously, and error checking and correcting circuit 512 can be examined according to this mistake It looks into and error checking and correction program is executed to read data with correcting code.

Fig. 8 is the schematic diagram of the buffer storage according to shown by an exemplary embodiment.

Fig. 8 is please referred to, in this exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) Mapping table area MTZ is marked off in buffer storage 508, is configured to temporarily store from 406 institute of reproducible nonvolatile memorizer module The logical address of loading-physical address mapping table.In particular, memorizer control circuit unit 404 (or memory management circuitry 502) mapping table area MTZ can be also divided into first area Z1 and second area Z2, and first area Z1 and second area Z2 points It Ju You not continuous multiple cache units.Each cache unit is configured to temporarily store a logical address-physical address mapping table, and every One cache unit can be denoted as different conditions, such as update (dirty) state, not more new state (clean), invalid (invalid) state, storage (saving) state or loading (loading) state etc., to indicate the data in cache unit State.In this exemplary embodiment, a logical address-physical address mapping table size is 512B, therefore, each caching The size of unit is 512B.And the size of first area Z1 and second area Z2 can be a particular value, such as 64MB or 128MB. However, it is necessary to be appreciated that, in other exemplary embodiments, the size of cache unit can be according to actual logical address-physically Depending on the mapping table of location, and the size of first area Z1 and second area Z2 also visually actually uses demand and sets, and the present invention is simultaneously It is without restriction.

As shown in figure 8, first area Z1 has cache unit 810 (1-0)~810 (1-n), second area Z2 has caching Unit 810 (2-0)~810 (2-n).In this exemplary embodiment, memorizer control circuit unit 404 (or memory management electricity Road 502) multiple logical addresses-physical address mapping table can be carried from reproducible nonvolatile memorizer module 406 in advance Enter the mapping table area MTZ into buffer storage 508, and these logical addresses-physical address mapping table is distinctly kept in In the cache unit of one region Z1 and second area Z2.

Fig. 9 A~9F is the schematic diagram of the buffer storage supervisory method according to shown by an exemplary embodiment.

Fig. 9 A is please referred to, cache unit 810 (1-0)~810 (1-n) the difference register logic address-in the Z1 of first area Cache unit 810 (2-0)~810 (2-n) in physical address mapping table MT (0)~MT (n), second area Z2 is kept in respectively patrols Collect address-physical address mapping table MT (n+1)~MT (2n).For convenience of description, this exemplary embodiment be with first area Z1 with The cache unit of second area Z2 does not start to illustrate for more new state.When receiving write instruction from host system 11, this Write-in data are written to logical address for write instruction instruction, memorizer control circuit unit 404 (or memory management circuitry 502) logical address belonging to this logical address-physical address mapping table can be kept in the first area Z1 of mapping table area MTZ To be safeguarded.In more detail, memorizer control circuit unit 404 (or memory management circuitry 502) first judgement can be intended to write Whether logical address belonging to the logical address entered-physical address mapping table has been temporarily stored in first area Z1's or second area Z2 In cache unit.

It writes first data into when receiving instruction from host system to belonging to the first logical address-physical address mapping table When the first write instruction of the first logical address of MT (n+2), memorizer control circuit unit 404 (or memory management circuitry 502) the loaded mapping table area into buffer storage 508 the first logical address-physical address mapping table MT (n+2) is judged MTZ, and it is temporarily stored in the cache unit 810 (2-1) (below referring also to for the first cache unit) of second area Z2.Therefore, it deposits Memory control circuit unit 404 (or memory management circuitry 502) can write first data into duplicative is non-volatile and deposit First logical address mapped entity program unit in memory modules 406, and update and be temporarily stored in cache unit 810 (2-1) The first logical address-physical address mapping table MT (n+2).Also, memorizer control circuit unit 404 (or memory management Circuit 502) it can be by updated first logical address-physical address mapping table MT (n+2) from the cache unit of second area Z2 810 (2-1) are moved to first area Z1.

In this exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) can also set One index P1 is directed toward one of cache unit in the Z1 of first area, and this cache unit being pointed to is not to have updated shape State.Specifically, memorizer control circuit unit 404 (or memory management circuitry 502) can be according to more in the Z1 of first area The tandem of a cache unit sequentially judges whether not from front to back as more new state.As shown in Figure 9 A, due at this time All cache units in one region Z1 are not more new state, therefore, memorizer control circuit unit 404 (or memory Manage circuit 502) set first cache unit 810 (1-0) that the first index P1 is directed toward in the Z1 of first area.Later, it stores Device control circuit unit 404 (or memory management circuitry 502) can store updated logical address-according to the first index P1 Physical address mapping table.For example, memorizer control circuit unit 404 (or memory management circuitry 502) can be according to the first index P1 is by updated first logical address-physical address mapping table MT (n+2) from the cache unit 810 (2-1) of second area Z2 It moves into the cache unit 810 (1-0) of first area Z1 (below referring also to for the second cache unit).

Fig. 9 B is please referred to, updated first logical address-physical address mapping table MT (n+2) is moved to first area After in the cache unit 810 (1-0) of Z1, memorizer control circuit unit 404 (or memory management circuitry 502) can will be cached Unit 810 (1-0) is denoted as more new state.Then, memorizer control circuit unit 404 (or memory management circuitry 502) The latter that the cache unit 810 (1-0) that the first index P1 is directed toward in the Z1 of first area can be set is not the slow of more new state Memory cell.In this exemplary embodiment, the latter cache unit 810 (1-1) of the second cache unit 810 (1-0) is not i.e. for More new state, therefore, memorizer control circuit unit 404 (or memory management circuitry 502), which sets the first index P1 and is directed toward, to be delayed Memory cell 810 (1-1).In this exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) is also Originally the logical address in the cache unit 810 (1-0) for being temporarily stored in first area Z1-physical address mapping table MT (0) can be removed It moves in the cache unit 810 (2-1) of second area Z2.And in another exemplary embodiment, it can not also move and directly cover Fall logical address-physical address mapping table MT (0).

If the second data are written to belonging to the second logical address-physically at this point, receiving instruction from host system When the second write instruction of the second logical address of location mapping table MT (n), memorizer control circuit unit 404 (or memory pipe Reason circuit 502) judge the loaded mapping into buffer storage 508 of the second logical address-physical address mapping table MT (n) Table area MTZ, and it is temporarily stored in the cache unit 810 (1-n) (below referring also to for third cache unit) of first area Z1.Such as figure Shown in 9C, memorizer control circuit unit 404 (or memory management circuitry 502) the second data can be written non-to duplicative Second logical address mapped entity program unit in volatile 406, update are temporarily stored in cache unit 810 The second logical address-physical address mapping table MT (n) in (1-n), and be denoted as cache unit 810 (1-n) to have updated shape State.

If third data are written to belonging to third logical address-physically at this point, receiving instruction from host system When the third write instruction of the third logical address of location mapping table MT (k), memorizer control circuit unit 404 (or memory pipe Reason circuit 502) it judges third logical address-physical address mapping table MT (k) and is not yet loaded in buffer storage 508 Mapping table area MTZ.Therefore, memorizer control circuit unit 404 (or memory management circuitry 502) can be non-volatile from duplicative Third logical address-physical address mapping table MT (k) is loaded into mapping table area MTZ in property memory 406, and with the first index Cache unit 810 (1-1) (below referring also to for the 4th cache unit) in first area Z1 pointed by P1 keeps in third Logical address-physical address mapping table MT (k).As shown in fig. 9d, third logical address-physical address mapping table MT (k) is temporary There are in the cache unit 810 (1-1) in the Z1 of first area, and memorizer control circuit unit 404 (or memory management circuitry 502) third data are written into type nonvolatile 406.Memorizer control circuit unit 404 (or storage Device manages circuit 502) and it will be updated third logical address-physical address mapping table MT (k), and by 810 (1- of the 4th cache unit 1) it is denoted as more new state.Further, memorizer control circuit unit 404 (or memory management circuitry 502) can select The latter for taking the 4th cache unit 810 (1-1) in the Z1 of first area be not the cache unit 810 (1-2) of more new state with For keeping in next updated logical address-physical address mapping table, and sets the first index P1 and be directed toward cache unit 810 (1-2)。

If all cache units 810 (1-0)~810 (1-n) in the Z1 of first area are all denoted as more new state, Memorizer control circuit unit 404 (or memory management circuitry 502) will start copy-back operation, will be temporarily stored in first area Z1 All cache units 810 (1-0)~810 (1-n) in logical address-physical address mapping table restore to duplicative it is non-easily In the property lost memory module 406.

It is noted that it is above-mentioned about memorizer control circuit unit 404 (or memory management circuitry 502) by data It is written to the running of reproducible nonvolatile memorizer module 406, it can be before more new logical addresses-physical address mapping table Or execute later, the present invention is not limited thereto.

In this exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) can also set Two index P2 are directed toward one of cache unit in second area Z2.Specifically, memorizer control circuit unit 404 (or Memory management circuitry 502) the can be determined back to front according to the tandems of multiple cache units in second area Z2 The two index P2 cache units to be directed toward.It as shown in fig. 9e, can be from the 810 (2- of the last one cache unit in second area Z2 N) start, the second index P2 of setting is directed toward cache unit 810 (2-n).

If belonging to four logical addresses-physical address mapping table MT (s) at this point, receiving instruction from host system and reading The 4th logical address the 4th data first read instruction when, memorizer control circuit unit 404 (or memory management electricity Road 502) judge the mapping that four logical addresses-physical address mapping table MT (s) is not yet loaded in buffer storage 508 Table area MTZ.Therefore, memorizer control circuit unit 404 (or memory management circuitry 502) can be deposited from duplicative is non-volatile Four logical addresses-physical address mapping table MT (s) is loaded into mapping table area MTZ in reservoir 406, and with the second index P2 institute The cache unit 810 (2-n) (below referring also to for the 5th cache unit) of direction reflects to keep in four logical addresses-physical address Firing table MT (s).As shown in fig. 9f, it is temporarily stored in second area Z2 in four logical addresses-physical address mapping table MT (s) After in cache unit 810 (2-n), memorizer control circuit unit 404 (or memory management circuitry 502) can be according to the 4th Logical address-physical address mapping table MT (s) reads the 4th data being stored in type nonvolatile.Storage Device control circuit unit 404 (or memory management circuitry 502) and can set the second index P2 be directed toward second area Z2 in cache The previous cache unit of unit 810 (2-n), i.e. cache unit 810 (2- (n-1)).In this exemplary embodiment, if second When index P2 has pointed to first cache unit 810 (2-0) of second area Z2, memorizer control circuit unit 404 (or storage Device manages circuit 502) the last one cache unit 810 (2-n) of second area Z2 can be chosen as next second index P2 The cache unit to be directed toward.

If belonging to five logical addresses-physical address mapping table MT (n+ at this point, receiving instruction from host system and reading 1) when the second of the 5th data of the 5th logical address reads instruction, memorizer control circuit unit 404 (or memory management Circuit 502) it judges five logical addresses-physical address mapping table MT (n+1) and has been loaded on reflecting in buffer storage 508 Firing table area MTZ, and it is temporarily stored in the cache unit 810 (2-0) of second area Z2.As shown in fig. 9f, memorizer control circuit list First 404 (or memory management circuitries 502) are directly according to the 5th be temporarily stored in the cache unit 810 (2-0) of second area Z2 Logical address-physical address mapping table MT (n+1) reads the 5th data in reproducible nonvolatile memorizer module 406.

Figure 10 is the flow chart of the buffer storage supervisory method according to shown by an exemplary embodiment.

Please refer to Figure 10.In step S1001, memorizer control circuit unit 404 (or memory management circuitry 502) meeting Mapping table area is marked off in buffer storage 508.

In the step s 1003, memorizer control circuit unit 404 (or memory management circuitry 502) can be by mapping table area It is divided into the first area for being respectively provided with continuous multiple cache units and second area.

In step S1005, memorizer control circuit unit 404 (or memory management circuitry 502) is non-from duplicative Multiple logical addresses-physical address mapping table to first area and second area is loaded into volatile.Institute as above It states, each logical address being loaded into-physical address mapping table is the one of caching list being temporarily stored in first area One of cache unit in member or second area.

In step S1007, memorizer control circuit unit 404 (or memory management circuitry 502) is from host system 11 Write instruction is received, the instruction of this write instruction writes data into the logic for belonging to one logical address-physical address mapping table Address.

In step S1009, memorizer control circuit unit 404 (or memory management circuitry 502) judges this logically Whether logical address belonging to location-physical address mapping table has been temporarily stored in first area or second area.

In step S1011, if logical address belonging to this logical address-physical address mapping table has been temporarily stored in When in the cache unit (below referring also to for the first cache unit) in two regions, memorizer control circuit unit 404 (or memory Management circuit 502) it writes data into reproducible nonvolatile memorizer module, it updates belonging to this logical address logically Location-physical address mapping table moves updated logical address-physical address mapping table to the cache unit of first area In (below referring also to for the second cache unit), and move by updated logical address-physical address mapping table to After second cache unit in one region, the second cache unit is denoted as more new state.

In step S1013, if logical address belonging to this logical address-physical address mapping table has been temporarily stored in In the cache unit (below referring also to for third cache unit) in one region, memorizer control circuit unit 404 (or memory pipe Reason circuit 502) it writes data into reproducible nonvolatile memorizer module, it updates belonging to this logical address logically Location-physical address mapping table, and third cache unit is denoted as more new state.

If logical address belonging to this logical address-physical address mapping table is not yet temporarily stored in first area or second Region, in step S1015, memorizer control circuit unit 404 (or memory management circuitry 502) is non-volatile from duplicative Property memory module is loaded into logical address belonging to this logical address-physical address mapping table and is temporarily stored in the caching of first area In unit (below referring also to for the 4th cache unit), writes data into reproducible nonvolatile memorizer module, update Logical address belonging to this logical address-physical address mapping table, and the 4th cache unit is denoted as more new state.

In step S1017, if all cache units of first area are all denoted as more new state, memory Control circuit unit 404 (or memory management circuitry 502) will be temporarily stored in all cache units of first area logically Location-physical address mapping table restores in reproducible nonvolatile memorizer module.

In conclusion buffer storage supervisory method provided by the present invention, memorizer control circuit unit and memory Storage device is that the specific region with continuous cache unit is marked off in buffer storage, and the logic that will be updated Address-physical address mapping table concentration is kept in this specific region, in this way, work as the update in buffer storage Logical address-physical address mapping table when restoring to reproducible nonvolatile memorizer module, can be according to entity program The size for changing unit, updated logical address-physical address mapping table is written to entity journey directly from this specific region Sequence unit, and need not in addition execute the operation of duplication with collection.And by the way that this specific region is set as particular size, can keep away When exempting to carry out copy-back operation, the problem for causing system load overweight because the data volume that need to be handled is excessive, and then effectively promoted back Deposit the processing speed of operation.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution The range of scheme.

Claims (21)

1. a kind of buffer storage supervisory method, the buffer storage for a memory storage apparatus, which is characterized in that institute Memory storage apparatus is stated with a reproducible nonvolatile memorizer module, the buffer storage supervisory method includes:

A mapping table area is marked off in said buffer memory；

The mapping table zoning is divided into a first area and a second area, wherein the first area and the second area Respectively there are continuous multiple cache units；

Multiple logical addresses-physical address mapping table is loaded into from the reproducible nonvolatile memorizer module to described One region and the second area, wherein each logical address-physical address mapping table can be temporarily stored in firstth area One of the cache unit in domain or one of the cache unit of the second area；

From a host system receive one first write instruction, wherein first write instruction instruction by one first data be written to One first logical address, and first logical address belonging to first logical address-physical address mapping table is temporary There are in one first cache unit among the cache unit of the second area；

The first logical address-physical address mapping table is updated, the updated first logical address-physical address is reflected Firing table is moved into one second cache unit among the cache unit of the first area；

By the updated first logical address-physical address mapping table move to the first area cache unit it In second cache unit in after, second cache unit is denoted as a more new state；And

If all cache units of the first area are all denoted as the more new state, described first will be temporarily stored in Logical address-physical address mapping table in all cache units in region restores to the type nonvolatile In module.

2. buffer storage supervisory method according to claim 1, which is characterized in that further include:

It will be temporarily stored in another logical address-physical address mapping table in second cache unit of the first area originally It moves in first cache unit into the second area.

3. buffer storage supervisory method according to claim 1, which is characterized in that further include:

One second write instruction is received from the host system, wherein one second data are written for second write instruction instruction To one second logical address, and second logical address belonging to second logical address-physical address mapping table by It is temporarily stored in the third cache unit among the cache unit of the first area；And

The second logical address-physical address mapping table is updated, the third cache unit is denoted as described to have updated shape State.

4. buffer storage supervisory method according to claim 1, which is characterized in that further include:

A third write instruction is received from the host system, wherein one third data are written for third write instruction instruction To a third logical address, and a third logical address-physical address mapping table belonging to the third logical address is not yet It is loaded into the mapping table area；

Third logical address-physical address the mapping table is loaded into from the reproducible nonvolatile memorizer module to institute Mapping table area is stated, wherein third logical address-physical address mapping table is temporarily stored in the cache unit of the first area Among one the 4th cache unit in；And

Third logical address-physical address the mapping table is updated, the 4th cache unit is denoted as described to have updated shape State.

5. buffer storage supervisory method according to claim 1, which is characterized in that further include:

According to the sequence of the cache unit in the first area, choosing in the first area is not the more new state First cache unit as second cache unit, and set one first index and be directed toward second cache unit；With And

After second cache unit to be denoted as to the more new state, sets first index and be directed toward described first Another cache unit among the cache unit in region, wherein another described cache unit is second cache unit The latter is not the cache unit of the more new state.

6. buffer storage supervisory method according to claim 1, which is characterized in that further include:

One first is received from the host system and reads instruction, wherein the first reading instruction instruction reads one the 4th logically One the 4th data of location, and a four logical addresses-physical address mapping table belonging to the 4th logical address not yet carries Enter into the mapping table area；And

Four logical addresses-physical address the mapping table is loaded into from the reproducible nonvolatile memorizer module to institute Mapping table area is stated, and the four logical addresses-physical address mapping table has been temporarily stored in the caching list of the second area In one the 5th cache unit among member.

7. buffer storage supervisory method according to claim 6, which is characterized in that further include:

According to the sequence of the cache unit in the second area, the last one cache unit chosen in the second area is made For the 5th cache unit, and sets one second index and be directed toward the 5th cache unit；And

After the four logical addresses-physical address mapping table is temporarily stored in the 5th cache unit, described in setting Second index is directed toward the previous cache unit of the 5th cache unit in the second area.

8. a kind of memorizer control circuit unit, for controlling a reproducible nonvolatile memorizer module, which is characterized in that The memorizer control circuit unit includes:

One host interface, to be coupled to a host system；

One memory interface, to be coupled to the reproducible nonvolatile memorizer module；

One buffer storage is coupled to the host interface and the memory interface；And

One memory management circuitry is coupled to the host interface, the memory interface and the buffer storage, and uses To mark off a mapping table area in said buffer memory；

Wherein, the memory management circuitry is also to be divided into a first area and a second area for the mapping table zoning, Wherein the first area and the second area respectively have continuous multiple cache units,

Wherein, the memory management circuitry from the reproducible nonvolatile memorizer module also to be loaded into multiple patrol Address-physical address mapping table is collected to the first area and the second area, wherein each logical address-is physically Location mapping table can be temporarily stored in the cache unit of one of cache unit of the first area or the second area One of them,

Wherein, also to receive one first write instruction from the host system, described first writes the memory management circuitry Enter instruction instruction one first data are written to one first logical address, and one first is patrolled belonging to first logical address Address-physical address mapping table is collected to be temporarily stored in one first cache unit among the cache unit of the second area,

Wherein, the memory management circuitry will update also to update the first logical address-physical address mapping table The first logical address-physical address mapping table move among the cache unit of the first area one second caching In unit,

Wherein, it moves by the updated first logical address-physical address mapping table to the caching of the first area After in second cache unit among unit, the memory management circuitry is also to by the second cache unit mark It is shown as a more new state,

Wherein, if all cache units of the first area are all denoted as the more new state, the memory Logical address-physical address mapping table of the management circuit also will be temporarily stored in all cache units of the first area returns It deposits into the reproducible nonvolatile memorizer module.

9. memorizer control circuit unit according to claim 8, which is characterized in that the memory management circuitry is also used Another logical address-physical address mapping table being temporarily stored in second cache unit of the first area originally to be removed It moves in first cache unit in the second area.

10. memorizer control circuit unit according to claim 8, which is characterized in that the memory management circuitry is also To receive one second write instruction from the host system, one second data are written to one for the second write instruction instruction Second logical address, and second logical address belonging to second logical address-physical address mapping table is temporarily stored in In a third cache unit among the cache unit of the first area,

Wherein, the memory management circuitry is also to update the second logical address-physical address mapping table, by described Three cache units are denoted as the more new state.

11. memorizer control circuit unit according to claim 8, which is characterized in that the memory management circuitry is also To receive a third write instruction from the host system, one third data are written to one for the third write instruction instruction Third logical address, and a third logical address-physical address mapping table belonging to the third logical address is not yet loaded into Extremely in the mapping table area,

Wherein, the memory management circuitry from the reproducible nonvolatile memorizer module also to be loaded into described Three logical addresses-physical address mapping table is to the mapping table area, wherein third logical address-physical address mapping table quilt It is temporarily stored in one the 4th cache unit among the cache unit of the first area,

Wherein, the memory management circuitry is also to update the third logical address-physical address mapping table, by described Four cache units are denoted as the more new state.

12. memorizer control circuit unit according to claim 8, which is characterized in that the memory management circuitry is also To the sequence according to the cache unit in the first area, choosing in the first area is not the more new state First cache unit as second cache unit, and set one first index and be directed toward second cache unit,

Wherein, after second cache unit to be denoted as to the more new state, the memory management circuitry is also used To set another cache unit that first index is directed toward among the cache unit of the first area, wherein described another A cache unit be second cache unit it is next be not the more new state cache unit.

13. memorizer control circuit unit according to claim 8, which is characterized in that the memory management circuitry is also Instruction is read to receive one first from the host system, described first, which reads instruction instruction, reads one the 4th logical address One the 4th data, and a four logical addresses-physical address mapping table belonging to the 4th logical address is not yet loaded into In the mapping table area,

Wherein, the memory management circuitry from the reproducible nonvolatile memorizer module also to be loaded into described Four logical addresses-physical address mapping table, wherein the four logical addresses-physical address mapping table is temporarily stored in described second In one the 5th cache unit among the cache unit in region.

14. memorizer control circuit unit according to claim 13, which is characterized in that the memory management circuitry is also To the sequence according to the cache unit in the second area, the last one cache unit chosen in the second area is made For the 5th cache unit, and sets one second index and is directed toward the 5th cache unit,

Wherein, described after the four logical addresses-physical address mapping table is temporarily stored in the 5th cache unit Memory management circuitry also to set the 5th cache unit that second index is directed toward in the second area before One cache unit.

15. a kind of memory storage apparatus characterized by comprising

One connecting interface unit, to be coupled to a host system；

One reproducible nonvolatile memorizer module；And

One memorizer control circuit unit is coupled to the connecting interface unit and the type nonvolatile mould Block, and including a buffer storage, and to mark off a mapping table area in said buffer memory,

Wherein, the memorizer control circuit unit is also to be divided into a first area and one second area for the mapping table zoning Domain, wherein the first area and the second area respectively have continuous multiple cache units,

Wherein, the memorizer control circuit unit is also more to be loaded into from the reproducible nonvolatile memorizer module A logical address-physical address mapping table is to the first area and the second area, wherein each logical address-reality Body address mapping table can be temporarily stored in the caching list of one of cache unit of the first area or the second area One of member,

Wherein, the memorizer control circuit unit is also to receive one first write instruction from the host system, and described the One first data are written to one first logical address the instruction of one write instruction, and one the belonging to first logical address One logical address-physical address mapping table is temporarily stored in one first cache unit among the cache unit of the second area In,

Wherein, the memorizer control circuit unit, will also to update the first logical address-physical address mapping table The the first logical address-physical address mapping table updated is moved to one second among the cache unit of the first area In cache unit,

Wherein, it moves by the updated first logical address-physical address mapping table to the caching of the first area After in second cache unit among unit, the memorizer control circuit unit is also to single by second caching Member is denoted as a more new state,

Wherein, if all cache units of the first area are all denoted as the more new state, the memory Logical address-physical address mapping of the control circuit unit also will be temporarily stored in all cache units of the first area Table restores in the reproducible nonvolatile memorizer module.

16. memory storage apparatus according to claim 15, which is characterized in that the memorizer control circuit unit is also Another logical address-physical address mapping table in second cache unit of the first area will be temporarily stored in originally It moves in first cache unit into the second area.

17. memory storage apparatus according to claim 15, which is characterized in that the memorizer control circuit unit is also To receive one second write instruction from the host system, one second data are written to one for the second write instruction instruction Second logical address, and second logical address belonging to second logical address-physical address mapping table is temporarily stored in In a third cache unit among the cache unit of the first area,

Wherein, the memorizer control circuit unit is also to update the second logical address-physical address mapping table, by institute It states third cache unit and is denoted as the more new state.

18. memory storage apparatus according to claim 15, which is characterized in that the memorizer control circuit unit is also To receive a third write instruction from the host system, one third data are written to one for the third write instruction instruction Third logical address, and a third logical address-physical address mapping table belonging to the third logical address is not yet loaded into Extremely in the mapping table area,

Wherein, the memorizer control circuit unit from the reproducible nonvolatile memorizer module also to be loaded into institute Third logical address-physical address mapping table is stated to the mapping table area, wherein third logical address-physical address mapping Table is temporarily stored in one the 4th cache unit among the cache unit of the first area,

Wherein, the memorizer control circuit unit is also to update the third logical address-physical address mapping table, by institute It states the 4th cache unit and is denoted as the more new state.

19. memory storage apparatus according to claim 15, which is characterized in that the memorizer control circuit unit is also To the sequence according to the cache unit in the first area, choosing in the first area is not the more new state First cache unit as second cache unit, and set one first index and be directed toward second cache unit,

Wherein, after second cache unit to be denoted as to the more new state, the memorizer control circuit unit Another cache unit being also directed toward among the cache unit of the first area to set first index, wherein described Another cache unit be second cache unit it is next be not the more new state cache unit.

20. memory storage apparatus according to claim 15, which is characterized in that the memorizer control circuit unit is also Instruction is read to receive one first from the host system, described first, which reads instruction instruction, reads one the 4th logical address One the 4th data, and a four logical addresses-physical address mapping table belonging to the 4th logical address is not yet loaded into In the mapping table area,

Wherein, the memorizer control circuit unit from the reproducible nonvolatile memorizer module also to be loaded into institute State four logical addresses-physical address mapping table, wherein the four logical addresses-physical address mapping table be temporarily stored in it is described In one the 5th cache unit among the cache unit of second area.

21. memory storage apparatus according to claim 20, which is characterized in that the memorizer control circuit unit is also To the sequence according to the cache unit in the second area, the last one cache unit chosen in the second area is made For the 5th cache unit, and sets one second index and is directed toward the 5th cache unit,

Wherein, described after the four logical addresses-physical address mapping table is temporarily stored in the 5th cache unit The 5th cache unit that memorizer control circuit unit is also directed toward in the second area to set second index Previous cache unit.