CN106549054A - FET and preparation method thereof - Google Patents
FET and preparation method thereof Download PDFInfo
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- CN106549054A CN106549054A CN201510595003.9A CN201510595003A CN106549054A CN 106549054 A CN106549054 A CN 106549054A CN 201510595003 A CN201510595003 A CN 201510595003A CN 106549054 A CN106549054 A CN 106549054A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Abstract
A kind of FET, including：Multiple fins, extend in a first direction on substrate, the source-drain area of channel region and channel region both sides including high mobility material；Multiple gate stacks, extend in a second direction, around each channel region；Separation layer, between substrate and channel region.High mobility FET according to the present invention and preparation method thereof, defines autoregistration isolation by the selective etch oxidation to cushion below mobility channel, improves device drive ability and reliability low-cost high-efficiency.
Description
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing method, more particularly to a kind of rear grid structure
High mobility FET of middle autoregistration isolation and preparation method thereof.
Background technology
In current sub- 20nm technologies, three-dimensional multi-gate device (FinFET or Tri-gate) is
Main device architecture, this structure enhance grid control ability, inhibit electric leakage and short ditch
Channel effect.
For example, the MOSFET of double gate SOI structure and traditional single grid body Si or SOI
MOSFET is compared, and short-channel effect (SCE) and leakage can be suppressed to cause induced barrier to reduce
(DIBL) effect, with lower junction capacity, can realize that raceway groove is lightly doped, can be by setting
The work function for putting metal gates carrys out adjusting threshold voltage, can obtain about 2 times of driving current, reduces
Requirement for effective gate oxide thickness (EOT).And tri-gate devices are compared with double-gated devices, grid
Pole encloses channel region top surface and two sides, and grid control ability is higher.Further, entirely
It is more advantageous around nano wire multi-gate device.
Single gate device is compared, double-gated devices are advantageous；Double grid is compared, tri-gate devices are advantageous；Phase
Than three grid, loopful is advantageous around nano wire multi-gate device；But the manufacture work of nano wire multi-gate device
Skill is typically complex, incompatible with main flow FinFETal technique.
On the other hand, although ring gate device has more preferable grid control function, can more effectively control short ditch
Channel effect, has more advantage during the reduction of sub- 14 nanometer technology, but a key issue is
Due to small conducting channel, more driving currents can not be provided in the equivalent silicon area of plane.
For this purpose, prior art generally in three-dimensional FinFET integrated heterogeneous mobility channel being conducive to more
Device and circuit performance are improved under small size.Conventional method is extension or selective epitaxy on substrate
High mobility material, this is unfavorable for that CMOS is integrated, and grid prevailing technology poor compatibility after MG/HK,
It is many compared with thick buffering substrate defects, electric leakage is easily introduced in raceway groove.
The content of the invention
From the above mentioned, it is an object of the invention to overcome above-mentioned technical difficulty, a kind of rear grid are proposed
High mobility FET of autoregistration isolation and preparation method thereof in structure, so as to improve device drive
Performance and reliability.
For this purpose, the invention provides a kind of FET, including：Multiple fins, along on substrate
One direction extends, the source-drain area of channel region and channel region both sides including high mobility material；
Multiple gate stacks, extend in a second direction, around each channel region；Separation layer, positioned at lining
Between bottom and channel region.
Wherein, cushion is further included between source-drain area and substrate；Optionally, cushion
Lattice paprmeter is between substrate and channel region.
Wherein, source-drain area includes following at least one：Source drain extension area, source and drain heavily doped region,
Lifting source-drain area.
Wherein, high mobility material is selected from Ge, SiGe, SiC, SiGeC, iii-v chemical combination
Any one of thing semiconductor, II-VII compound semiconductors and combinations thereof.
Wherein, separation layer is oxide and/or nitride.
Present invention also offers a kind of FET manufacture methods, including step：The extension successively on substrate
The channel layer of grown buffer layer and high mobility material；Etching channel layer and cushion are formed along the
Multiple fins that one direction extends；The dummy grid for extending in a second direction is formed on multiple fins
Stacking；Dummy grid stacking is removed, the gate openings of exposure channel layer are formed；Perform oxidation and/
Or nitriding process, it is changed into the buffer layer part below channel layer in gate openings or fully
Separation layer；Gate stack is formed in gate openings.
Wherein, the lattice paprmeter of cushion is between substrate and channel region.
Further include to form source-drain area in the channel layer of fin before removing dummy grid stacking；
Optionally, source-drain area includes source drain extension area, source and drain heavily doped region, lifting source-drain area at least
One.
Wherein, further include before performing oxidation and/or nitriding process, laterally etched grid is opened
Cushion in mouthful below channel layer so that residual buffer layer top width is less than channel layer bottom
Width.
Wherein, high mobility material is selected from Ge, SiGe, SiC, SiGeC, iii-v chemical combination
Any one of thing semiconductor, II-VII compound semiconductors and combinations thereof.
High mobility FET according to the present invention and preparation method thereof, by mobility channel
The selective etch oxidation of lower section cushion defines autoregistration isolation, carries low-cost high-efficiency
High device drive ability and reliability.
Description of the drawings
Referring to the drawings describing technical scheme in detail, wherein：
Fig. 1 (Figure 1A and Figure 1B) to Fig. 8 (Fig. 8 A and Fig. 8 B) is according to the present invention's
The generalized section of each step of nanowire MOS transistor manufacture method is stacked, wherein certain figure A is
Along the sectional view perpendicular to channel direction, certain figure B is along the sectional view parallel to channel direction；
And
Fig. 9 is the schematic perspective view of the FinFET structure according to the present invention.
Specific embodiment
The technology of the present invention side is described in detail referring to the drawings and with reference to schematic embodiment
The feature and its technique effect of case, improves device drive ability with disclosing low-cost high-efficiency
And the high mobility FET and its manufacture method of reliability.It is pointed out that similar is attached
Icon note represents similar structure, term " first " use herein, " second ",
" on ", D score etc. can be used to modify various device architectures or manufacturing process.These modifications
Space, order or the layer of modified device architecture or manufacturing process are not implied that unless stated otherwise
Level relation.
Fig. 9 show the solid of the stacking nanowire MOS transistor according to present invention manufacture and shows
It is intended to, wherein stacking what is extended in a first direction on nanowire MOS transistor, including substrate
Multiple nano wire stackings, extend and span the multiple of each nano wire stacking in a second direction
Metal gates, the nano wire for extending in a first direction stack multiple source-drain areas of both sides, positioned at many
Multiple channel regions that nano wire stacking between individual source-drain area is constituted, wherein metal gates are around ditch
Road area.Below by with initial reference to Fig. 1 to Fig. 8 describing each sectional view of manufacture method, finally
The device architecture of Fig. 9 will be later described in further detail.
Especially, certain figure A is perpendicular to channel direction (X-X ' in a second direction) along Fig. 9 below
Sectional view, certain figure B is parallel to channel direction (Y-Y ' in the first direction) along Fig. 9
Sectional view.
With reference to Figure 1A and Figure 1B, stress relaxation cushion (SRB) is formed on substrate 1
1B and channel layer 1C.Substrate 1 is provided, substrate 1 is needed and reasonable selection according to device application,
May include monocrystalline silicon (Si), monocrystal germanium (Ge), strained silicon (Strained Si),
Germanium silicon (SiGe), or compound semiconductor materials, such as gallium nitride (GaN), arsenic
Gallium (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon-based semiconductors are for example
Graphene, SiC, carbon nanotube etc..For the consideration compatible with CMOS technology, substrate 1
Preferably body Si.By PECVD, HDPCVD, UHVCVD, MOCVD, MBE,
The techniques such as ALD, epitaxial growth SRB layer 1B and channel layer 1C successively on substrate 1, its
The carrier mobility of middle channel layer 1C is more than substrate 1, and the lattice paprmeter of SRB layer 1B
Between channel layer 1C and substrate 1.In a preferred embodiment of the invention, channel layer 1C
Material is Ge, SiGe, SiC, SiGeC, Group III-V compound semiconductor, II-VII races
Any one of compound semiconductor and combinations thereof, be selected from Ge, SiGe, SiC, SiGeC,
SiGeSn、SiGaN、SiGaP、SiGaAs、InSiN、InSiP、InSiAs、InSiSb、
Any one of GaN, InSb, InP, InAs, GaAs, SiInGaAs and combinations thereof.SRB
Layer 1B materials can also selected from above-mentioned material scope be also Ge, SiGe, SiC, SiGeC,
Any one of Group III-V compound semiconductor, II-VII compound semiconductors and combinations thereof, and
And lattice paprmeter is between channel layer 1C and substrate 1.In a preferred embodiment of the invention
In, substrate 1 is Si, and SRB layer is Si1-xGexOr Si1-yCy, channel layer 1C be Ge,
Si1-zGez、Si1-m-nGemCn, wherein x, y, z, m, n be all higher than equal to 0 less than etc.
X and/or y is preferably more than less than 1, z more than 0 in 1, m and n sums.Due to selecting
Appropriate lattice paprmeter, SRB layer 1B will reduce high mobility material channel layer 1C with lining
Lattice mismatch between bottom 1, so as to reduce dislocation, interface defect density, improves raceway groove
Layer film growth quality, is beneficial to improve the reliability of device.
With reference to Fig. 2A and Fig. 2 B, etching channel layer 1C, SRB layer 1B and substrate 1, formed
The multiple fin structures for extending in a first direction, wherein first direction prolong for future device channel region
Stretch direction.The photoresist figure for extending in a first direction is formed on laminated construction 1/1B/1C for example
Shape (not shown), is mask stack accordingly, forms multiple along first party in substrate 1
Constituted to 1 material of remaining substrate between the groove 1G and groove 1G of parallel distribution
Fin bottom 1F, leaves channel layer 1C's and SRB layer 1B on the top of fin bottom 1F
Lines.The depth-to-width ratio of groove 1G is preferably more than 5:1.Preferably, in multiple fin structures
Deposited atop hard mask layer (not shown), its material can be silica, silicon nitride, nitrogen
Silica and combinations thereof, and preferably silicon nitride.
Reference picture 3A and Fig. 3 B, in the groove 1G between fin structure by PECVD,
The process deposits such as HDPCVD, RTO (rapid thermal oxidation) filling material be, for example, silica,
Silicon oxynitride, silicon oxide carbide, low k's (low-k) etc. is dielectrically separated from dielectric layer, so as to constitute
Shallow trench isolation (STI) 2.Low-k materials include but is not limited to organic low-k materials and (for example contain
The organic polymer of aryl or many yuan of rings), (such as amorphous carbon nitrogen is thin for inorganic low-k material
Film, polycrystalline boron nitrogen film, fluorine silica glass, BSG, PSG, BPSG), porous low k material
Material (three oxygen alkane (SSQ) Quito hole low-k materials of such as two silicon, porous silica, porous
SiOCH, mix C silica, to mix F porous amorphous carbon, porous diamond, porous organic
Polymer).Optional, STI isolation oxides are negative expansion dielectric material, such as calcium titanium
Ore deposit type oxide, such as including Bi0.95La0.05NiO3、BiNiO3、ZrW2O8；Or STI
Isolation oxide is positive thermal expansion dielectric material, for example, frame material, is such as included
Ag3[Co(CN)6], thus STI isolation oxides are by the positivity during following process or negative
Property expansion and further increase channel region stress, further increase carrier mobility.Such as
Shown in Fig. 3 A, (etch-back) and/or cmp planarizationization process are carved by returning so that STI 2
Top be preferably lower than at the top of SRB layer 1B, and higher than the bottom of SRB layer 1B, so as to
Guarantee to be effectively isolated substrate, reduce substrate leakage currents, prevent substrate break-through, while and revealing
Go out channel layer 1C and be beneficial to when being subsequently formed gate stack to reduce parasitic capacitance.
Reference picture 4A and Fig. 4 B, formed extend in a second direction, on the fin structure
Dummy grid stacks 3A/3B, and in dummy grid stacks the channel layer 1C of both sides forms source-drain area.
First, form dummy grid stacking.For example by LPCVD, PECVD, evaporate, splash
Techniques such as (magnetron sputterings) is penetrated, bed course 3A and dummy gate layer 3B, and photoetching/etching shape is formed
Into the dummy grid stacking lines for extending in a second direction.Bed course 3A is used to protect channel layer 1C tables
Face, surface defect density increase, material is avoided in subsequent etching oxidizing process for example, to aoxidize
Silicon, silicon nitride, non-crystalline silicon, amorphous germanium, amorphous carbon, SiOC, low-k materials etc. and combinations thereof,
Preferably to distinguish with 2 materials of STI, so as to avoid during subsequent etching by unexpectedly
Remove.Dummy gate layer 3B material is, for example, polysilicon, non-crystalline silicon, microcrystal silicon, amorphous carbon, many
Brilliant germanium, amorphous germanium etc. and combinations thereof.
Secondly, form source-drain area.In a preferred embodiment of the invention, directly to channel layer
1C is doped and forms source-drain area, namely is first performed with dummy grid stacking 3A/3B as mask light
Doped ions inject the source drain extension area 1LS to form low concentration shallow junction deep (namely LDD structures)
And 1LD, subsequently silicon nitride, DLC amorphous carbon (DLC) are formed in dummy grid stacking both sides
Etc. the grid curb wall 3C of material, heavy doping ion is performed as mask with grid curb wall and injects to form height
Source and drain the heavily doped region 1HS and 1HD of the big junction depth of concentration, it is outer optionally on heavy-doped source drain region
Prolong to form lifting source-drain area 1ES and 1ED to reduce source-drain series resistance.It is another excellent in the present invention
In selecting embodiment, before injection doping forms source-drain area, mask selection is stacked as with dummy grid first
Property etching channel layer 1C, the channel layer 1C for removing dummy grid stacking both sides in the first direction formed
The source and drain groove (not shown) of exposure SRB layer 1B, and only retain the ditch of dummy grid stacking lower section
Channel layer 1C is used as the final channel region of device, subsequently other Gao Qian of epitaxial growth in source and drain groove
Shifting rate material (preferably synchronous to adulterate) forms source-drain area 1S and 1D, subsequently re-forms Fig. 4 B
Shown other source-drain area parts.The ionic type of injection doping is selected according to MOSFET types
Take, such as PMOS is As, P, Sb, Sn etc., for NMOS is B, BF2、
Be, In, Ga etc..Preferably, after forming source-drain area, metallic silicon is formed on source-drain area
Compound (not shown) with reduce interface potential barrier, reduce source-drain contact resistance.
Reference picture 5A and Fig. 5 B, selective etch remove dummy grid stacking.Lead on whole device
Cross the interlayer dielectric layer (ILD) that the techniques such as spin coating, spraying, serigraphy, CVD form low-k materials
4.Cmp planarization ILD 4 is until exposure dummy gate layer 3B.Selective etch removes dummy gate layer
3B and bed course 3A, until forming gate openings 4G of exposure channel layer 1C.Dummy gate layer 3B
For Si (amorphous, crystallite, polycrystalline) when, from KOH, TMAH wet etching, layer 3B is
During amorphous carbon, from oxygen plasma dry etching.Carved from HF bases when bed course 3A is silica
Erosion agent wet etching, selects hot phosphoric acid when layer 3A is silicon nitride.
Optionally, reference picture 6A and Fig. 6 B, laterally etched SRB layer 1B, under channel layer 1C
The SRB layer 1B both sides of side form depression 1R.For example can from strong oxidizer (hydrogen peroxide,
Plasma water ozoniferous) and strong acid (nitric acid, sulfuric acid) combination wet etching semiconductor
The layer 1B of material.Or carbon fluorine-based etching gas (fluorohydrocarbon C can be adjustedxHyFz) proportioning
So that etching speed of the etching gas to residual fin 1F at the top of channel layer 1C, STI 2, substrate 1
Rate is much smaller than the etch rate to SRB layer 1B, and the lateral quarter preferably to SRB layer 1B
Erosion speed is more than vertical etch rate.Depression 1R that etching is formed can be square as shown in Figure 6A
Shape is square, or and trapezoidal, inverted trapezoidal, Σ shapes (multistage broken line is connected), C-shaped are (super
Cross 1/2 curved surface, curved surface can be disc, ellipsoid, hyperboloid), D-shaped (1/2 curved surface, it is bent
Face can be disc, ellipsoid, hyperboloid).Preferably, etching stopping point is chosen so that recessed
The bottom of sunken 1R is less than the top of STI 2 or flushes, and thus effectively ensures that remaining SRB
Layer 1B is sufficiently narrow strengthening subsequent oxidation/efficiency of nitridation.
Reference picture 7A and Fig. 7 B, perform oxidation and/or nitriding process so that SRB layer 1B parts
Ground is completely transformed into separation layer 5.In (such as O containing oxidizing gases2、O3、NO2、
CO2、H2) or nitriability gas (N2, N O2O、NO、NH3) atmosphere under, heating
High-temperature process so that the semiconductive material portion of SRB layer 1B is fully changed into dielectric material
Separation layer 5.Such as 600～1300 DEG C of heat treatment temperature, time such as 10min～2h.Every
5 material of absciss layer such as silica, germanium oxide, silicon germanium oxide etc..As shown in Fig. 7 A, 7B,
5 top width of separation layer is less than channel layer 1C bottom widths, it is ensured that future gate is stacked three
Face ring improves device drive control performance around channel layer is surrounded.
Reference picture 8A and Fig. 8 B, form gate stack in gate openings 4G.Pass through
The techniques such as PECVD, MOCVD, MBE, ALD, evaporation, sputtering, in gate openings
The gate insulator 6A and the grid conducting layer of metal material of high-g value are sequentially depositing in 4G
6B, constitutes gate stack structure.High-g value is included selected from HfO2、
HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx、HfLaSiOx
Hafnium sill (wherein, each material is different according to multi-element metal component proportion and chemical valence,
Oxygen atom content x can Reasonable adjustment, for example can be 1～6 and be not limited to integer), or bag
Include selected from ZrO2、La2O3、LaAlO3、TiO2、Y2O3Rare earth base high K dielectric material,
Or including Al2O3, with the composite bed of its above-mentioned material.Grid conducting layer then can for polysilicon,
Poly-SiGe or metal, wherein metal may include Co, Ni, Cu, Al, Pd, Pt, Ru,
The metal simple-substances such as Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La,
Or the nitride of the alloy and these metals of these metals, can also be doped with grid conducting layer
The elements such as C, F, N, O, B, P, As are adjusting work function.Grid conducting layer and grid
Nitride is formed by conventional methods such as PVD, CVD, ALD further preferably between insulating barrier
Barrier layer (not shown), barrier layer material are MxNy、MxSiyNz、MxAlyNz、MaAlxSiyNz,
Wherein M is Ta, Ti, Hf, Zr, Mo, W or other elements.It is highly preferred that grid grid
Pole conductive layer not only with lamination layer structure stacked up and down, can also be adopted and be mixed with barrier layer
Injection doping Rotating fields, namely constitute the material on grid conducting layer and barrier layer while being deposited on
On gate insulator, therefore grid conducting layer includes the material on above-mentioned barrier layer.Cmp planarization
Change gate stack structure until exposure ILD 4.Hereafter, according to standard technology, in ILD 4
The through source-drain area 1S/D of etching source and drain contact hole (not shown), deposits in source and drain contact hole
The barrier layer of metal nitride and the conductive layer of metal material, form source and drain contact plug and (do not show
Go out).
The stereogram of the device architecture for eventually forming as shown in figure 9, including：Along first on substrate
The channel region of the high mobility material that direction extends, extends in a second direction and spans each
Multiple metal gates of channel region, multiple source and drain of the channel region both sides for extending in a first direction
Area, wherein metal gates also have the isolated area of dielectric material around channel region below channel region.
The material and geometry of above-mentioned these structures is described in detail in method description, therefore here is no longer
Repeat.
High mobility FET according to the present invention and preparation method thereof, by mobility channel
The selective etch oxidation of lower section cushion defines autoregistration isolation, carries low-cost high-efficiency
High device drive ability and reliability.
Although with reference to one or more exemplary embodiments explanation present invention, people in the art
Member could be aware that and various suitable changes are made without departing from the scope of the invention and to device architecture
And equivalents.Additionally, by disclosed teaching can make many can be adapted to particular condition or
The modification of material is without deviating from the scope of the invention.Therefore, the purpose of the present invention does not lie in and is limited to
It is as realizing the preferred forms of the present invention and disclosed specific embodiment, and disclosed
Device architecture and its manufacture method will include all embodiments for falling within the scope of the present invention.
Claims (10)
1. a kind of FET, including：
Multiple fins, extend in a first direction on substrate, including the raceway groove of high mobility material
Area and the source-drain area of channel region both sides；
Multiple gate stacks, extend in a second direction, around each channel region；
Separation layer, between substrate and channel region.
2. FET as claimed in claim 1, wherein, buffering is further included between source-drain area and substrate
Layer；Optionally, the lattice paprmeter of cushion is between substrate and channel region.
3. FET as claimed in claim 1, wherein, source-drain area includes following at least one：Source and drain is prolonged
Stretch area, source and drain heavily doped region, lifting source-drain area.
4. FET as claimed in claim 1, wherein, high mobility material selected from Ge, SiGe, SiC,
SiGeC, Group III-V compound semiconductor, II-VII compound semiconductors any one and
Its combination.
5. FET as claimed in claim 1, wherein, separation layer is oxide and/or nitride.
6. a kind of FET manufacture methods, including step：
The channel layer of epitaxial growth buffer and high mobility material successively on substrate；
Etching channel layer and cushion form the multiple fins for extending in a first direction；
The dummy grid stacking for extending in a second direction is formed on multiple fins；
Dummy grid stacking is removed, the gate openings of exposure channel layer are formed；
Oxidation and/or nitriding process are performed, by the buffer layer part below channel layer in gate openings
Or fully it is changed into separation layer；
Gate stack is formed in gate openings.
7. method as claimed in claim 6, wherein, the lattice paprmeter of cushion is between substrate and raceway groove
Between area.
8. method as claimed in claim 6, wherein, further include before removing dummy grid stacking
Source-drain area is formed in the channel layer of fin；Optionally, source-drain area include source drain extension area,
At least one of source and drain heavily doped region, lifting source-drain area.
9. method as claimed in claim 6, wherein, perform taking a step forward for oxidation and/or nitriding process
Including the cushion in laterally etched gate openings below channel layer so that residual buffer
Layer top width is less than channel layer bottom width.
10. method as claimed in claim 6, wherein, high mobility material selected from Ge, SiGe, SiC,
Any one of SiGeC, Group III-V compound semiconductor, II-VII compound semiconductors
And combinations thereof.
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| CN110534569A (en) * | 2018-05-25 | 2019-12-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN111599757A (en) * | 2020-06-03 | 2020-08-28 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| WO2023065549A1 (en) * | 2021-10-18 | 2023-04-27 | 长鑫存储技术有限公司 | Semiconductor device, and preparation method therefor and use thereof |
| EP4199117A4 (en) * | 2021-10-18 | 2023-08-23 | Changxin Memory Technologies, Inc. | Semiconductor device, and preparation method therefor and use thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110534569A (en) * | 2018-05-25 | 2019-12-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN110534569B (en) * | 2018-05-25 | 2023-09-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN111599757A (en) * | 2020-06-03 | 2020-08-28 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
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| EP4199117A4 (en) * | 2021-10-18 | 2023-08-23 | Changxin Memory Technologies, Inc. | Semiconductor device, and preparation method therefor and use thereof |
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Application publication date: 20170329 |