CN106528311A - Embedded system and control method thereof - Google Patents
Embedded system and control method thereof Download PDFInfo
- Publication number
- CN106528311A CN106528311A CN201610864377.0A CN201610864377A CN106528311A CN 106528311 A CN106528311 A CN 106528311A CN 201610864377 A CN201610864377 A CN 201610864377A CN 106528311 A CN106528311 A CN 106528311A
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- Prior art keywords
- chip
- operation mark
- register
- change
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0733—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a data processing system embedded in an image processing device, e.g. printer, facsimile, scanner
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
Abstract
The invention discloses an embedded system and a control method thereof. The embedded system comprises a system on chip and a monitoring chip, wherein the monitoring chip is connected to the system on chip through a data bus and is connected to a reset terminal of the system on chip through a control line; during a running period, the system on chip reports running identification to the monitoring chip; and the monitoring chip judges a running state of the system on chip according to the running identification, generates a reset signal when the system on chip is abnormal, and sends the reset signal to the reset terminal so that the system on chip restarts. The embedded system improves the system reliability by use of the peripheral monitoring chip.
Description
Technical field
The present invention relates to processor chips system, more particularly, to embedded system and its control method.
Background technology
With the development of semiconductor technology, embedded system is used widely.Embedded system includes microprocessor, outer
Enclose hardware device, operating system and user application.With the development of chip fabrication techniques, on a single chip can be with
The hardware and software part of integrated embedded system, forms on-chip system (SOC).SOC is had been developed as sector application
The various upper mini system of customization.For example, the application processor for generally adopting in smart mobile phone and BBP difference
It is different SOC systems.
Program operation exception is likely to occur in embedded systems, such as because being likely to occur program race by extraneous interference
Winged phenomenon, causes system operation abnormal.Program fleet refers to that the value of program counter deviates predetermined value, causes the fortune of program
Row result malfunctions.As shown in figure 1, on-chip system SOC can include central processing unit CPU and digital house dog WDT, so as to
The abnormal case of program fleet makes system reset when occurring so that system can be always maintained at normal work.
Digital house dog WDT includes counter 110.During system operation, central processing unit CPU operation drives journey
Sequence, initializes to digital house dog WDT, configures counter, opens and counts.Counter to house dog at regular intervals
It is zeroed out, referred to as feeds dog.Under normal circumstances, spilling of hello the dog time interval of central processing unit CPU less than counter
Time, digital house dog WDT will not carry out system reset.When system exception, central processing unit CPU can not be normally carried out feeding
Dog operates, feeding after the dog time beyond setting, counter overflow.Digital house dog WDT forces central processing unit CPU to reset.
It is after central processing unit CPU is restarted, again normal to run, so as to ensure that embedded system is extensive from software, the mistake of hardware
It is multiple to run to normal.
Although the above-mentioned scheme for being internally integrated house dog in SOC combines the high and flexible advantage of integrated level, normal
Under the environmental condition of rule, the exception of program fleet can be prevented.But when embedded system needs to be applied to harsh environment
Under the conditions of, such as more high/low operating temperature, the counting of abnormal of digital house dog WDT itself may cause mistakenly frequently weight
Starting system, so that meet the requirement of practical application.Now optional application scheme is but the technical grade using technical grade SOC
The price of SOC is high, causes cost to be substantially improved.
Therefore, it is desirable to the reliability of embedded system can be improved at low cost.
The content of the invention
In view of the above problems, it is an object of the invention to provide it is a kind of using system exception on peripheral monitoring chip detection lug and
Restart the embedded system and its control method of system.
According to an aspect of the present invention, there is provided a kind of embedded system, including：On-chip system, the on-chip system include
CPU and the first register；And monitoring chip, the monitoring chip include detect judge module and second deposit
Device, wherein, the monitoring chip is connected to the on-chip system via data/address bus, and is connected to described via control line
The reset terminal of upper system, the on-chip system is in run duration to monitoring chip report operation mark, the monitoring chip
The running status of the on-chip system is judged according to the operation mark, and is produced when system occurs abnormal on said sheets multiple
Position signal, and reset signal is sent to the reset terminal so that the on-chip system is restarted.
Preferably, when the change of the operation mark is consistent with performance of expected change, judge the on-chip system normal operation,
When the change of the operation mark is inconsistent with performance of expected change, the on-chip system operation exception is judged.
Preferably, the CPU of the on-chip system is write in first register in run duration timing
First numerical value of the operation mark.
Preferably, the operation mark that the monitoring chip is stored in first register is read in run duration timing
First numerical value, and compared with the second value of the operation mark stored in second register, and after the comparison
The second value of the operation mark stored in second register will be updated.
Preferably, the operation is designated count value, the performance of expected change of the operation mark be the count or
Successively decrease.
Preferably, the numerical value of the operation mark periodically changes between numerical value 1 and 0, and it is pre- that the operation is identified
Phase becomes the change frequency for turning to the running mark equal to expected frequence.
According to a further aspect in the invention, there is provided a kind of control method of embedded system, the embedded system include
On-chip system and monitoring chip, methods described include：The on-chip system is to monitoring chip report operation mark；The prison
Control chip judges the running status of the on-chip system according to the operation mark；System goes out the monitoring chip on said sheets
Reset signal is produced when now abnormal；And the monitoring chip provides reset signal to the on-chip system and restarts which.
Preferably, when the change of the operation mark is consistent with performance of expected change, judge the on-chip system normal operation,
When the change of the operation mark is inconsistent with performance of expected change, the on-chip system operation exception is judged.
Preferably, the CPU of the on-chip system is write in first register in run duration timing
First numerical value of the operation mark.
Preferably, the operation mark that the monitoring chip is stored in first register is read in run duration timing
First numerical value, and compared with the second value of the operation mark stored in the second register, and after the comparison will more
The second value of the operation mark stored in new second register.
Preferably, the operation is designated count value, the performance of expected change of the operation mark be the count or
Successively decrease.
Preferably, the numerical value of the operation mark periodically changes between numerical value 1 and 0, and it is pre- that the operation is identified
Phase becomes the change frequency for turning to the running mark equal to expected frequence.
Embedded system according to embodiments of the present invention and its control method, detect on-chip system using peripheral monitoring chip
It is abnormal and restart system, on the basis of being not apparent from increasing system cost can greatly improve the reliability of embedded system, make
Which can work under more stringent environment.
Description of the drawings
By description referring to the drawings to the embodiment of the present invention, the above-mentioned and other purposes of the present invention, feature and
Advantage will be apparent from, in the accompanying drawings：
Fig. 1 illustrates the schematic block diagram of the on-chip system according to prior art；
Fig. 2 illustrates the schematic block diagram of the on-chip system for using in embodiments of the present invention；
Fig. 3 illustrates the schematic block diagram of embedded system according to embodiments of the present invention.
Specific embodiment
Various embodiments of the present invention are more fully described hereinafter with reference to accompanying drawing.In various figures, identical element
Represented using same or similar reference.For the sake of clarity, the various pieces in accompanying drawing are not necessarily to scale.
Fig. 2 illustrates the schematic block diagram of the on-chip system for using in embodiments of the present invention.Save in on-chip system SOC
Digital house dog WDT.Alternatively, on-chip system SOC includes central processing unit CPU and register 120.Due on piece being
System generally includes register, therefore on-chip system SOC can adopt existing inexpensive consumer level chip.
Fig. 3 illustrates the schematic block diagram of embedded system according to embodiments of the present invention.The embedded system is included such as Fig. 2
Shown on-chip system SOC, and the monitoring chip 200 of periphery.As described above, on-chip system SOC can adopt existing low
Cost consumer level chip.In this embodiment, monitoring chip 200 can be from the technical grade that may operate in harsh environment condition
Chip.
Monitoring chip 200 includes detecting judge module 210 and register 220.Detection judge module 210 is via internal bus
It is connected with register 220, so as to be written and read operation to the latter.Additionally, detection judge module 210 is via external data bus
It is connected with the register 120 of on-chip system SOC, so as to carry out read operation to the latter.Detection judge module 210 is also via control
Line is connected to the reset terminal of on-chip system SOC.
At work, the CPU SOC timing of on-chip system SOC carries out write operation to register 120, to update
The value of register 120.The register 120 in on-chip system SOC is read in 210 timing of detection judge module of monitoring chip 200
Count value.The count value of reading is compared with the storage value in register 220, and after the comparison, the meter that will be read
With the storage value of renewal register 220 in numerical value write register 220.
In above-mentioned step, if the comparison indicate that the central processing unit CPU of on-chip system SOC it is anticipated that
Mode updates register 120, and such as count then judges SOC normal operation.If the comparison indicate that on piece being
System SOC central processing unit CPU fail the scheduled time update register 120, or update register 120 mode with it is pre-
The mode of phase is different, then judge SOC operation exception.
In the case of SOC operation exception is judged, the detection judge module 210 of monitoring chip 200 is to on-chip system
The reset terminal of SOC sends reset signal so that on-chip system SOC recovers normal after restarting and runs.
In this embodiment, monitoring chip 200 is the peripheral chip independently of on-chip system SOC.It is for instance possible to use work
51 single-chip microcomputers of industry level can be used as monitoring chip.The monitoring chip 200 includes detection judge module 210 and register 220, and
And design and be packaged into the technical grade chip of high reliability.Under harsh environmental condition, the operation of monitoring chip 200 itself is protected
It is fixed to keep steady, therefore the register mistake of itself can be avoided to cause on-chip system SOC frequently to restart system.Even if on-chip system
Consumer level chips of the SOC using low cost, the embedded system that on-chip system SOC and monitoring chip 200 are collectively constituted can also
Reliably detect the exception in on-chip system and restart system, such that it is able to improve the reliability of embedded system at low cost.
In the above-described embodiment, describe the register 220 of the register 120 and monitoring chip 200 of on-chip system SOC
The current data and historical data of the count value of the central processing unit CPU triggering of on-chip system SOC is stored respectively, according to counting
Whether the change of value is consistent with performance of expected change judging whether on-chip system SOC operation exception occurs.
In an alternative embodiment, the register 220 of the register 120 and monitoring chip 200 of on-chip system SOC can
To store the current data and historical data of any running mark of the central processing unit CPU of on-chip system SOC respectively, according to
Whether the change of running mark is consistent with performance of expected change judging whether on-chip system SOC operation exception occurs.Such as operation
Mark periodically changes between numerical value 1 and 0.Judge module is detected in continuous read operation, according to running mark
Whether change frequency is consistent with expected frequence judging whether on-chip system SOC operation exception occurs.
According to embodiments of the invention as described above, these embodiments do not have all of details of detailed descriptionthe, not yet
It is only described specific embodiment to limit the invention.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is for the principle and practical application of preferably explaining the present invention, so that affiliated
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.The protection model of the present invention
Enclose the scope that should be defined by the claims in the present invention to be defined.
Claims (13)
1. a kind of embedded system, including：
On-chip system；And
Monitoring chip,
Wherein, the monitoring chip is connected to the on-chip system via data/address bus, and is connected to via control line described
The reset terminal of on-chip system,
The on-chip system is identified to monitoring chip report operation in run duration,
The monitoring chip judges the running status of the on-chip system, and system on said sheets according to the operation mark
Reset signal is produced when occurring abnormal, and reset signal is sent to the reset terminal so that the on-chip system is restarted.
2. embedded system according to claim 1, wherein, consistent with performance of expected change in the change of the operation mark
When, judge the on-chip system normal operation,
When the change of the operation mark is inconsistent with performance of expected change, the on-chip system operation exception is judged.
3. embedded system according to claim 1, wherein, the on-chip system includes that CPU and first is posted
Storage, the monitoring chip include detecting judge module and the second register.
4. embedded system according to claim 3, wherein, the CPU of the on-chip system is in run duration
Timing writes the first numerical value of the operation mark in first register.
5. embedded system according to claim 4, wherein, the detection judge module of the monitoring chip is in run duration
First numerical value of the operation mark that timing is stored in reading first register, and with second register in store
The second value of operation mark compares, and after the comparison by the operation mark stored in renewal described second register
Second value.
6. embedded system according to claim 2, wherein, the operation is designated count value, the operation mark
Performance of expected change is the count or successively decreases.
7. embedded system according to claim 2, wherein, the numerical value of the operation mark is periodically in numerical value 1 and 0
Between change, it is described operation mark performance of expected change be the running mark change frequency be equal to expected frequence.
8. a kind of control method of embedded system, the embedded system include on-chip system and monitoring chip, methods described
Including：
The on-chip system is to monitoring chip report operation mark；
The monitoring chip judges the running status of the on-chip system according to the operation mark；
The monitoring chip produces reset signal when system occurs abnormal on said sheets；And
The monitoring chip provides reset signal to the on-chip system restarts which.
9. method according to claim 8, wherein, when the change of the operation mark is consistent with performance of expected change, judges
The on-chip system normal operation,
When the change of the operation mark is inconsistent with performance of expected change, the on-chip system operation exception is judged.
10. method according to claim 9, wherein, the CPU of the on-chip system is in run duration timing
The first numerical value of the operation mark is write in the first register.
11. methods according to claim 10, wherein, the detection judge module of the monitoring chip is in run duration timing
Store in reading first register operation mark the first numerical value, and with the second register in store operation mark
Second value compare, and the second number of the operation mark that store in second register will be updated after the comparison
Value.
12. methods according to claim 8, wherein, the operation is designated count value, the expected change of the operation mark
Turn to the count or successively decrease.
13. methods according to claim 8, wherein, the numerical value that the operation is identified is periodically between numerical value 1 and 0
Change, the performance of expected change that the operation is identified are that the change frequency of the running mark is equal to expected frequence.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610864377.0A CN106528311A (en) | 2016-09-29 | 2016-09-29 | Embedded system and control method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610864377.0A CN106528311A (en) | 2016-09-29 | 2016-09-29 | Embedded system and control method thereof |
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| CN106528311A true CN106528311A (en) | 2017-03-22 |
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| CN201610864377.0A Pending CN106528311A (en) | 2016-09-29 | 2016-09-29 | Embedded system and control method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107193680A (en) * | 2017-05-18 | 2017-09-22 | 郑州云海信息技术有限公司 | A kind of heartbeat detecting method, equipment and system |
| CN110221934A (en) * | 2019-05-08 | 2019-09-10 | 惠州市德赛西威汽车电子股份有限公司 | A kind of onboard system restoration methods |
| CN111813207A (en) * | 2020-07-27 | 2020-10-23 | 南方电网数字电网研究院有限公司 | Chip resetting device and relay protection device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107193680A (en) * | 2017-05-18 | 2017-09-22 | 郑州云海信息技术有限公司 | A kind of heartbeat detecting method, equipment and system |
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| CN111813207B (en) * | 2020-07-27 | 2022-05-17 | 南方电网数字电网研究院有限公司 | Chip resetting device and relay protection device |
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