CN106527562B - A kind of low-power consumption SRAM word line voltage based on FPGA realizes circuit and method - Google Patents
A kind of low-power consumption SRAM word line voltage based on FPGA realizes circuit and method Download PDFInfo
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- CN106527562B CN106527562B CN201611149766.1A CN201611149766A CN106527562B CN 106527562 B CN106527562 B CN 106527562B CN 201611149766 A CN201611149766 A CN 201611149766A CN 106527562 B CN106527562 B CN 106527562B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
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Abstract
The invention discloses a kind of low-power consumption SRAM word line voltage based on FPGA to realize circuit and method, and system includes：Band-gap reference circuit, for providing reference voltage；Control circuit, for generating control signal and reset signal；Read/write decoding circuit, for obtaining circuit status according to control selections, and generate partial pressure selection signal；Word line voltage generation circuit, for being respectively circuit cleared condition, write state and read states setting word line voltage, and, select to obtain the word line voltage value under circuit status according to the partial pressure selection signal of reception by the reference voltage as the reference voltage；Address decoding circuitry, for SRAM address decodings to be configured, obtaining decoding output signal；Address output circuit, exported for decoding output signal when decoding output signal is effective, to be converted to the word line voltage value under corresponding circuits status to corresponding SRAM to be configured.The present invention uses different word line voltages, both can guarantee that reading correctness, reduces the power consumption of overall chip again.
Description
Technical field
The present invention relates to a kind of low-power consumption SRAM word line voltage based on FPGA to realize circuit and method, belong to it is static with
The technical field of machine memory.
Background technology
SRAM (Static Randon Acess Memory), i.e. static RAM are a kind of with static state
The internal memory of access facility, it is not necessary to which refresh circuit can preserve the data of its storage inside.
In FPGA storage arrays, the SRAM of six tubular constructions is most commonly seen, as shown in Figure 1.SRAM work is generally divided into
Three parts：Data are kept, data is read and writes data.When reading data, word line voltage is first charged to high level, makes a pipe conducting, so
For Data Node to bit line charge/discharge, sense amplifier identifies that the voltage difference of two bit lines zooms into level qualified height afterwards
Low level, i.e. data read-out.When writing data, first according to the data to be write by a certain bit line preliminary filling to high level, another puts
Electricity arrive low level, and then wordline is height, and door pipe turns on, and bit line is to back end charge/discharge.
Common word line voltage is usually supply voltage, and during read/write data, makes a word line voltage for pipe conducting also phase
Together, it is all supply voltage, and the high level voltage of bit line is also usually supply voltage, therefore wordline is identical with bit-line voltage,
It is unfavorable for SRAM write operation in some cases.In read operation, certain power consumption can be also wasted, particularly with large-scale
SRAM array.
The content of the invention
The technical problems to be solved by the invention are overcome the deficiencies in the prior art, there is provided a kind of low work(based on FPGA
Consumption SRAM word line voltages realize circuit and method, and solution wordline is identical with bit-line voltage, is unfavorable for SRAM's in some cases
Write and read operates, it is impossible to ensures to read correctness, the problem of can not reducing the power consumption of overall chip.
It is of the invention specifically to solve above-mentioned technical problem using following technical scheme：
A kind of low-power consumption SRAM word line voltage based on FPGA realizes circuit, including：
Band-gap reference circuit, for providing reference voltage；
Control circuit, for generating control signal and reset signal；
Read/write decoding circuit, for being selected to obtain circuit status, the circuit according to the control signal of control circuit
Status includes cleared condition, write state and read states；And partial pressure selection signal is generated according to the circuit status of selection；
Word line voltage generation circuit, for the partial pressure selection signal according to reception, using the reference voltage as with reference to electricity
Pressure carries out partial pressure, obtains the word line voltage value under circuit status；
Address decoding circuitry, row decoding is entered to SRAM to be configured address for the control signal according to control circuit, obtained
Obtain decoding output signal；
Address output circuit, for receiving the reset signal of control circuit, and the decoding of the address decoding circuitry in reception
When output signal is effective, decoding output signal is converted to the word line voltage value under corresponding circuits status, and by the wordline
Magnitude of voltage is exported to the door pipe control terminal of SRAM to be configured corresponding to address decoding circuitry decoding.
Further, include as a preferred technical solution of the present invention, the word line voltage generation circuit：
Voltage-stablizer, for as the reference voltage, reference voltage to be obtained into the output voltage after voltage stabilizing；
Resistance string, for carrying out partial pressure to the output voltage after voltage stabilizing obtained by voltage-stablizer according to partial pressure selection signal, obtain
The different output voltage of magnitude of voltage；
Biasing circuit, for resistance string to be obtained into the different output voltage of magnitude of voltage, to be converted into word line voltage value respectively defeated
Go out.
Further, as a preferred technical solution of the present invention, in the word line voltage generation circuit, initialization circuit
The word line voltage value VG1 of cleared condition is less than the word line voltage value VG2 of circuit write state；And the wordline electricity of initialization circuit read states
Pressure value VG3 is more than the threshold voltage of door pipe, and word line voltage value VG1 and the wordline electricity of write state less than circuit cleared condition
Pressure value VG2.
Further, include what is be connected with each other as a preferred technical solution of the present invention, the address decoding circuitry
Nor gate and phase inverter.
A kind of low-power consumption SRAM word line voltage implementation method based on FPGA, comprises the following steps：
Generate control signal；
Selected to obtain circuit status according to control signal, the circuit status includes cleared condition, write state
And read states；And partial pressure selection signal is generated according to the circuit status of selection；
One reference voltage is provided, and divided reference voltage as the reference voltage according to the partial pressure selection signal of reception
Pressure, obtains the word line voltage value under circuit status；
Row decoding is entered to SRAM to be configured address according to control signal, obtains decoding output signal；
When the decoding output signal of reception is effective, decoding output signal is converted into the word under corresponding circuits status
Line voltage value, and the word line voltage value is exported to the door pipe control terminal of SRAM to be configured corresponding to decoding.
Further, as a preferred technical solution of the present invention, the temperature coefficient of the reference voltage is zero.
The present invention uses above-mentioned technical proposal, can produce following technique effect：
The present invention devises a kind of low-power consumption SRAM word line voltage based on FPGA and realizes circuit and method, provides one first
The reference voltage of individual zero-temperature coefficient, as the reference voltage of word line voltage, read/write is decoded by control circuit and address is translated
The control of code circuit, chooses suitable word line voltage value and address, the door pipe control terminal for SRAM.Related in FPGA different phases
And using different word line voltages during SRAM operations, on the one hand in write operation, it is easier to configuration information is write into sram cell,
On the other hand in read operation, reading correctness had both been can guarantee that, has reduced the power consumption of overall chip again.
The present invention can overcome the deficiencies in the prior art, and reading correctness is effectively ensured, and reduce overall chip again
Power consumption.
Brief description of the drawings
Fig. 1 is six traditional in the prior art pipe SRAM structures.
Fig. 2 is the schematic diagram that the low-power consumption SRAM word line voltage of the invention based on FPGA realizes circuit.
Fig. 3 is the schematic diagram of word line voltage generation circuit in the present invention.
Fig. 4 is the schematic diagram of address output circuit in the present invention.
Fig. 5 is the schematic diagram of the low-power consumption SRAM word line voltage implementation method based on FPGA in the present invention.
Wherein, reference is explained：13- band-gap reference circuits, 14- word line voltages generation circuit, 15- control circuits, 16-
Read/write decoding circuit, 17- address decoding circuitries, 18- addresses output circuit, 19- voltage-stablizers, 20- resistance strings, 21- biased electricals
Road, 22- nor gates, 23- phase inverters.
Embodiment
Embodiments of the present invention are described with reference to Figure of description.
As shown in Fig. 2 the present invention devises a kind of low-power consumption SRAM word line voltage based on FPGA and realizes circuit, including：
Band-gap reference circuit 13, for providing reference voltage；
Control circuit 15, for generating control signal and reset signal RST；
Read/write decoding circuit 16, for being selected to obtain circuit status, the electricity according to the control signal of control circuit
Road status includes cleared condition, write state and read states；And partial pressure selection letter is generated according to the circuit status of selection
Number；
Word line voltage generation circuit 14, for the partial pressure selection signal according to reception, using the reference voltage as reference
Voltage carries out partial pressure, obtains the word line voltage value signal WL_VS under circuit status；
Address decoding circuitry 17, row decoding is entered to SRAM to be configured address for the control signal according to control circuit,
Obtain decoding output signal WL_EN；
Address output circuit 18, translated for receiving the reset signal of control circuit, and in the address decoding circuitry of reception
When code output signal WL_EN is effective, decoding output signal WL_EN is converted into the word line voltage under corresponding circuits status
Value, and the word line voltage value is exported to the door pipe control terminal WL of SRAM to be configured corresponding to address decoding circuitry decoding.
The system is provided the reference voltage of a zero-temperature coefficient by band-gap reference circuit 13, the reference as word line voltage
Voltage, by control circuit to read/write decode and address decoding circuitry control, choose suitable word line voltage value and address,
Door pipe control terminal WL for SRAM to be configured.
The read/write decoding circuit 16, include two signal for coming from control module CLEAR_EN and PROGRAMME_
EN.When input signal CLEAR_EN and PROGRAMME_EN is simultaneously high level, determine that circuit is in cleared condition.Work as input
Signal CLEAR_EN is low level, when PROGRAMME_EN is high level, determines that circuit is in write state.Work as input signal
CLEAR_EN is low level, when PROGRAMME_EN is low level, determines that circuit is in read states.And it is determined that the circuit of selection
After status, partial pressure selection signal corresponding to generation is exported to word line voltage generation circuit 14.
Shown in a kind of implementation Fig. 3 of the word line voltage generation circuit 14, including low pressure difference linear voltage regulator 19, electricity
Resistance string 20 and biasing circuit 21.The reference voltage of wherein low pressure difference linear voltage regulator comes from band-gap reference circuit 13, resistance string
Partial pressure selection signal come from read/write decoding circuit 16.Voltage-stablizer 19, for reference voltage as the reference voltage, to be obtained
Output voltage after voltage stabilizing；Resistance string 20, for according to partial pressure selection signal to the output voltage after the gained voltage stabilizing of voltage-stablizer 19
Partial pressure is carried out, obtains the different output voltage of magnitude of voltage；Biasing circuit 21, for resistance string to be obtained into different defeated of magnitude of voltage
Go out voltage and be converted into corresponding word line voltage value WL_VS outputs respectively.
The resistance string 20, the output voltage VLDO of low pressure difference linear voltage regulator is divided according to read/write different operating
Pressure, obtains the different output voltage VBIAS of magnitude of voltage.When circuit is carried out into write operation, the magnitude of voltage of partial pressure output is designated as
VBIAS1；When circuit is carried out into read operation, the magnitude of voltage of partial pressure output is designated as VBIAS2.The magnitude of voltage of the VBIAS1 is more than
VBIAS2 magnitude of voltage.
The word line voltage generation circuit 14, its control signal derives from the read/write decoding circuit 16, when in clearing
During state, word line voltage WL_VS value is the first word line voltage value VG1；When the value in write state, word line voltage WL_VS is
Second word line voltage value VG2；When the value in read states, word line voltage WL_VS is the 3rd word line voltage value VG3.
And the first word line voltage value VG1, its value are less than the second word line voltage value VG2.3rd word line voltage
Value VG3, its value are slightly larger than the threshold voltage VTH of door pipe, less than the first word line voltage value VG1 and the second word line voltage its value
VG2。
Shown in a kind of implementation Fig. 4 of the address output circuit 6, including a nor gate 22 and a phase inverter
23.Wherein nor gate port a input signal WL_EN derives from address decoding circuitry 17, port b input signal RST sources
It is reset signal in control module 15.
The nor gate 22 connects voltage, is digital circuit power source voltage VCCINT, it is 1.1v.
The phase inverter 23 connects voltage, is the output voltage of word line voltage generation circuit, is WL_VS.
The output voltage WL_VS of the word line voltage generation circuit, when circuit is in cleared condition, WL_VS voltage
Value is identical with supply voltage VCCINT magnitudes of voltage, is 1.1V, is designated as VG1.When circuit is in write state, WL_VS magnitudes of voltage are about
1.18V, it is designated as VG2.When circuit is in read states, WL_VS magnitudes of voltage are about 0.75V, are designated as VG3.
The system is to the configuration process of SRAM word line voltages, as shown in Figure 5.When fpga chip carries out write operation, generally
It is divided into the different write operation of two classes, resets and configure.The write operation in the clearing stage, exactly all SRAM to be configured are write
Enter 0.Now all SRAM to be configured bit line gets out data 0, and address decoding circuitry is translated by column according to control signal
Code, opens SRAM to be configured by column.Now by the first word line voltage value VG1 with the wordline to be configured in opening.
After clearing terminates, start to configure SRAM to be configured.During configuration, first determine whether to read SRAM to be configured
Operation, or write operation.If carrying out write operation, all SRAM to be configured are exactly write into configuration information, now basis
Address decoding circuitry carries out certain column decoding according to control signal, and certain row SRAM to be configured is opened and carries out write operation, now by the
Two word line voltage value VG2 are with the SRAM wordline to be configured of opening；If read operation is carried out, according to address decoding circuitry root
Certain column decoding is carried out according to control signal, certain row SRAM to be configured is opened and carries out read operation, now by the 3rd word line voltage value VG3
With in the SRAM wordline to be configured of opening, to complete configuration process.
The first word line voltage value VG1, its value is identical with supply voltage VCCINT, the second word line voltage value VG2,
Its value is slightly above the first word line voltage value VG1, and the 3rd word line voltage value VG3, its value is less than VG1 and VG2, than the threshold of door pipe
Threshold voltage VTH is slightly higher, to ensure the unlatching of pipe.
On the basis of said system, the present invention also proposes a kind of low-power consumption SRAM word line voltage realization side based on FPGA
Method, this method can be used in said system, and method specifically includes following steps：
First, control signal is generated.Selected to obtain circuit status, the circuit status bag according to control signal
Include cleared condition, write state and read states；And partial pressure selection signal is generated according to the circuit status of selection；
The reference voltage that a temperature coefficient is zero is provided, according to the partial pressure selection signal of reception using reference voltage as ginseng
Examine voltage and carry out partial pressure, obtain the word line voltage value WL_VS under circuit status；I.e.：When selection obtains circuit cleared condition
When, selection obtains corresponding word line voltage value WL_VS and is designated as VG1;When selection obtains circuit write state, selection obtains correspondingly
Word line voltage value WL_VS be designated as VG2；When selection obtains circuit read states, selection obtains corresponding word line voltage value WL_VS
It is designated as VG3.
Row decoding is entered to SRAM to be configured address according to control signal, obtains decoding output signal；
When the decoding output signal of reception is effective, decoding output signal is converted into the word under corresponding circuits status
Line voltage value, and the word line voltage value is exported to the door pipe control terminal of SRAM to be configured corresponding to decoding.I.e.：Match somebody with somebody according to treating
After putting address decoding, certain row SRAM to be configured is opened and is zeroed out or configures operation.When the output of selected word line voltage
Voltage WL_VS, when circuit is in cleared condition, word line voltage value WL_VS is identical with supply voltage VCCINT magnitudes of voltage, is
1.1V, VG1 is designated as, now by the first word line voltage value VG1 with the SRAM wordline to be configured opened in decoding.When circuit is in
Write state, word line voltage value WL_VS is about 1.18V, is designated as VG2, and the second word line voltage value VG2 now is used in into decoding opening treats
In the wordline for configuring SRAM.When circuit is in read states, word line voltage value WL_VS is about 0.75V, is designated as VG3, now by the 3rd
Word line voltage value VG3 is with the SRAM wordline to be configured opened in decoding.
Thus, system and method for the invention are by the way that to read/write decoding and the control of address decoding circuitry, it is suitable to choose
Word line voltage value and address, the door pipe control terminal for SRAM.When FPGA different phases are related to SRAM operations using different
Word line voltage, on the one hand in write operation, it is easier to configuration information is write into sram cell, on the other hand in read operation, both
Reading correctness is can guarantee that, reduces the power consumption of overall chip again.
Embodiments of the present invention are explained in detail above in conjunction with accompanying drawing, but the present invention is not limited to above-mentioned implementation
Mode, can also be on the premise of present inventive concept not be departed from those of ordinary skill in the art's possessed knowledge
Make a variety of changes.
Claims (5)
1. a kind of low-power consumption SRAM word line voltage based on FPGA realizes circuit, it is characterised in that including：
Band-gap reference circuit, for providing reference voltage；
Control circuit, for generating control signal and reset signal；
Read/write decoding circuit, for being selected to obtain circuit status according to the control signal of control circuit, residing for the circuit
State includes cleared condition, write state and read states；And partial pressure selection signal is generated according to the circuit status of selection；
Word line voltage generation circuit, for the partial pressure selection signal according to reception, the reference voltage is entered as the reference voltage
Row partial pressure, obtain the word line voltage value under circuit status；
Address decoding circuitry, row decoding is entered to SRAM to be configured address for the control signal according to control circuit, translated
Code output signal；
Address output circuit, for receiving the reset signal of control circuit, and the decoding output of the address decoding circuitry in reception
When signal is effective, decoding output signal is converted to the word line voltage value under corresponding circuits status, and by the word line voltage
SRAM to be configured door pipe control terminal corresponding to value output to address decoding circuitry decoding；
Wherein, the address decoding circuitry includes the nor gate and phase inverter being connected with each other.
2. the low-power consumption SRAM word line voltage based on FPGA realizes circuit according to claim 1, it is characterised in that the word
Line voltage generation circuit includes：
Voltage-stablizer, for as the reference voltage, reference voltage to be obtained into output voltage after voltage stabilizing；
Resistance string, for carrying out partial pressure to the output voltage after voltage stabilizing obtained by voltage-stablizer according to partial pressure selection signal, obtain voltage
It is worth different output voltages；
Biasing circuit, for resistance string partial pressure to be obtained into the different output voltage of magnitude of voltage, to be converted into word line voltage value respectively defeated
Go out.
3. the low-power consumption SRAM word line voltage based on FPGA realizes circuit according to claim 1, it is characterised in that：The word
In line voltage generation circuit, the word line voltage value VG1 of initialization circuit cleared condition is less than the word line voltage value of circuit write state
VG2；And the word line voltage value VG3 of initialization circuit read states is more than the threshold voltage of door pipe, and less than circuit cleared condition
Word line voltage value VG1 and write state word line voltage value VG2.
4. a kind of low-power consumption SRAM word line voltage implementation method based on FPGA, it is characterised in that comprise the following steps：
Generate control signal；
Selected to obtain circuit status according to control signal, the circuit status includes cleared condition, write state and reading
State；And partial pressure selection signal is generated according to the circuit status of selection；
One reference voltage is provided, and reference voltage is carried out by partial pressure according to the partial pressure selection signal of reception as the reference voltage,
Obtain the word line voltage value under circuit status；
Row decoding is entered to SRAM to be configured address according to control signal, obtains decoding output signal；
When the decoding output signal of reception is effective, decoding output signal is converted to the wordline electricity under corresponding circuits status
Pressure value, and the word line voltage value is exported to the door pipe control terminal of SRAM to be configured corresponding to decoding.
5. the low-power consumption SRAM word line voltage implementation method based on FPGA according to claim 4, it is characterised in that：The base
The temperature coefficient of quasi- voltage is zero.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1383153A (en) * | 2001-01-26 | 2002-12-04 | 萧正杰 | Multi-port memory unit structure |
| CN1421861A (en) * | 2001-11-26 | 2003-06-04 | 萧正杰 | High-performance semiconductor memory equipment |
| CN101162611A (en) * | 2006-10-12 | 2008-04-16 | 三星电子株式会社 | Voltage generation circuit, flash memory device including the same and method for programming the flash memory device |
| CN101359508A (en) * | 2007-07-30 | 2009-02-04 | 松下电器产业株式会社 | Non-volatile memory control device |
| CN101540195A (en) * | 2008-03-20 | 2009-09-23 | 中国科学院半导体研究所 | Unloaded static random access memory comprising four NMOS transistors |
| CN102163456A (en) * | 2010-02-17 | 2011-08-24 | 三星电子株式会社 | Nonvolatile memory device, operating method thereof, and memory system including the same |
| CN104183269A (en) * | 2014-08-29 | 2014-12-03 | 东南大学 | Low-voltage single-end read-write SRAM (Static Random Access Memory) storage unit and control method |
| US9431062B2 (en) * | 2014-02-03 | 2016-08-30 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method of driving word line of the nonvolatile memory |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101559909B1 (en) * | 2009-02-06 | 2015-10-15 | 삼성전자주식회사 | circuit for driving word line and driving method used the same |
-
2016
- 2016-12-14 CN CN201611149766.1A patent/CN106527562B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1383153A (en) * | 2001-01-26 | 2002-12-04 | 萧正杰 | Multi-port memory unit structure |
| CN1421861A (en) * | 2001-11-26 | 2003-06-04 | 萧正杰 | High-performance semiconductor memory equipment |
| CN101162611A (en) * | 2006-10-12 | 2008-04-16 | 三星电子株式会社 | Voltage generation circuit, flash memory device including the same and method for programming the flash memory device |
| CN101359508A (en) * | 2007-07-30 | 2009-02-04 | 松下电器产业株式会社 | Non-volatile memory control device |
| CN101540195A (en) * | 2008-03-20 | 2009-09-23 | 中国科学院半导体研究所 | Unloaded static random access memory comprising four NMOS transistors |
| CN102163456A (en) * | 2010-02-17 | 2011-08-24 | 三星电子株式会社 | Nonvolatile memory device, operating method thereof, and memory system including the same |
| US9431062B2 (en) * | 2014-02-03 | 2016-08-30 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method of driving word line of the nonvolatile memory |
| CN104183269A (en) * | 2014-08-29 | 2014-12-03 | 东南大学 | Low-voltage single-end read-write SRAM (Static Random Access Memory) storage unit and control method |
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Effective date of registration: 20201222 Address after: 2 / F, building B1, No. 777, Jianzhu West Road, Binhu District, Wuxi City, Jiangsu Province, 214000 Patentee after: WUXI ZHONGWEI YIXIN Co.,Ltd. Address before: 214000 15 / F, B1 building, 777 Jianzhu Road, Wuxi City, Jiangsu Province Patentee before: WUXI ZHONGWEI YIXIN Co.,Ltd. Patentee before: The 58th Research Institute of China Electronics Technology Group Corp. |
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