CN106486363A - Group III-nitride enhancement mode HEMT based on p-type layer and preparation method thereof - Google Patents
Group III-nitride enhancement mode HEMT based on p-type layer and preparation method thereof Download PDFInfo
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- 230000004888 barrier function Effects 0.000 claims abstract description 36
- 239000000463 material Substances 0.000 claims description 32
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- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 12
- 238000000407 epitaxy Methods 0.000 description 9
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
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- H01L21/0254—Nitrides
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
The invention discloses a kind of group III-nitride enhancement mode HEMT based on p-type layer and preparation method thereof.Described HEMT comprises the hetero-junctions being mainly made up of and the source, grid and the drain electrode that are connected with described hetero-junctions the first half, the second semiconductor layer, and being also distributed between this gate electrode and barrier layer can be with the 3rd semiconductor layer of the second semiconductor layer formation hetero-junctions；Etch stop layer is also distributed between described three, the second semiconductor layers, the composition material that the composition material of described etch stop layer has, than the composition material of the 3rd semiconductor layer, the region closed in higher etching selection ratio, or described second semiconductor layer with the 3rd semiconductor layer has higher etching selection ratio than the composition material of the 3rd semiconductor layer.The enforcement difficulty of p-type gate technique can be greatly reduced by the design of the present invention, and the etching depth of precise control p-type layer is it is ensured that the repeatability of device electrology characteristic and chip fabrication technique, uniformity, stability are it is adaptable to large-scale production.
Description
Technical field
The present invention relates to a kind of preparation technology of HEMT device, the group III-nitride enhancing of particularly a kind of utilization etch stop layer
The preparation method of type HEMT.
Background technology
Compared to traditional silicon substrate MOSFET, the HEMT (High based on AGaN/GaN hetero-junctions
Electron Mobility Transistor, HEMT) there is the advantages such as low on-resistance, high-breakdown-voltage, high switching frequency, because
This can use as core devices in all kinds of electric power coversion systems, has important application prospect in terms of energy-saving consumption-reducing.However,
Due to III-nitride material system polarity effect it is however generally that, all exhausted based on the HEMT of AlGaN/GaN hetero-junctions
Type (normally opened), when the device of the type is applied in circuit-level system, needs to design negative polarity gate driver circuit, to realize
On-off control to device, this complexity that circuit has been significantly greatly increased and cost.Additionally, depletion device is in fail safe ability
Aspect existing defects, therefore, it is impossible to really realize commercial applications.For solving this problem, prepared based on p-type gate technique and strengthen
Type HEMT is a kind of feasible scheme, refering to Fig. 1, that is, on the basis of traditional HEMT epitaxial structure, (non-in AlGaN potential barrier
Deliberately doping N-shaped) Epitaxial growth p-type layer, thus forming pn-junction in the range of whole epitaxial wafer, and carry out constituency etching and realize p
Prepared by type grid, thus exhausting the two-dimensional electron gas below p-type grid.In the etching process of constituency, need the large area area to non-grid
Domain performs etching, if but be unable to effective control etching homogeneity, easily lead to the possible over etching of regional area inner p-type layer
(Over-etching), then may owe in regional area to etch (Under-etching), and both finally all can lead to device gate
Between source, grid leak, the two-dimensional electron gas in region reduce, and produce exhibiting high surface defect state, thus having a strong impact on device in work
Conducting resistance when making and dynamic characteristic.Therefore, the quarter to non-area of grid p-type layer is required based on the p-type gate technique of constituency etching
Erosion depth controllable precise, this has been significantly greatly increased the difficulty of p-type gate technique so that the repeatability (between piece and piece) of this technology, all
Even property (in piece between zones of different), stability (between different wheel techniques) are all difficult to ensure that.
Content of the invention
Present invention is primarily targeted at providing a kind of group III-nitride enhancement mode HEMT and preparation method thereof, to overcome existing skill
The deficiency of art.
For realizing aforementioned invention purpose, the technical solution used in the present invention includes：
Provide a kind of group III-nitride enhancement mode HEMT based on p-type layer among some embodiments, comprise mainly by as ditch
First semiconductor layer of channel layer and the hetero-junctions of the second semiconductor layer composition as barrier layer and the source being connected with described hetero-junctions
Electrode, gate electrode and drain electrode, are also distributed between described gate electrode and barrier layer and can form hetero-junctions with the second semiconductor layer
3rd semiconductor layer；Wherein：
Etch stop layer is also distributed between described 3rd semiconductor layer and the second semiconductor layer, and, with respect to selected engraving
Matter, the composition material of described etch stop layer has higher etch resistant performance than the composition material of described 3rd semiconductor layer；
Or, with respect to selected etching material, the group in the region closed on the 3rd semiconductor layer in described second semiconductor layer is become a useful person
Material has higher etch resistant performance than the composition material of the 3rd semiconductor layer.
In some more preferred embodiment, described etch stop layer or the second semiconductor layer are additionally provided with passivation layer, described blunt
Change layer to include at least by the regional area on described etch stop layer top layer or the regional area on the second semiconductor layer top layer and described etching
Substance reaction and the natural passivation layer that is formed in situ.
In certain embodiments, additionally provide a kind of method preparing group III-nitride enhancement mode HEMT based on p-type layer, its bag
Include：
On substrate, growth is formed as the first semiconductive layer body of channel layer, the second semiconductor layer as barrier layer and energy successively
Form the 3rd semiconductor layer of hetero-junctions with the second semiconductor layer, wherein, with respect to selected etching material, described second quasiconductor
The composition material in the region closed on the 3rd semiconductor layer in layer has higher etch resistance than the composition material of the 3rd semiconductor layer
Can,
Or, on substrate successively growth formed the first semiconductor layer as channel layer, the second semiconductor layer as barrier layer,
Etch stop layer and the 3rd semiconductor layer that hetero-junctions can be formed with the second semiconductor layer, wherein, with respect to selected etching material,
The composition material of described etch stop layer has higher etch resistant performance than the composition material of described 3rd semiconductor layer；
Described 3rd semiconductor layer forms layer of gate electrode material, then pattern mask is set in described layer of gate electrode material,
And layer of gate electrode material and the 3rd semiconductor layer are performed etching, thus forming gate electrode, and make the second semiconductor layer or etching eventually
Only layer exposes；
And, setting source electrode and drain electrode on the device being formed by abovementioned steps, thus obtain described HEMT.
In some more preferred embodiment, described preparation method may also include：Figure is arranged on described layer of gate electrode material
Change mask, and performed etching with selecting engraving confrontation the 3rd semiconductor layer, until described etching material and the second semiconductor layer table
The regional area on the regional area of layer or etch stop layer top layer stops etching after reacting and being formed in situ nature passivation layer.
The present invention passes through before growth regulation three semiconductor layer (such as p-type layer), and growth and the group of the 3rd semiconductor layer are become a useful person
There is between material the material of higher etching selection ratio, and combine lithographic technique, effective, the reliable etching realizing the 3rd semiconductor layer
Terminate, thus precise control the 3rd semiconductor layer etching depth, at utmost ensure that the two-dimensional electron gas of non-area of grid are not subject to
The impact of etching technics, it is ensured that device electrology characteristic includes output current, dynamic characteristic etc., greatly reduces the enforcement of p-type gate technique
Difficulty is it is ensured that the repeatability of device electrical chip technique, uniformity, stability are it is adaptable to large-scale production.It is especially preferred,
Etching technics effect under, semiconductor surface can self-assembling formation in-situ passivation layer, this passivation layer can play key protection make
With, thus the problems such as effectively reduce the surface damage causing due to follow-up passivation layer deposition technique and the material thus bringing
The problems such as electrology characteristic deteriorates (such as sheet resistance becomes big, electric current collapses specially good effect should be notable).
Brief description
Fig. 1 is the schematic diagram preparing p-type grid enhancement mode HEMT in prior art based on constituency lithographic technique；
Fig. 2 is a kind of epitaxial structure schematic diagram of HEMT in the embodiment of the present invention 1；
Fig. 3 is the schematic diagram forming etch stop layer on epitaxial structure shown in Fig. 1；
Fig. 4 is the schematic diagram forming p-GaN layer on etch stop layer shown in Fig. 3；
Fig. 5 is the schematic diagram that device shown in Fig. 4 is carried out with active area isolation；
Fig. 6 is the schematic diagram forming gate electrode metal layer on device shown in Fig. 5；
Fig. 7 is schematic diagram after gate electrode metal layer and p-GaN layer etching for the device shown in Fig. 6；
Fig. 8 is the schematic diagram forming passivation layer on device shown in Fig. 7；
Fig. 9 be device shown in Fig. 8 passivation layer through windowing process after schematic diagram；
Figure 10 is the schematic diagram forming source, drain electrode and field plate on device shown in Fig. 9；
Figure 11 is the structural representation of the obtained HEMT of embodiment 1；
Figure 12 a is a kind of epitaxial structure schematic diagram of HEMT in the embodiment of the present invention 2；
Figure 12 b is the change schematic diagram of Al component in barrier layer in epitaxial structure shown in Figure 12 a；
Figure 13 is the schematic diagram forming p-GaN layer on device shown in Figure 12 a；
Figure 14 is the structural representation of the obtained HEMT of embodiment 2；
Figure 15 a is a kind of epitaxial structure schematic diagram of HEMT in the embodiment of the present invention 3；
Figure 15 b is the change schematic diagram of Al component in barrier layer in epitaxial structure shown in Figure 15 a；
Figure 16 is the schematic diagram forming p-GaN layer on device shown in Figure 15 a；
Figure 17 is the structural representation of the obtained HEMT of embodiment 3；
Figure 18 a is a kind of epitaxial structure schematic diagram of HEMT in the embodiment of the present invention 4；
Figure 18 b is the change schematic diagram of Al component in barrier layer in epitaxial structure shown in Figure 18 a；
Figure 19 is the schematic diagram forming p-GaN layer on device shown in Figure 18 a；
Figure 20 is the structural representation of the obtained HEMT of embodiment 4.
Specific embodiment
One aspect of the present invention provides a kind of group III-nitride enhancement mode HEMT based on p-type layer, comprises mainly by as ditch
First semiconductor layer of channel layer and the hetero-junctions of the second semiconductor layer composition as barrier layer and the source being connected with described hetero-junctions
Electrode, gate electrode and drain electrode, are also distributed between described gate electrode and barrier layer and can form hetero-junctions with the second semiconductor layer
3rd semiconductor layer.In a more preferred case study on implementation, also it is distributed between described 3rd semiconductor layer and the second semiconductor layer
There is etch stop layer, between the composition material of described etch stop layer and described 3rd semiconductor layer, there is higher etching selection ratio.
That is, for selected etching material, the composition material of described etch stop layer is become a useful person than the group of described 3rd semiconductor layer
Material has higher etch resistant performance.
The composition material in region closing on the 3rd semiconductor layer in described second semiconductor layer and the composition material of the 3rd semiconductor layer
Between there is higher etching selection ratio.
That is, for selected etching material, the composition material in the region closed on the 3rd semiconductor layer in described second semiconductor layer
Than the composition material of described 3rd semiconductor layer, there is higher etch resistant performance.
In certain embodiments, it is distributed in below gate electrode in described 3rd semiconductor layer, and be located at described gate electrode in barrier layer
On orthographic projection in.
In some more preferred embodiment, described etch stop layer or the second semiconductor layer are additionally provided with passivation layer, described blunt
Change layer to include at least by the regional area on described etch stop layer top layer or the regional area on the second semiconductor layer top layer and described etching
Substance reaction and the natural passivation layer that is formed in situ, for example, natural passivation layer of oxidation aluminium material etc..
Wherein, the composition material of described barrier layer is at least selected from but is not limited to AlxInyGazN (0 ＜ x≤1,0≤y≤1,
X+y+z=1).
In certain embodiments, described barrier layer near the local of the 3rd semiconductor layer as etch stop layer, and can ensure
On the premise of two-dimensional electron gas have superior electrical characteristics, Al component contained by it can also be the various functions in epitaxial growth z direction.
In some more preferred embodiment, the composition material of described barrier layer is selected from AlxInyGazN (0 ＜ x≤1,0≤y≤1,
(x+y+z)=1), wherein along the direction pointing to the 3rd semiconductor layer from the first semiconductor layer, x is in totally trend (its increasing
In some aspects may keep constant or be declined slightly).Its increase mode can be linear increase, step growth, superlattices
Formula growth, the growth of multilamellar class superlattice structure formula etc..
Wherein, the composition material of described channel layer at least can be selected for but be not limited to GaN, InGaN, AlGaN, AlInN or
AlInGaN.
Wherein, the composition material of described 3rd semiconductor layer be at least selected from but be not limited to p-GaN, p-AlGaN, p-AlInN,
p-InGaN、p-AlInGaN.
Wherein, the composition material of described etch stop layer is at least selected from AlN, SiNx(0 ＜ x≤3), AlxGa1-xN (0 ＜ x ＜
1) etc., but there is and the 3rd quasiconductor (such as p-type layer) between the material of higher etching selection ratio also selected from other.
In certain embodiments, described hetero-junctions also includes the interposed layer being distributed between the first semiconductor layer and the second semiconductor layer.
Wherein, the composition material of described interposed layer at least can be selected for but is not limited to AlN, AlInN or AlInGaN.
In certain embodiments, described passivation layer also includes the SiN being formed on described natural passivation layerxLayer (0 ＜ x≤3).
Wherein, described selected etching material can be conventional all kinds of materials in dry etching or wet etching, it is preferred to use dry
Method etching technics, such as IBE (Ion Beam Etch, ion beam etching), ICP (Inductive Coupled Plasma, electricity
Sense coupled plasma) etc..
More preferred, described selected etching material is selected from the etching gas containing aerobic.
In certain embodiments, described HEMT also includes substrate, and cushion is also distributed between described substrate and hetero-junctions.
Wherein, described substrate can be the substrate such as sapphire, carborundum, gallium nitride, aluminium nitride, but not limited to this.
Wherein, the material of described cushion can industry be commonly used, for example, can be GaN, AlGaN etc.
Wherein, described source electrode, drain electrode and the epitaxial structure of described HEMT form Ohmic contact.
In addition, described HEMT also has field plate structure.
The material of aforementioned source electrode, drain electrode, gate electrode etc. can industry be commonly used, for example, can be W, Ni, Au etc..
One aspect of the present invention additionally provides a kind of preparation method of group III-nitride enhancement mode HEMT based on p-type layer, its bag
Include：
On substrate, growth is formed as the first semiconductive layer body of channel layer, the second semiconductor layer as barrier layer and energy successively
Form the 3rd semiconductor layer of hetero-junctions with the second semiconductor layer, wherein, with respect to selected etching material, described second quasiconductor
The composition material in the region closed on the 3rd semiconductor layer in layer has higher etch resistant than the composition material with the 3rd semiconductor layer
Performance,
Or, on substrate successively growth formed as the first semiconductive layer body of channel layer, the second semiconductor layer as barrier layer,
Etch stop layer and the 3rd semiconductor layer that hetero-junctions can be formed with the second semiconductor layer, wherein, with respect to selected etching material,
The composition material of described etch stop layer has higher etch resistant performance than the composition material of described 3rd semiconductor layer；
Described 3rd semiconductor layer forms layer of gate electrode material, then pattern mask is set in described layer of gate electrode material,
And layer of gate electrode material and the 3rd semiconductor layer are performed etching, thus forming gate electrode, and make the second semiconductor layer or etching eventually
Only layer exposes；
And, setting source electrode and drain electrode on the device being formed by abovementioned steps, thus obtain described HEMT.
In certain embodiments, described preparation method may also include：Described layer of gate electrode material arranges pattern mask, and
Performed etching with selecting engraving confrontation the 3rd semiconductor layer, until the partial zones on described etching material and the second semiconductor layer top layer
The regional area on domain or etch stop layer top layer stops etching after reacting and being formed in situ nature passivation layer.
Wherein, composition material of described barrier layer, channel layer, etch stop layer etc. can be as indicated earlier.
More preferred, described preparation method may also include：After forming gate electrode, passivation layer is set in obtained device surface,
And processing forms window region on described passivation layer, setting source electrode and drain electrode in described window region afterwards, thus obtain institute
State HEMT.
More preferred, described preparation method may also include：After growth forms the 3rd semiconductor layer, active to obtained device
Area carries out isolation processing, arranges layer of gate electrode material afterwards again on the 3rd semiconductor layer.
In certain embodiments, described preparation method may also include：Shape is grown between the first semiconductor layer and the second semiconductor layer
Become interposed layer.
In certain embodiments, described preparation method may also include：Between substrate and hetero-junctions, growth forms cushion.
The present invention is directed to existing p-type gate technique, passes through epitaxial growth etch stop layer, effectively solving chip work in material epitaxy aspect
In skill the problems such as the accurate etching of p-type layer, etching injury, enhancement mode HEMT active area is carried out with effective protection, improve enhancement mode
HEMT device performance.On this basis, in conjunction with suitable etching technics, complete semiconductor surface in etching technics situ
Natural passivation layer is formed, and this passivation layer can play crucial protective effect, thus effectively reducing due to follow-up passivation layer deposition work
Skill and cause surface damage the problems such as (mainly have plasma bombardment to cause) and the material electrology characteristic that thus brings is disliked
The problems such as change, main inclusion sheet resistance change is big, electric current collapses specially good effect and should significantly wait.
More specifically illustrate below in conjunction with some embodiments and accompanying drawing technical scheme.Postscript, real as follows
Applying the various products structural parameters employed in example, various reaction partner and process conditions is all more typical example, but
Through the checking of inventor's lot of experiments, in those listed above other Different structural parameters, other types of reaction partner
And other process conditions are also all applicable, and also all claimed technique effect invented by attainable cost.
As shown in figure 11, it includes cushion, the Al being formed on substrate to the structure of this HEMT of embodiment 1xGa1-xN/GaN is different
Matter knot (x=0.1～0.35), AlN etch stop layer, passivation layer, source electrode (abbreviation source electrode), drain electrode (referred to as drain),
Gate electrode (abbreviation grid) etc..Wherein, substrate can be the substrate such as sapphire, carborundum, gallium nitride, aluminium nitride, but not
It is limited to this.And the material of cushion can industry be commonly used, for example, can be GaN, AlGaN etc..
A kind of method preparing this HEMT that the present embodiment provides may include steps of：
S1：The HEMT based on AlGaN/GaN hetero-junctions for the MOCVD epitaxy growth.Wherein, AlGaN potential barrier Al component x is
10%～35%, thickness is 5～25nm；AlN interposed layer is about 1nm；GaN channel layer is 50～200nm, outside HEMT
Prolong structure as shown in Figure 2.
S2：MOCVD epitaxial growth AlN etch stop layer, thickness is 0.5～5nm, as shown in Figure 3.
S3：MOCVD epitaxy grows p-GaN, and thickness is 5～300nm, and mg-doped concentration range is 1018～1021/cm3Magnitude,
As shown in Figure 4.But it should be noted that, wherein mg-doped concentration is not limited to single doping content, can also be epitaxial growth z side
To function.
S4：Active area isolation.Isolated using N ion implantation technique, ion implantation energy is 150～400KeV ion
Injection, injects ion dose 1012～1014/cm2, injection depth is to exceed cushion 50～250nm, as shown in Figure 5.
S5：Gate metal deposition.Tungsten (W) metal deposit is carried out using magnetron sputtering, thickness 50～200nm, as shown in Figure 6.
S6：Gate metal and p-GaN etching.Mask is made using photoresist AZ5214, plasma quarter is carried out to non-area of grid
Erosion：First, using IBE (Ion Beam Etch, ion beam etching), tungsten metal is performed etching；Secondly, using ICP (Inductive
Coupled Plasma, inductively coupled plasma) lithographic technique performs etching to p-GaN, etching gas Cl2/BCl3/N2/O2
In, oxygen content volume ratio accounts for 2%～70%, and etch rate controls in 5～40nm/min.By AlN etch stop layer control
The etching depth of p-GaN processed, the scope control that AlN etch stop layer can be etched, in 0～5nm, generates oxide layer Al2O3
Thickness about 0.5～5nm.As shown in Figure 7.
S7：Passivation layer deposition.By the cvd dielectric layer technology such as PECVD, ICP-CVD, LPCVD, carry out SiNx(0 ＜ x
≤ 3) passivation layer deposition, thickness 50～500nm, as shown in Figure 8.
S8：Passivation layer etching windowing.By RIE (Reactive Ion Etch, reactive ion etching) to SiNxPerform etching,
Realize Ohmic contact windowing, as shown in Figure 9.
S9：Source and drain Ohmic contact, the preparation of source field plate.Preparation condition：Metal Ti/Al/Ni/Au, thickness is 20nm/130nm/50
Nm/150nm, annealing conditions are 890 DEG C, 30s, nitrogen atmosphere, as shown in Figure 10.
S10：Lead electrode.Preparation condition：W metal/Au, thickness is 50nm/400nm, as shown in figure 11.
As shown in figure 14, it includes cushion, the Al being formed on substrate to the structure of this HEMT of embodiment 2xGa1-xN/GaN is different
Matter knot (x=0.1～0.4), passivation layer, source electrode (abbreviation source electrode), drain electrode (referred to as draining), gate electrode (abbreviation grid
Pole) etc..In barrier layer, Al component is in that step changes barrier layer with growth z direction, and high Al contents AlGaN terminates as etching
Layer (Al0.4Ga0.6N).
A kind of method preparing this HEMT that the present embodiment provides may include steps of：
S1：The HEMT based on AlGaN/GaN hetero-junctions for the MOCVD epitaxy growth.Wherein, AlGaN potential barrier Al component x edge
Epitaxial growth z direction is respectively 10%, 20%, 30%, 40%, and barrier layer thickness is 5～25nm；AlN interposed layer is about 1nm；
GaN channel layer is 50～200nm, and HEMT epitaxial structure is as shown in Figure 12 a- Figure 12 b.
S2：MOCVD epitaxy grows p-GaN, and thickness is 5～300nm, and mg-doped concentration range is 1018～1021/cm3
Magnitude, as shown in figure 13.
S3～S9：With S4～S10 in embodiment 1.In " gate metal and p-GaN etching ", high Al contents AlGaN in barrier layer,
I.e. Al0.4Ga0.6N is etch stop layer, using itself higher etching selection ratio and p-GaN between, controls p-GaN etching depth.
Meanwhile, by oxygenous etching gas Cl2/BCl3/N2/O2Carry out ICP etching, oxygen content volume ratio accounts for 2%～70%, life
Become oxide layer Al2O3 THICKNESS CONTROL in 0.5～5nm.The device completing after whole chip technology is as shown in figure 14.
As shown in figure 17, it includes cushion, the Al being formed on substrate to the structure of embodiment 3HEMTxGa1-xN/GaN is heterogeneous
Knot (x=0.1～0.4), passivation layer, source electrode (abbreviation source electrode), drain electrode (referred to as draining), gate electrode (abbreviation grid)
Deng.In barrier layer, with growth z direction is linear and step combination and variation barrier layer, high Al contents AlGaN is as quarter for Al component
Erosion stop layer (Al0.4Ga0.6N)
A kind of method preparing this HEMT that the present embodiment provides may include steps of：
S1：The HEMT based on AlGaN/GaN hetero-junctions for the MOCVD epitaxy growth.Wherein, AlGaN potential barrier Al component x edge
Epitaxial growth z direction linearly changes first, and Al change of component scope is 10% to 30%；Then, Al component x remains 40%.
Barrier layer thickness is 5～25nm；AlN interposed layer is about 1nm；GaN channel layer is 50～200nm, and HEMT epitaxial structure is such as
Shown in Figure 15 a- Figure 15 b.
S2：MOCVD epitaxy grows p-GaN, and thickness is 5～300nm, and mg-doped concentration range is 1018～1021/cm3Magnitude,
As shown in figure 16.
S3：With S4～S10 in embodiment 1.In " gate metal and p-GaN etching ", high Al contents AlGaN in barrier layer,
I.e. Al0.4Ga0.6N is etch stop layer, using itself higher etching selection ratio and p-GaN between, controls p-GaN etching depth.
Meanwhile, by oxygenous etching gas Cl2/BCl3/N2/O2Carry out ICP etching, oxygen content volume ratio accounts for 2%～70%, life
Become oxide layer Al2O3THICKNESS CONTROL is in 0.5～5nm.The device completing after whole chip technology is as shown in figure 17.
As shown in figure 20, it includes cushion, the Al being formed on substrate to the structure of embodiment 4HEMTxGa1-xN/GaN is heterogeneous
Knot (x=0.1～0.5), passivation layer, source electrode (abbreviation source electrode), drain electrode (referred to as draining), gate electrode (abbreviation grid)
Deng.Wherein, barrier layer is heterogeneous multi-layer junction structure, and high Al contents AlGaN is as etch stop layer (Al0.4Ga0.6N/Al0.5Ga0.5N)
A kind of method preparing this HEMT that the present embodiment provides may include steps of：
S1：The HEMT based on AlGaN/GaN hetero-junctions for the MOCVD epitaxy growth.Wherein, AlGaN potential barrier Al component x edge
Epitaxial growth z direction change is as shown in Figure 18 a- Figure 18 b.Barrier layer thickness is 5～25nm；AlN interposed layer is about 1nm；GaN
Channel layer is 50～200nm.
S2：MOCVD epitaxy grows p-GaN, and thickness is 5～300nm, and mg-doped concentration range is 1018～1021/cm3
Magnitude, as shown in figure 19.
S3：With S4～S10 in embodiment 1.In " gate metal and p-GaN etching ", high Al contents AlGaN in barrier layer,
I.e. Al0.4Ga0.6N/Al0.5Ga0.5N is etch stop layer, using itself higher etching selection ratio and p-GaN between, controls p-GaN
Etching depth.Meanwhile, by oxygenous etching gas Cl2/BCl3/N2/O2Carrying out ICP etching, oxygen content volume ratio accounts for 2%～
70%, generate oxide layer Al2O3THICKNESS CONTROL is in 0.5～5nm.The device completing after whole chip technology is as shown in figure 20.
It should be noted that herein, term " inclusion ", "comprising" or its any other variant are intended to nonexcludability
Comprise so that including a series of process of key elements, method, article or equipment not only include those key elements, but also
Including other key elements being not expressly set out, or also include for this process, method, article or intrinsic the wanting of equipment
Element.In the absence of more restrictions, the key element being limited by sentence "including a ..." is it is not excluded that including described wanting
Also there is other identical element in the process of element, method, article or equipment.
The above is only the specific embodiment of the present invention it is noted that coming for those skilled in the art
Say, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (10)
1. a kind of group III-nitride enhancement mode HEMT based on p-type layer, comprise main by as channel layer the first semiconductor layer and
Hetero-junctions as the second semiconductor layer composition of barrier layer and the source electrode, gate electrode and the drain electrode that are connected with described hetero-junctions,
Threeth semiconductor layer that can with second semiconductor layer form hetero-junctions is also distributed with, its feature exists between described gate electrode and barrier layer
In：
Etch stop layer is also distributed between described 3rd semiconductor layer and the second semiconductor layer, and, with respect to selected engraving
Matter, the composition material of described etch stop layer has higher etch resistant performance than the composition material of described 3rd semiconductor layer；
Or, with respect to selected etching material, the group in the region closed on the 3rd semiconductor layer in described second semiconductor layer is become a useful person
Material has higher etch resistant performance than the composition material of the 3rd semiconductor layer.
2. group III-nitride enhancement mode HEMT based on p-type layer according to claim 1 is it is characterised in that described etching is whole
Only it is additionally provided with passivation layer on layer or the second semiconductor layer, described passivation layer includes the partial zones at least by described etch stop layer top layer
The regional area on domain or the second semiconductor layer top layer and the described natural passivation layer etching substance reaction and being formed in situ.
3. group III-nitride enhancement mode HEMT based on p-type layer according to claim 1 it is characterised in that：
The composition material of described barrier layer is at least selected from AlxInyGazN(0<X≤1,0≤y≤1, (x+y+z)=1)；
And/or, the composition material of described channel layer includes any one in GaN, InGaN, AlGaN, AlInN, AlInGaN
Plant or two or more combinations；
And/or, the composition material of described 3rd semiconductor layer includes p-GaN, p-AlGaN, p-AlInN, p-InGaN, p-AlInGaN
In any one or two or more combinations；
And/or, the composition material of described etch stop layer includes AlN, SiNx(0<x≤3)、AlxGa1-xN(0<x<1)
In any one or two or more combinations；
Preferably, the composition material of described barrier layer is selected from AlxInyGazN(0<X≤1,0≤y≤1, (x+y+z)=1), its
In along from first semiconductor layer point to the 3rd semiconductor layer direction, x totally be in increase trend.
4. group III-nitride enhancement mode HEMT based on p-type layer according to any one of claim 1-3 it is characterised in that
Described selected etching material is at least selected from the etching gas containing aerobic.
5. group III-nitride enhancement mode HEMT based on p-type layer according to any one of claim 1-3 it is characterised in that
Described hetero-junctions also includes the interposed layer being distributed between the first semiconductor layer and the second semiconductor layer；
Preferably, the composition material of described interposed layer include in AlN, AlInN, AlInGaN any one or two or more
Combination.
6. a kind of preparation method of group III-nitride enhancement mode HEMT based on p-type layer is it is characterised in that include：
On substrate, growth is formed as the first semiconductive layer body of channel layer, the second semiconductor layer as barrier layer and energy successively
Form the 3rd semiconductor layer of hetero-junctions with the second semiconductor layer, wherein, with respect to selected etching material, described second quasiconductor
The composition material in the region closed on the 3rd semiconductor layer in layer has higher etch resistance than the composition material of the 3rd semiconductor layer
Can,
Or, on substrate successively growth formed as the first semiconductive layer body of channel layer, the second semiconductor layer as barrier layer,
Etch stop layer and the 3rd semiconductor layer that hetero-junctions can be formed with the second semiconductor layer, wherein, with respect to selected etching material,
The composition material of described etch stop layer has higher etch resistant performance than the composition material of described 3rd semiconductor layer；
Described 3rd semiconductor layer forms layer of gate electrode material, then pattern mask is set in described layer of gate electrode material,
And layer of gate electrode material and the 3rd semiconductor layer are performed etching, thus forming gate electrode, and make the second semiconductor layer or etching eventually
Only layer exposes；
And, setting source electrode and drain electrode on the device being formed by abovementioned steps, thus obtain described HEMT.
7. preparation method according to claim 6 is it is characterised in that include：Figure is arranged on described layer of gate electrode material
Change mask, and performed etching with selecting engraving confrontation the 3rd semiconductor layer, until described etching material and the second semiconductor layer table
The regional area on the regional area of layer or etch stop layer top layer stops etching after reacting and being formed in situ nature passivation layer.
8. the preparation method according to any one of claim 6-7 it is characterised in that：The composition material of described barrier layer is at least
Selected from AlxInyGazN(0<X≤1,0≤y≤1, (x+y+z)=1)；
And/or, the composition material of described channel layer includes any one in GaN, InGaN, AlGaN, AlInN, AlInGaN
Plant or two or more combinations；
And/or, the composition material of described 3rd semiconductor layer includes p-GaN, p-AlGaN, p-AlInN, p-InGaN, p-AlInGaN
In any one or two or more combinations；
And/or, the composition material of described etch stop layer includes AlN, SiNx(0<x≤3)、AlxGa1-xN(0<x<1)
In any one or two or more combinations；
Preferably, the composition material of described barrier layer is selected from AlxInyGazN(0<X≤1,0≤y≤1, (x+y+z)=1), its
In along from first semiconductor layer point to the 3rd semiconductor layer direction, x totally be in increase trend.
9. the preparation method according to any one of claim 6-7 is it is characterised in that described selected etching material is at least selected from and contains
The etching gas of aerobic.
10. preparation method according to claim 6 is it is characterised in that also include：After forming gate electrode, in obtained device
Surface arranges passivation layer, and processing forms window region on described passivation layer, setting source electrode and leakage in described window region afterwards
Electrode, thus obtain described HEMT.
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| PCT/CN2015/099175 WO2017036025A1 (en) | 2015-09-01 | 2015-12-28 | Iii-group nitride enhanced type hemt and preparation method therefor |
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