CN106484364B - Randomizer based on transition effect ring oscillator - Google Patents
Randomizer based on transition effect ring oscillator Download PDFInfo
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- CN106484364B CN106484364B CN201610888531.8A CN201610888531A CN106484364B CN 106484364 B CN106484364 B CN 106484364B CN 201610888531 A CN201610888531 A CN 201610888531A CN 106484364 B CN106484364 B CN 106484364B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/588—Random number generators, i.e. based on natural stochastic processes
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Abstract
The invention discloses a kind of randomizers based on transition effect ring oscillator, including：One random number core circuit, it is final to stablize in fixed high level or low level for generating one section of oscillator signal for being not fixed the time；One control circuit, the reset signal for generating the random number core circuit and counter circuit；One counter enables random number core circuit after resetting；The pulse generated to random number core circuit counts.The present invention has higher rate and better attack tolerant energy.The present invention can be used in various cryptographic systems.
Description
Technical field
The present invention relates to information securities and integrated circuit fields, and transition effect ring oscillator is based on more particularly to one kind
Randomizer.
Background technology
It is well known that information security is more and more important in contemporary society, and the core of information security is chip, with integrated
The fast development of circuit technology, chip are widely used in all trades and professions, in the safety chip that finance, security fields use to core
More stringent requirements are proposed for the safety of piece, and real random number generator is the key component of safety chip.
Usually there are two types of realization method, pseudo random number and real random number generators for randomizer.Pseudo random number is general
It is generated with digital timing circuit, as long as giving a seed, the random number generated is typically long period series, theoretically can be with
Prediction.Most common structure is linear feedback shift register (LFSR) in pseudorandom number generator.Generally with deposit on circuit
Device and XOR gate are realized.It selects certain register-combinatorial tap to be connected to XOR gate, most macrocyclic sequence can be reached so that
Sequence is similar random.Due to the fixed algorithm of pseudo random number, as long as given seed, sequence is exactly completely specified.Therefore,
Theoretically pseudo random number is foreseeable.
Real random number generator is typically based on the noise of device, it usually needs is realized using the analog circuit of full custom.
Compared with pseudo random number, sequence caused by real random number generator is uncertain, it is thus possible to better protection information
Transmission.
However, conventional real random number generator is made of analog circuit, but the rate of its output random number is relatively low, usually
Less than 1Mbps.
Invention content
The technical problem to be solved in the present invention is to provide a kind of randomizer based on transition effect ring oscillator,
With higher rate and better attack tolerant energy.
In order to solve the above technical problems, the randomizer based on transition effect ring oscillator of the present invention, including：
One random number core circuit, it is final to stablize in fixed high electricity for generating one section of oscillator signal for being not fixed the time
Flat or low level；
One control circuit, the reset signal for generating the random number core circuit and counter circuit；
One counting circuit enables random number core circuit after resetting；The pulse that random number core circuit is generated
It is counted；
The random number core circuit is made of asymmetric RS latch, i.e., two branches of the described RS latch prolong
Slow Time Inconsistency, but the logic function of two branches is consistent.
The duration of oscillation of the random number core circuit, the number of oscillation are related to the thermal noise of random number core circuit.
All circuits of the present invention are made of digital circuit unit, and circuit can be placed in digital circuit, when placement-and-routing
It is mixed in digital circuit, safety higher, there is better attack tolerant energy.Compared with traditional true random number circuit, this hair
Faster, the random number rate of output can reach several Mbps to the rate of bright output random number；By improving random number core circuit
Frequency of oscillation can improve the random performance of circuit.
The present invention can be used in various cryptographic systems.
Description of the drawings
The present invention is described in further detail with specific implementation mode below in conjunction with the accompanying drawings：
Fig. 1 is the random number generator circuit schematic diagram based on transition effect ring oscillator；
Fig. 2 is one schematic diagram of random number core circuit embodiment in Fig. 1；
Fig. 3 is one schematic diagram of random number core circuit embodiment in Fig. 1；
Fig. 4 is one embodiment schematic diagram of control circuit in Fig. 1；
Fig. 5 is one embodiment schematic diagram of counting circuit in Fig. 1.
Specific implementation mode
In conjunction with shown in Fig. 1, the randomizer based on transition effect ring oscillator, including：Random number core
Circuit, control circuit and counting circuit.
The random number core circuit is the key that the randomizer portion based on transition effect ring oscillator
Point, it be generate random number source, be made of asymmetric RS latch, with traditional RS latch difference lies in it not
Symmetry, i.e. the two of latch branch is inconsistent, the delay time that two branches are shown as in sequential be it is unequal,
Two branch inconsistencies can be ensured when design from circuit or on domain, due to this asymmetry of RS latch
So that latch will appear temporary oscillation, i.e. there is metastable state phenomenon in latch, and being influenced the number of oscillation by device noise is
Random, counting is carried out to the number of oscillation and can be obtained by random number SJS (in conjunction with Fig. 1).
The control circuit coordinates random number core circuit and counting circuit and designs, and meter is must assure that in sequential
Random number core circuit is enabled again after the completion of number circuit reset, just can ensure that correct counting in this way.Control circuit is by digital units
Basic element circuit in library is constituted.
The counting circuit is a kind of common asynchronous counting circuit structure, since the random number for only needing to obtain one is defeated
Go out, therefore chooses output signals of the lowest order D0 as random number in counting circuit.Counting circuit is by d type flip flop circuit, number
Word buffer circuit is constituted.
Fig. 2 is the schematic diagram of the random number core circuit embodiment one.It is made of asymmetric RS latch.RS is latched
Device can be all made of NAND gate (referring to Fig. 2), can also be made of NAND gate and phase inverter (referring to Fig. 3), can also be by
Other equivalent logic circuits are constituted.Meanwhile the circuit asymmetry is mainly reflected in prolonging for two branches of RS latch
Slow Time Inconsistency, but the logic function of two branches is consistent.In the present embodiment, the first branch 21 of RS latch
(dotted line frame in Fig. 2) is made of 4 concatenated NAND gates, NAND gate one termination high level VDD, the other end of NAND gate and
The output end of adjacent NAND gate realizes that head and the tail are connected, the output of the first branch 21 to the first buffer HC1 and the second NAND gate
An input terminal of NAND2, the output of the first buffer HC1 are the output signal t_out of random number core circuit.RS latch
Another branch, that is, the second branch 22 (dotted line frame in Fig. 2) is made of 6 concatenated NAND gates, the high electricity of a termination of NAND gate
The output end of flat VDD, the other end of NAND gate and adjacent NAND gate realizes that head and the tail are connected.By adjusting the not right of RS latch
Title property adjusts the frequency of oscillation and the number of oscillation of random number core circuit, and that the first branch 21 can be adjusted to 2,4,6,8 ... is even
Several NAND gates, the second branch 22 can be adjusted to 4,6,8,10 ... even number NAND gates, and the NAND gate of the second branch 22
Number is more than the NAND gate number of the first branch 2, so that it is guaranteed that the asymmetry of two branches of RS latch.The first branch 21 it is defeated
Enter end with the output end of the first NAND gate NAND1 to be connected, the one of the output end of the second branch 22 and the first NAND gate NAND1 is defeated
Enter end to be connected, the input terminal of the second branch 22 is connected with the output end of the second NAND gate NAND2；First NAND gate NAND1
Another input terminal and another input terminal of the second NAND gate NAND2 be connected with the output end of the second buffer HC2, second is slow
Rush the enable signal (t_en) of the input terminal input random number core circuit of device HC2.
Fig. 3 is another realization method (embodiment two) of random number core circuit, a branch 31 (figure of RS latch
Dotted line frame in 3) it is made of 4 concatenated phase inverters, phase inverter head and the tail are connected, the output of branch 31 to the first buffer HC1,
The output of buffer HC1 is signal t_out.Another branch 32 (dotted line frame in Fig. 3) of RS latch is concatenated anti-by 6
Phase device forms, and phase inverter head and the tail are connected.The oscillation of random number core circuit is adjusted by adjusting the asymmetry of RS latch
Frequency and the number of oscillation, branch 31 can be adjusted to 2,4,6,8 ... even number of inverters, branch 32 can be adjusted to 4,6,8,
10 ... even number of inverters, and the phase inverter number of branch 32 is more than the phase inverter number of branch 31, so that it is guaranteed that RS latch
The asymmetry of two branches.
It is to be noted that asymmetry RS latch not only limits to and Fig. 2, both Fig. 3 realization method, as long as ensureing RS locks
The delay time inconsistent random number core circuit structure that the present invention can be achieved of two branches of storage.
Referring to Fig. 4, the control circuit is made of the basic element circuit in digital units library, contain buffer HC3,
HC4, delay unit circuit DLY1, DLY2, NAND gate circuit NAND3, AND gate circuit AND1, OR circuit OR1.Control circuit
The input terminal of enable signal EN input third buffers HC3, an input of the output end connection and door AND1 of third buffer HC3
End, the output end of the second delay unit circuit DLY 2 is connect with another input terminal of door AND1, is exported with the output end of door AND1
Signal t_en.Clock signal clk inputs the input terminal of the 4th buffer HC4, and the output end connection first of the 4th buffer HC4 is prolonged
One input terminal of the input terminal and third NAND gate NAND3 of slow element circuit DLY1, the first delay unit circuit DLY1's is defeated
Outlet connects another input terminal of third NAND gate NAND3, and the output end of third NAND gate NAND3 connects the second delay cell electricity
The input terminal of road DLY2 and/or an input terminal of door OR1, the output end of the second delay unit circuit DLY2 is connected to or door OR1
Another input terminal or door OR1 output end output reset signal RST.
Shown in described counting circuit combination Fig. 5, in the embodiment shown in fig. 5, eased up by d type flip flop DCF1-DCF10
Device HC5-HC14 compositions are rushed, are a kind of asynchronous counting circuits, choose random numbers of the lowest order D0 as output in counting circuit.
The output end that D0-D9 in Fig. 5 is buffer HC5-HC14.
Although the present invention is illustrated using specific embodiment, the present invention's is not intended to limit to the explanation of embodiment
Range.One skilled in the art is by reference to explanation of the invention, without departing substantially from the spirit and scope of the present invention
In the case of, it is easy to carry out various modifications or embodiment can be combined.
Claims (6)
1. a kind of randomizer based on transition effect ring oscillator, which is characterized in that including：
One random number core circuit, for generating one section of oscillator signal for being not fixed the time, it is final stablize in fixed high level or
Low level；
One control circuit, the reset signal for generating the random number core circuit and counter circuit,
One counting circuit enables random number core circuit after resetting；The pulse that random number core circuit generates is carried out
It counts；The random number core circuit is made of asymmetric RS latch, i.e., the delay of two branches of the described RS latch
Time Inconsistency, but the logic function of two branches is consistent.
2. randomizer as described in claim 1, it is characterised in that：The first branch of the RS latch is by even number
NAND gate is constituted, and the second branch is also made of even number NAND gate, and the NAND gate number of the second branch is more than the first branch
NAND gate number.
3. randomizer as described in claim 1, it is characterised in that：The first branch of the RS latch is by even number
Phase inverter is constituted, and the second branch is also made of even number of inverters, and the phase inverter number of the second branch is more than the first branch
Phase inverter number.
4. randomizer as described in claim 1, it is characterised in that：The duration of oscillation of the random number core circuit,
The number of oscillation is related to the thermal noise of random number core circuit.
5. randomizer as described in claim 1, it is characterised in that：The control circuit includes third buffer,
Four buffers, the first delay unit circuit, the second delay unit circuit, third NAND gate, first and door, first or door；
The input terminal of the enable signal EN input third buffers of control circuit, the output end connection first of third buffer and door
An input terminal, first connect the output end of the second delay unit circuit with another input terminal of door, first with the output end of door
Output signal t_en；Clock signal clk inputs the input terminal of the 4th buffer, the first delay of output end connection of the 4th buffer
The input terminal of element circuit and an input terminal of third NAND gate, the first delay unit circuit output end connection third with it is non-
Another input terminal of door, the output end of third NAND gate connect the input terminal and first or one of door of the second delay unit circuit
Input terminal, the output end of the second delay unit circuit are connected to another input terminal of first or door, first or door output end it is defeated
Go out reset signal RST.
6. randomizer as described in claim 1, it is characterised in that：The counting circuit is by d type flip flop and buffer
Composition is asynchronous counting circuit, chooses random numbers of the lowest order D0 as output in counting circuit.
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| CN201610888531.8A CN106484364B (en) | 2016-10-12 | 2016-10-12 | Randomizer based on transition effect ring oscillator |
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| CN201610888531.8A CN106484364B (en) | 2016-10-12 | 2016-10-12 | Randomizer based on transition effect ring oscillator |
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| CN106484364B true CN106484364B (en) | 2018-10-26 |
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| CN110825347B (en) * | 2018-08-09 | 2023-05-09 | 旺宏电子股份有限公司 | Adjustable random number generation circuit and adjustable random number generation method |
| CN110851331B (en) * | 2019-11-13 | 2021-11-16 | 中国电子科技集团公司第五十八研究所 | On-chip monitoring circuit of antifuse Field Programmable Gate Array (FPGA) |
| TWI765479B (en) * | 2020-12-17 | 2022-05-21 | 國立中山大學 | Random number generator |
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| EP1239363A3 (en) * | 2001-03-07 | 2005-01-19 | Kabushiki Kaisha Toshiba | Random number's seed generating circuit, driver having the same, and SD memory card system |
| CN101788899A (en) * | 2010-01-08 | 2010-07-28 | 浙江大学 | Low power consumption digital true random source |
| US8583711B2 (en) * | 2009-12-02 | 2013-11-12 | Seagate Technology Llc | Random number generation system with ring oscillators |
| CN104572014A (en) * | 2013-10-15 | 2015-04-29 | 飞思卡尔半导体公司 | True random number generator with repeatedly-activated oscillators |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20100281088A1 (en) * | 2009-04-29 | 2010-11-04 | Psigenics Corporation | Integrated true random number generator |
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| EP1239363A3 (en) * | 2001-03-07 | 2005-01-19 | Kabushiki Kaisha Toshiba | Random number's seed generating circuit, driver having the same, and SD memory card system |
| US8583711B2 (en) * | 2009-12-02 | 2013-11-12 | Seagate Technology Llc | Random number generation system with ring oscillators |
| CN101788899A (en) * | 2010-01-08 | 2010-07-28 | 浙江大学 | Low power consumption digital true random source |
| CN104572014A (en) * | 2013-10-15 | 2015-04-29 | 飞思卡尔半导体公司 | True random number generator with repeatedly-activated oscillators |
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