CN106470024A - Glitch-free clock switch circuit using Muller C-element - Google Patents
Glitch-free clock switch circuit using Muller C-element Download PDFInfo
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- CN106470024A CN106470024A CN201510659344.8A CN201510659344A CN106470024A CN 106470024 A CN106470024 A CN 106470024A CN 201510659344 A CN201510659344 A CN 201510659344A CN 106470024 A CN106470024 A CN 106470024A
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Abstract
The present invention relates to using the glitch-free clock switch circuit of Muller C-element, including the first and second clock lines, the first and second selection lines, the first to the 4th Muller C-element. Muller C-element is connected to clock line and selection line and the first and second gates.First and second delay cells are connected to clock line and second and the 4th Muller C-element.First AND-gate is connected to the first clock line, the output of the first Muller C-element and the first delay cell.Second AND-gate is connected to the second delay cell, the 3rd Muller C-element and second clock line, and OR door is connected to the first and second AND-gate.
Description
Technical field
The present invention is directed to integrated circuit package, specifically, for a kind of using Muller (Muller) C unit
The clock switch circuit of part.
Background technology
In the integrated circuit (IC) with multiple clocks, there is provided a kind of switching circuit.The most conventional cuts
Change circuit and include multiple triggers, it consumes a large amount of board area (or chip area) in transistor form.
In addition, this circuit generally can not complete handoff functionality when a clock stops.
Accordingly, it is desirable to provide a kind of clock switch circuit, it uses less transistor, thus expending less
Space, even if can also complete when clock stops to switch, and when being easy to extension to accommodate more
Clock.
Brief description
Exemplary and show the present invention without limitation by the embodiment shown in accompanying drawing, in the accompanying drawings,
The similar key element of similar reference instruction. show the key element of in figure for simplicity and clarity, but differ
Surely it is drawn to scale. it is interesting to note that exaggerating some vertical dimensions with respect to some horizontal sizes.
In the accompanying drawings：
Fig. 1 is the schematic circuit of clock switch circuit according to the first advantageous embodiment of the invention；
Fig. 2A is the schematic circuit of traditional Muller C-element；
Fig. 2 B can be applied to the logical value table of the Muller C-element of Fig. 2A；
Fig. 3 is the schematic circuit for the delay cell in the clock switch circuit of Fig. 1；
Fig. 4 is the schematic circuit of clock switch circuit according to the second, preferred embodiment of the present invention；And
Fig. 5 is the schematic circuit of the clock switch circuit of the third preferred embodiment according to the present invention.
Specific embodiment
In one embodiment, the invention provides a kind of clock switch circuit, including：First clock line,
First clock signal is provided；Second clock line, provides second clock signal；First choice line, provides first
Selection signal；Second selection line, provides the second selection signal；First Muller C-element, connects in its input
To the first clock line and first choice line；Second Muller C-element, its input be connected to first choice line and
The output of the first gate；3rd Muller C-element, is connected to the second selection line and the second logic in its input
The output of door；4th Muller C-element, is connected to the second selection line and second clock line in its input；First
Delay cell, is connected to the first clock line and the output of the second Muller C-element in its input；Second postpones list
Unit, is connected to output and the second clock line of the 3rd Muller C-element in its input；First AND-gate,
Its input is connected to the output of the first clock line, the output of the first Muller C-element and the first delay cell；The
Two AND-gate, its input be connected to the output of the second delay cell, the output of the 4th Muller C-element and
Second clock line；And OR door, it is connected to the output of the first and second AND-gate in its input, and defeated at it
Going out to provide output clock signal. first choice signal is used for being chosen as exporting clock signal by the first clock signal,
It is output clock signal that second selection signal is used for second clock signal behavior.
In another embodiment, the invention provides a kind of clock switch circuit, including：Multiple clock lines,
Each clock lines all provide respective clock signal；OR door, provides output clock signal；A plurality of selection
Line, each selection line both corresponds to respective clock lines in multiple clock lines, and provides selection signal,
For corresponding clock signal is chosen as exporting clock signal；And multiple clock selection module.Each when
Clock selecting module all includes the first Muller C-element, and its input is connected to corresponding clock line and corresponding selection
Line, and the second Muller C-element, its input is connected to corresponding selection line and the output of the first AND-gate.
One input of the first AND-gate is connected to corresponding selection line, receives the output of OR door in another input
Inverse value. the input of delay cell is connected to corresponding clock line and the output of the second Muller C-element.
The input of two AND-gate is connected to corresponding clock line, the output of the first Muller C-element and delay cell
Output.The output of the second AND-gate is connected to the input of OR door.
Select refer to the attached drawing, wherein, middle identical reference is used for indicating identical in the whole text in several accompanying drawings
Assembly, shows the first embodiment of the clock switch circuit 10 according to the present invention in Fig. 1.Electricity in Fig. 1
Road 10 includes the first clock line 12 and second clock line 14, and it provides the first and second clock signals respectively
clk1、clk2.It should be understood that circuit 10 can comprise more than two clock lines, such as shown in Fig. 5.
Circuit 10 also includes first choice line 16 and the second selection line 18, and it provides the first and second choosings respectively
Select signal select1、select2. in the embodiment shown in fig. 1, the second selection line 18 is phase inverter 20
Output, phase inverter 20 be connected to first choice line 16. in its input thus, the second choosing shown in embodiment
Select signal select2It is first choice signal select1Anti-phase form.But this structure can in turn, or
Person first and second selection signal select1、select2It can be separate and distinct signal.First and second choosings
Select signal select1、select2For selecting corresponding first or second clock signal clk1、clk2, to use
Make output clock signal out_clk. of the output 22 in circuit 10
Circuit 10 also includes multiple Muller C-element 24,26,28,30. and shows conventional Mu in fig. 2
Strangle C-element design.Muller C-element receives two inputs A, B, and the two is all fed to the upper pull-up network of composition
Respective p-type metal oxide semiconductor (PMOS) transistor M0, M1 and constitute pulldown network
Respective N-shaped (NMOS) transistor M2, M3.Node between networks exports with phase inverter
11 latch, phase inverter 11 is coupled to the output Z of Muller C-element, and company in parallel with weak phase inverter 13
Connect. but other designs of Muller C-element can also be suitable to the present invention, including the design with reset capability etc.
If Fig. 2 B shows the regular logical table of input A, the B and output Z for Muller C-element.
Input A, B are low, if output Z is also low. input A, B are high, and output Z is also height. such as
Input A, B are different for fruit, and output Z is maintained for its current state.
Refer again to Fig. 1, the input of the first Muller C-element 24 is connected to the first clock line 12 and the first choosing
The input selecting line 16. second Muller C-element 26 is connected to first choice line 16 and the first gate 32
Output. in the embodiment shown in fig. 1, the first gate 32 preferably NOR-gate, its input connects
To the second selection line 18 and second clock line 14.
The output of the second Muller C-element 26 is connected to the input D of the first delay cell 34, and first postpones list
Another input of unit 34 is connected to the first clock line 12. delay cell 34 can be by from the second Muller C unit
The rise edge delay of the signal that part 26 receives is to the first clock signal clk1Trailing edge.
The exemplary embodiment of the first delay cell 34 is shown in Fig. 3. the first delay cell 34 is preferably
Including the first delay Muller C-element 36, its input is connected to the output and first of the second Muller C-element 26
The delay phase inverter 38 of clock line 12. first delay cell 34 is also connected to the first clock line 12. in its input
It is solemn that the output of the first delay Muller C-element 36 and the generation postponing phase inverter 38 may be coupled to the second delay
Strangle the input of C-element 40, the first delay cell 34 is served as in the output of the second delay Muller C-element 40
Output.
The input of the first AND-gate 42 is connected to the first clock line 12, the output of the first Muller C-element 24
Output with the first delay cell 34. first and second Muller C-element the 24,26, first gates 32,
First delay cell 34 and the first AND-gate 42 preferably collectively form clock switching " module ", for selecting
First clock signal clk1.
Additionally provide in circuit 10 for second clock signal clk2Clock switchover module.3rd Muller C unit
The input of part 28 is connected to the defeated of second clock line 14 and the second selection line 18. the 4th Muller C-element 30
Enter the output being connected to the second selection line 18 and the second gate 33.As the first gate 32, this reality
Apply the second gate 33 preferably NOR-gate in example, although its input is connected to first choice line 16
With the first clock line 12.
The output of the 4th Muller C-element 30 is connected to the input D of the second delay cell 44, its another defeated
Enter to be connected to second clock line 14. second delay cell 44 preferably have identical with the first delay cell 34
Structure, as shown in Figure 3. the input of the second AND-gate 46 is connected to second clock line the 14, the 3rd
The output of Muller C-element 28 and the output of the second delay cell 44. the first and second AND-gate 42,46
Output be connected to the input of OR door 48, OR door 48 provides output clock signal in circuit output 22
out_clk.
With reference now to Fig. 4, it is shown that the second embodiment of clock switch circuit. second embodiment is similar to above-mentioned
First embodiment.Similar reference is used for similar key element, real except hundreds word is used for second
Apply example. therefore, eliminate the complete explanation of second embodiment, only explanation difference.
In the embodiment of clock switch circuit 110 shown in Fig. 4, the first gate 132 is AND-gate,
Rather than NOR-gate as shown in Figure 1. the first gate 132 is connected to first choice line 116, also receives
The inverse value of the output of OR door 122, represents in first choice signal select1With output clock signal out_clk
Inverse value between make logic and compare.Similarly, the second gate 133 is AND-gate, and an input is even
It is connected to the second selection line 118, receive the inverse value of the output of OR door 122 in another input.
In both embodiments, compared with the conventional clock switching circuit using trigger, switching circuit 10,
110 use less transistor, take less area.
Embodiments of the invention also allow for expanding clock switching circuit to be used together with multiple clock sources. example
As Fig. 5 shows clock switch circuit 210, has n clock lines 2121-212n, provide n respectively
Clock signal clk1-clkn. additionally provide a plurality of selection line 2161-216n, with corresponding to a respective clock
Line 2121-212n, and be used for corresponding clock signal clk1-clknIt is chosen as the output 222 in circuit 210
Output clock signal out_clk.
Each clock lines 2121-212nAnd corresponding selection line 2161-216nAll with multiple clock selection modules
One of associated.As explained above, reference and nth bar clock line 212nAssociated clock selection module,
Each clock selection module includes：First Muller C-element 224n, its input is connected to corresponding clock
With selection line 212n、216n；And the second Muller C-element 226n, its input is connected to corresponding clock and choosing
Select line 216nWith the first gate 232nOutput (preferably AND-gate, its input is connected to corresponding
Selection line 216n, the inverse value of the output of another input reception OR door 248). each clock selecting mould
Block also includes delay cell 234n, its input is connected to corresponding clock line 212nWith the second Muller C-element
226nOutput. delay cell 234nPreferably with identical shown in Fig. 3. clock selection module is further preferably
Ground includes AND-gate 242n, its input is connected to corresponding clock line 212n, the first Muller C-element 224n
Output and delay cell 234nOutput, and its output is connected to the input of OR door 248.
In the foregoing specification, the particular example with reference to the embodiment of the present invention illustrates the present invention. it will be clear that
In the case of the broader spirit and scope of the present invention illustrating without departing from such as appended claims, Ke Yiyou
This makes multiple modifications and variations.
Described connection can be any to be suitable for coming each node, unit or equipment (for example setting via centre
Standby past) connection of the type of transmission signal. therefore, unless implied that or separately had statement, connection can be
It is directly connected to or be indirectly connected with. may be referred to single connection, multiple connection, unidirectional connection or be bi-directionally connected
To illustrate or to illustrate to connect.But different embodiments can change the implementation of connection.It is, for example possible to use
Individually unidirectional connection, rather than be bi-directionally connected, vice versa. furthermore, it is possible to multiple in order to serial or time-division
The single connection transmitting multiple signals with mode replaces multiple connections.Similarly, transmit the single of multiple signals
Connection can be divided into the multiple different of the subset transmitting these signals to connect.Accordingly, there exist for transmitting signal
Multiple options.
Although illustrating the polarity of specific conduction type or current potential in this example, can be appreciated that, conduction type
Can be contrary with the polarity of current potential. each signal as herein described can be designed to positive or negative logic.
In the case of negative logic signal, signal is Low level effective, and wherein, logically true state corresponds to logic level
Zero. in the case of positive logic signal, signal is that high level is effective, and wherein, logically true state corresponds to logic
Level one. note, any signal as herein described can be designed to negative or positive logical signal. therefore,
In alternate embodiment, illustrate that those signals for positive logic signal may be embodied as negative logic signal, and
Illustrate that those signals for negative logic signal may be embodied as positive logic signal.
In a preferred embodiment switch element is illustrated as transistor, but other types of switching circuit, for example
Mechanical switch, relay etc., it is possible to use these switch elements.Although in addition, some transistors are said
Bright for PMOS or NMOS type, but conductivity can be contrary, is still suitable to the present invention.
In detail in the claims, word " inclusion " or " having " do not exclude the presence of except listing in claim
Other elements in addition or step. additionally, word used herein " " is defined as one or more than one.
Additionally, the use of the guiding phrase of such as " at least one " and " one or more " should not solve in claims
It is interpreted as implying the right that the guiding of another claim elements will be comprised so to guide by indefinite article " "
Any specific rights requirement requiring key element is defined to only comprise the invention of a this key element, even if identical
Claim includes guiding the indefinite article of phrase " one or more " or " at least one " and such as " ". and right
It is also such in the use of definite article.The word of unless otherwise stated, such as " first " and " second " is used for
Arbitrarily distinguish between the key element of this word explanation.Thus, these words are not necessarily intended to indicate that this wanting
The time of element or other priority. the fact that state some means in claim different from each other does not indicate that
The combination of these means can not be used.
Claims (10)
1. a kind of clock switch circuit, including：
First clock line and the second clock line of the first clock signal and second clock signal are provided；
The first choice line of offer first choice signal and the second selection signal and the second selection line；
First Muller C-element, is connected to the first clock line and first choice line in its input；
Second Muller C-element, is connected to first choice line and the output of the first gate in its input；
3rd Muller C-element, is connected to the second selection line and second clock line in its input；
4th Muller C-element, is connected to the second selection line and the output of the second gate in its input；
First delay cell, is connected to the first clock line and the output of the second Muller C-element in its input；
Second delay cell, is connected to output and the second clock line of the 4th Muller C-element in its input；
First AND-gate, is connected to the first clock line, the output of the first Muller C-element and the in its input
The output of one delay cell；
Second AND-gate, is connected to the output of the second delay cell, the 3rd Muller C-element in its input
Output and second clock line；And
OR door, is connected to the output of the first AND-gate and the output of the second AND-gate in its input, and
Its output provides output clock signal, and wherein, first choice signal is defeated for being chosen as the first clock signal
Go out clock signal, and the second selection signal is used for second clock signal behavior being output clock signal.
2. clock switch circuit according to claim 1, wherein：
First gate is AND-gate, is connected to first choice line in an input, receives in another input
The inverse value of the output of OR door, and
Second gate is AND-gate, is connected to the second selection line in an input, receives in another input
The inverse value of the output of OR door.
3. clock switch circuit according to claim 2, also includes：
3rd clock line, provides the 3rd clock signal；
3rd selection line, provides the 3rd selection signal, for being chosen as exporting clock letter the 3rd clock signal
Number；
5th Muller C-element, is connected to the 3rd clock line and the 3rd selection line in its input；
6th Muller C-element, is connected to the output of the 3rd selection line and the 3rd gate in its input, and the 3rd
Gate is AND-gate, is connected to the 3rd selection line in an input, and receives OR door in another input
Output inverse value；
3rd delay cell, is connected to the output of the 3rd clock line and the 6th Muller C-element in its input；And
3rd AND-gate, is connected to the 3rd clock line, the output of the 5th Muller C-element and the in its input
The output of three delay cells, the output of the 3rd AND-gate is connected to the input of OR door.
4. clock switch circuit according to claim 1, wherein, the first delay cell includes：
First delay Muller C-element, is connected to output and first clock of the second Muller C-element in its input
Line, and
First delay phase inverter, is connected to the first clock line in its input, and
Second delay cell includes：
Second delay Muller C-element, is connected to output and the second clock of the 4th Muller C-element in its input
Line, and
Second delay phase inverter, is connected to second clock line in its input.
5. clock switch circuit according to claim 4, wherein：
First delay cell also includes the 3rd delay Muller C-element, in the described 3rd delay Muller C-element
Input is connected to the output of the first delay Muller C-element and the output of the first delay phase inverter, and
Second delay cell also includes the 4th delay Muller C-element, in the described 4th delay Muller C-element
Input is connected to the output of the second delay Muller C-element and the output of the second delay phase inverter.
6. clock switch circuit according to claim 1, wherein：
First gate is NOR-gate, is connected to the second selection line and second clock line in its input, and
Second gate is NOR-gate, is connected to first choice line and the first clock line in its input.
7. clock switch circuit according to claim 1, wherein, the second selection line is connected to phase inverter
Output, described phase inverter is connected to first choice line in its input.
8. a kind of clock switch circuit, including：
Multiple clock lines, each clock lines all provide respective clock signal；
OR door, provides output clock signal；
A plurality of selection line, each selection line both corresponds to corresponding clock lines in described multiple clock lines,
And provide selection signal, for being chosen as exporting clock signal corresponding clock signal；And
Multiple clock selection modules, each clock selection module includes：
First Muller C-element, is inputted and is connected to corresponding clock line and corresponding selection line,
Second Muller C-element, is inputted the output being connected to corresponding selection line and the first AND-gate,
One input of the first AND-gate is connected to corresponding selection line, receives the output of OR door in another input
Inverse value,
Delay cell, is inputted the output being connected to corresponding clock line and the second Muller C-element, and
Second AND-gate, be inputted be connected to corresponding clock line, the output of the first Muller C-element and
The output of delay cell, the output of the second AND-gate is connected to the input of OR door.
9. clock switch circuit according to claim 8, wherein, each delay cell includes：
First delay Muller C-element, its input be connected to the output of the second Muller C-element and corresponding when
Clock line, and
First delay phase inverter, is connected to corresponding clock line in its input.
10. clock switch circuit according to claim 9, wherein, each delay cell also includes
Second delay Muller C-element, is connected to the first delay Muller in the input of the described second delay Muller C-element
The output of C-element and the output of the first delay phase inverter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510659344.8A CN106470024A (en) | 2015-08-18 | 2015-08-18 | Glitch-free clock switch circuit using Muller C-element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510659344.8A CN106470024A (en) | 2015-08-18 | 2015-08-18 | Glitch-free clock switch circuit using Muller C-element |
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| CN106470024A true CN106470024A (en) | 2017-03-01 |
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| CN201510659344.8A Withdrawn CN106470024A (en) | 2015-08-18 | 2015-08-18 | Glitch-free clock switch circuit using Muller C-element |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ES2684846A1 (en) * | 2017-03-31 | 2018-10-04 | Universidad Carlos Iii De Madrid | Device and procedure for the univocal identification of an integrated circuit (Machine-translation by Google Translate, not legally binding) |
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| US5646554A (en) * | 1995-03-16 | 1997-07-08 | Research Foundation Of State University Of New York | Method and apparatus for selective clocking using a Muller-C element |
| JP2003150372A (en) * | 2001-11-12 | 2003-05-23 | Advanced Telecommunication Research Institute International | Random number generating circuit |
| CN101741372A (en) * | 2008-11-11 | 2010-06-16 | 株式会社瑞萨科技 | Semiconductor integrated circuit and control method for clock signal synchronization |
| CN103684363A (en) * | 2012-09-12 | 2014-03-26 | 辉达公司 | Timing calibration for on-chip interconnec |
| US20140320170A1 (en) * | 2013-04-30 | 2014-10-30 | Goverment Of The United States As Represented By Te Secretary Of The Air Force | Glitch free clock multiplexer |
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Patent Citations (5)
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|---|---|---|---|---|
| US5646554A (en) * | 1995-03-16 | 1997-07-08 | Research Foundation Of State University Of New York | Method and apparatus for selective clocking using a Muller-C element |
| JP2003150372A (en) * | 2001-11-12 | 2003-05-23 | Advanced Telecommunication Research Institute International | Random number generating circuit |
| CN101741372A (en) * | 2008-11-11 | 2010-06-16 | 株式会社瑞萨科技 | Semiconductor integrated circuit and control method for clock signal synchronization |
| CN103684363A (en) * | 2012-09-12 | 2014-03-26 | 辉达公司 | Timing calibration for on-chip interconnec |
| US20140320170A1 (en) * | 2013-04-30 | 2014-10-30 | Goverment Of The United States As Represented By Te Secretary Of The Air Force | Glitch free clock multiplexer |
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| THOMAS POLZER 等: "Metastability Characterization for Muller C-Elements", 《2013 23RD INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS)》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ES2684846A1 (en) * | 2017-03-31 | 2018-10-04 | Universidad Carlos Iii De Madrid | Device and procedure for the univocal identification of an integrated circuit (Machine-translation by Google Translate, not legally binding) |
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