CN106383338B - A kind of Multichannel radar signal pickup assembly based on digital channelizing - Google Patents
A kind of Multichannel radar signal pickup assembly based on digital channelizing Download PDFInfo
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- CN106383338B CN106383338B CN201611009563.2A CN201611009563A CN106383338B CN 106383338 B CN106383338 B CN 106383338B CN 201611009563 A CN201611009563 A CN 201611009563A CN 106383338 B CN106383338 B CN 106383338B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/28—Details of pulse systems
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Abstract
The invention discloses a kind of Multichannel radar signal pickup assembly based on digital channelizing, is related to radar signal acquisition technique field.It compensates for the deficiency that existing radar signal acquisition device does not have multi-channel synchronous digital channelizing acquisition function.The Multichannel radar signal pickup assembly based on digital channelizing technology, including the first FPGA, 2nd FPGA, 3rd FPGA, No. 9 analog-digital converters and multipath clock generator, No. 9 analog-digital converters are evenly distributed in the first FPGA, the input terminal of 2nd FPGA and the 3rd FPGA, first FPGA, design has 9 articles of channelizing acquisition channels in total on 2nd FPGA and the 3rd FPGA, first FPGA is main process task chip, 2nd FPGA and the 3rd FPGA is from processing chip, first FPGA provides synchronous acquisition signal by differential bus and GPIO signal for the 2nd FPGA and the 3rd FPGA, the synchronous digital channelizing acquisition of the radar intermediate frequency signal of 9 road 800MHz instant bandwidths can be achieved, the result of channelizing processing is gone here and there by high speed Row bus output, is handled convenient for follow-up signal.
Description
Technical field
The present invention relates to radar signal acquisition technique fields, and in particular to a kind of Multichannel radar based on digital channelizing
Signal pickup assembly.
Background technique
The reception and processing of radar ELECTROMAGNETIC RADIATION SIGNATURE are the key technology and research in electronic countermeasure and passive guidance field
Hot spot, with the high speed development of modern electronic technology, new system radar is continuously emerged, and radar is to improve itself working performance and do
Antagonism is disturbed, generally takes the multinomial measures such as extension working frequency, frequency agility, frequency diversity, intra-pulse modulation, and match
Standby radar decoy.For the variation for adapting to Radar Technology, passive guidance system needs higher requirement, to realize to multi-section radar
The tracking of signal and identification bait radar, many passive guidance systems use the Estimation of Spatial Spectrum based on array signal processing
Technology, for the realization for cooperating array df technology, passive guidance system needs to have the synchronous acquisition function of Multichannel radar signal
Energy.Radar signal acquisition device common at present, generally existing instant bandwidth is small, number of channels is few, inter-channel synchronization ability is poor
The disadvantages of, the Measure direction performance of passive guidance system is affected to a certain extent.
It is complete using multipath high-speed A/D device typically based on the multichannel wideband digital receiver of digital channelizing technology
At the digitlization of radiofrequency signal, the channelizing processing of multi-path digital signal is completed in FPGA, then carries out Radar Signal Recognition
And characteristic parameter extraction, various information required for obtaining, and these information are stored, it is transmitted by HSSI High-Speed Serial Interface
To rear class signal processor, the relevant information of target radar is obtained by operation.As shown in Figure 1, patent name is a kind of typical case
The Chinese patent (patent No.: CN204215243U) of radar signal acquisition device disclose a kind of radar signal acquisition device,
Radar signal is converted to intermediate frequency letter by microwave down conversion unit, intermediate-freuqncy signal receiving unit by the radar signal acquisition device
Number, digital channelizing processing then is carried out to radar signal using A/D and FPGA, finally passes processing result by PCIE bus
It is defeated to be processed and displayed to computer.
Exist in prior art following insufficient:
(1) the existing radar signal acquisition device based on digital channelizing technology, does not have multichannel synchronousing collection mostly
Function is unable to satisfy the applications such as Space ball.
(2) the data transmission based on PCIE bus, real-time is poor, is unable to satisfy the real-time processing of intensive radar pulse signal
Demand.
Summary of the invention
The purpose of the present invention is in view of the above deficiencies, proposing, an instant bandwidth is big, receiving channel is more, inter-channel synchronization is smart
A kind of Multichannel radar signal pickup assembly based on digital channelizing that degree is high and data processing real-time is good.
The present invention specifically adopts the following technical scheme that
A kind of Multichannel radar signal pickup assembly based on digital channelizing, including the first FPGA, the 2nd FPGA, third
FPGA, No. 9 analog-digital converters and multipath clock generator, No. 9 analog-digital converters be evenly distributed in the first FPGA, the 2nd FPGA and
The input terminal of 3rd FPGA, design has 9 articles of channelizing acquisition channels in total on the first FPGA, the 2nd FPGA and the 3rd FPGA, the
One FPGA is main process task chip, and the 2nd FPGA and the 3rd FPGA are from processing chip, and the first FPGA passes through differential bus and GPIO
Signal is that the 2nd FPGA and the 3rd FPGA provide synchronous acquisition signal.
It preferably, include 1 main acquisition channel and 8 in 9 acquisition channels from acquisition channel, the first FPGA, the
It is designed with 3 articles of acquisition channels in two FPGA and the 3rd FPGA, is connected separately on the first FPGA, the 2nd FPGA and the 3rd FPGA
No. 3 analog-digital converters.
Preferably, the main acquisition channel is located in the first FPGA.
Preferably, the first FPGA, the 2nd FPGA and the 3rd FPGA carry out digital channelizing processing to input signal, the
One FPGA further includes the configuration to system clock, is detected to the channelizing of main acquisition channel and to provide synchronous letter from acquisition channel
Number.
Preferably, 9 road analog if signals input the device, and analog-digital converter is sent into after signal conditioning circuit and is converted to
Digital medium-frequency signal, 9 railway digital intermediate-freuqncy signals complete 64 channelizings processing parallel in FPGA, 1 road signal are selected to enter master
Acquisition channel, and Channel Detection is carried out to its channelizing treated baseband signal, extract pulsewidth, the arrival time of radar pulse
And carrier parameter, remaining 8 road signal are respectively enterd from acquisition channel, main acquisition channel provides letter from acquisition channel to remaining 8
Road synchronization signal, 9 tunnels effective radar pulse channelized detection after synchronous for realizing the channelizing of 9 acquisition channels
Signal is respectively stored in the FIFO of the first FPGA, the 2nd FPGA and the 3rd FPGA, starts to deposit when detecting rising edge of a pulse
Storage detects and stops storage after pulse falling edge or memory space are full, then by the output of pulse signal that this is acquired, hereafter
Continue the detection of next radar pulse.
Preferably, the sampling clock of the analog-digital converter is generated by phase-locked loop, and sampling clock is after clock buffer
It is divided into 5 road differential clock signals, 5 road differential clock signals are respectively after delayer as the sampling clock of analog-digital converter.
Preferably, the main acquisition channel is chosen to be detected, it is defeated after the main channelized processing of acquisition channel intermediate-freuqncy signal
32 sub-channels out carry out pulse detection to 32 sub-channels, when detecting effective impulse signal rising edge in certain sub-channels
When, the channel number where pulse, pulse storage FIFO number parameter are sent to other 8 from acquisition channel, and passed through
GPIO signal provide impulsive synchronization store signal, 8 from acquisition channel according to impulsive synchronization information, effective impulse data are stored in
Data buffer storage provides effective FIFO number and synchronous storage end signal to from acquisition channel when detecting end-of-pulsing, and
The output of 9 acquisition channel channelized datas of synchronous averaging is transmitted.
Preferably, the output transmission of the data uses high-speed serial bus, is based on the first FPGA, the 2nd FPGA and third
GTX high-speed transceiver in FPGA carries out data transmission, each the first FPGA, the 2nd FPGA and the 3rd FPGA use 8
GTX transmitter sends data.
The invention has the advantages that: the multichannel number of radar signal is realized based on analog-digital converter and FPGA array
Word Digital Channelized Receiving, instantaneous reception bandwidth 800MHz, each Digital Channelized Receiving channel are realized stringent synchronization, are believed through multi-channel digital
Roadization receives treated radar baseband signal and is transferred to follow-up signal processing unit by HSSI High-Speed Serial Interface, guarantees subsequent letter
Number processing and direction finding synchronisation requirement；The present apparatus is with instant bandwidth is big, receiving channel is more, inter-channel synchronization precision is high, data
The features such as processing real-time is good is very suitable for the application to the passive array df of broadband radar target.
Detailed description of the invention
Fig. 1 is a kind of broadband signal collector structural schematic diagram based on digital channelizing；
Fig. 2 is the Multichannel radar signal pickup assembly structural schematic diagram based on digital channelizing；
Fig. 3 is A/D sampling clock synchronization scheme schematic diagram；
Fig. 4 is the synchronous schematic diagram of channelizing.
Specific embodiment
A specific embodiment of the invention is described further in the following with reference to the drawings and specific embodiments:
FPGA:(Field-Programmable Gate Array), i.e. field programmable gate array.
FIFO:(First Input First Output), First Input First Output.
GPIO:(General-Purpose Input/Output Ports), general purpose I/O port.
A/D:(Analog-to-Digital Converter), analog-digital converter.
As shown in Fig. 2, a kind of Multichannel radar signal pickup assembly based on digital channelizing, including the first FPGA,
Two FPGA, the 3rd FPGA, No. 9 analog-digital converters (A/D) and multipath clock generator, No. 9 analog-digital converters are evenly distributed in
The input terminal of one FPGA, the 2nd FPGA and the 3rd FPGA, design has 9 articles in total on the first FPGA, the 2nd FPGA and the 3rd FPGA
Channelizing acquisition channel, the first FPGA are main process task chip, and the 2nd FPGA and the 3rd FPGA are from processing chip, and the first FPGA is logical
It crosses differential bus and GPIO signal is that the 2nd FPGA and the 3rd FPGA provide synchronous acquisition signal.
It include 1 main acquisition channel and 8 in 9 acquisition channels from acquisition channel, the first FPGA, the 2nd FPGA and third
3 acquisition channels are designed in FPGA, wherein main acquisition channel is located in the first FPGA, the first FPGA, the 2nd FPGA and
No. 3 analog-digital converters are connected separately on three FPGA.
First FPGA, the 2nd FPGA and the 3rd FPGA carry out digital channelizing processing to input signal, and the first FPGA is also wrapped
The configuration to system clock is included, the channelizing of main acquisition channel is detected and to provide synchronization signal from acquisition channel.
9 road analog if signals input the device, and analog-digital converter is sent into after signal conditioning circuit and is converted in number
Frequency signal, 9 railway digital intermediate-freuqncy signals complete 64 channelizings processing parallel in FPGA, select 1 road signal to enter main acquisition logical
Road, and Channel Detection is carried out to its channelizing treated baseband signal, extract pulsewidth, arrival time and the carrier frequency of radar pulse
Parameter, remaining 8 road signal are respectively enterd from acquisition channel, and main acquisition channel is same from acquisition channel offer channelizing to remaining 8
Signal is walked, 9 tunnels effective radar pulse signal channelized detection after synchronous for realizing the channelizing of 9 acquisition channels, point
It is not stored in the FIFO of the first FPGA, the 2nd FPGA and the 3rd FPGA, starts to store when detecting rising edge of a pulse, detect
Stop storage after pulse falling edge or memory space are full, then exports this pulse signal acquired by GTX interface, this
Continue the detection of next radar pulse afterwards.
As shown in figure 3, the sampling clock of analog-digital converter is generated by phase-locked loop, sampling clock divides after clock buffer
For 5 road differential clock signals, 5 road differential clock signals are respectively after delayer as the sampling clock of analog-digital converter.It should
The amount of delay of delayer is adjustable, maximum delay time 1500ps, resolution ratio 5ps, by the way that amount of delay is arranged, it is ensured that adopt
Sample clock is alignment in the sampling clock input terminal of every A/D, this is also the synchronous premise of data.Data between 5 A/D are same
Step scheme is as shown in Fig. 2, wherein select a piece of A/D to work in Master mode, remaining 4 work in Slave mode, and work exists
For the reference clock RCOUT of the A/D output of master mode after clock distributor, the reference clock for being supplied to remaining 4 A/D is defeated
Enter RCLK, realizes the synchronization of 5 A/D output datas.Using the clock synchronizing method, it is ensured that 9 road A/D sampling clocks it is same
Error is walked within 20ps.
As shown in figure 4, a total of 9 acquisition channels of radar signal acquisition device of the present invention, if 9 acquisition channels
Channel Detection and radar pulse characteristic parameter extraction are all carried out after channelized processing, then it is easy to appear each Air conduct measurement results
Inconsistent situation is chosen main acquisition channel and is detected to avoid radar pulse caused by the problem from acquiring mistake, main acquisition
32 sub-channels are exported after the channelized processing of channel intermediate-freuqncy signal, pulse detection are carried out to 32 sub-channels, when in certain height
When Channel Detection is to effective impulse signal rising edge, the channel number where pulse, pulse storage FIFO number parameter are sent
To other 8 from acquisition channel, and impulsive synchronization being provided by GPIO signal and stores signal, 8 from acquisition channel according to pulse
Effective impulse data are stored in data buffer storage by synchronizing information, effective to providing from acquisition channel when detecting end-of-pulsing
FIFO number with synchronous storage end signal, and 9 acquisition channel channelized datas of synchronous averaging output transmit.
The output transmission of data uses high-speed serial bus, based on the GTX in the first FPGA, the 2nd FPGA and the 3rd FPGA
High-speed transceiver carries out data transmission, and the GTX interface maximum transmission rate in typical Xilinx company V7 Series FPGA is reachable
12.5Gbps, the Aurora IP kernel embedded using FPGA, is encoded, single channel GTX valid data transmission bandwidth is most using 8B10B
High reachable 10Gbps.In view of the overheads such as data-frame sync and the stability of system, the first FPGA, the 2nd FPGA and
Three FPGA use 8 GTX transmitters to send data, and the transmission bandwidth of single GTX is 6.25Gbps, and 8 channel GTX transmitters can
There is provided effective transmission bandwidth of 40Gbps, it is ensured that repetition period 5us, duty ratio are not more than the real-time biography of 30% radar pulse
It is defeated.
Certainly, the above description is not a limitation of the present invention, and the present invention is also not limited to the example above, this technology neck
The variations, modifications, additions or substitutions that the technical staff in domain is made within the essential scope of the present invention also should belong to of the invention
Protection scope.
Claims (4)
1. a kind of Multichannel radar signal pickup assembly based on digital channelizing, which is characterized in that including the first FPGA, second
FPGA, the 3rd FPGA, No. 9 analog-digital converters and multipath clock generator, No. 9 analog-digital converters be evenly distributed in the first FPGA,
The input terminal of 2nd FPGA and the 3rd FPGA, design has 9 articles of channelizings to adopt in total on the first FPGA, the 2nd FPGA and the 3rd FPGA
Collect channel, the first FPGA is main process task chip, and the 2nd FPGA and the 3rd FPGA are from processing chip, and the first FPGA is total by difference
Line and GPIO signal are that the 2nd FPGA and the 3rd FPGA provide synchronous acquisition signal；
It include 1 main acquisition channel and 8 in 9 acquisition channels from acquisition channel, the first FPGA, the 2nd FPGA and third
It is designed with 3 acquisition channels in FPGA, is connected separately with 3 tunnel analog-to-digital conversions on the first FPGA, the 2nd FPGA and the 3rd FPGA
Device, the main acquisition channel are located in the first FPGA；
First FPGA, the 2nd FPGA and the 3rd FPGA carry out digital channelizing processing to input signal, and the first FPGA is also wrapped
The configuration to system clock is included, the channelizing of main acquisition channel is detected and to provide synchronization signal from acquisition channel；
9 road analog if signals input the device, and analog-digital converter is sent into after signal conditioning circuit and is converted to digital intermediate frequency letter
Number, 9 railway digital intermediate-freuqncy signals complete 64 channelizings processing parallel in FPGA, and select 1 road signal to enter main acquisition channel, and
Channel Detection is carried out to its channelizing treated baseband signal, extracts pulsewidth, arrival time and the carrier parameter of radar pulse,
Remaining 8 road signal is respectively enterd from acquisition channel, and main acquisition channel provides channelizing synchronous letter for remaining 8 from acquisition channel
Number, synchronous for realizing the channelizing of 9 acquisition channels, the effective radar pulse signal in 9 tunnels after channelized detection is deposited respectively
In the FIFO of mono- FPGA of Chu, the 2nd FPGA and the 3rd FPGA, starts to store when detecting rising edge of a pulse, detect pulse
Stop storage after failing edge or memory space are full, then by the output of pulse signal that this is acquired, hereafter continues next thunder
Up to the detection of pulse.
2. a kind of Multichannel radar signal pickup assembly based on digital channelizing as described in claim 1, which is characterized in that
The sampling clock of the analog-digital converter is generated by phase-locked loop, and sampling clock is divided into 5 road differential clocks after clock buffer
Signal, 5 road differential clock signals are respectively after delayer as the sampling clock of analog-digital converter.
3. a kind of Multichannel radar signal pickup assembly based on digital channelizing as described in claim 1, which is characterized in that
It chooses the main acquisition channel to be detected, exports 32 sub-channels after the main channelized processing of acquisition channel intermediate-freuqncy signal, it is right
32 sub-channels carry out pulse detection will be where pulse when certain sub-channels detects effective impulse signal rising edge
Channel number, pulse storage FIFO number parameter are sent to other 8 from acquisition channel, and same by the offer pulse of GPIO signal
Step storage signal, 8 from acquisition channel according to impulsive synchronization information, effective impulse data are stored in data buffer storage, when detecting
When end-of-pulsing, effective FIFO number and synchronous storage end signal are provided to from acquisition channel, and synchronous averaging 9 acquisitions are logical
The output of road channelized data is transmitted.
4. a kind of Multichannel radar signal pickup assembly based on digital channelizing as claimed in claim 3, which is characterized in that
The output transmission of data uses high-speed serial bus, is received and dispatched based on the GTX high speed in the first FPGA, the 2nd FPGA and the 3rd FPGA
Device carries out data transmission, each the first FPGA, the 2nd FPGA and the 3rd FPGA use 8 GTX transmitters to send data.
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| CN107942291A (en) * | 2017-10-12 | 2018-04-20 | 西安天和防务技术股份有限公司 | Intermediate frequency digital receiver, IF signal processing method |
| CN109547091B (en) * | 2018-11-27 | 2020-06-30 | 上海航天电子通讯设备研究所 | Processing system for multi-channel detection based on VDE |
| CN110196416A (en) * | 2019-05-30 | 2019-09-03 | 电子科技大学 | A kind of radar multi-channel data acquisition and real-time processing device |
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| CN112162126B (en) * | 2020-09-16 | 2022-11-18 | 普源精电科技股份有限公司 | Multi-channel pulse generator, signal generation method, multi-channel synchronization system and method |
| CN112558522A (en) * | 2020-12-11 | 2021-03-26 | 深圳大学 | Electrical signal acquisition system of multichannel friction nanometer generator |
| CN112737626B (en) * | 2020-12-18 | 2022-07-01 | 中国电子科技集团公司第五十四研究所 | Broadband parallel receiving and processing device based on VPX bus |
| CN113311394A (en) * | 2021-05-18 | 2021-08-27 | 中国船舶重工集团公司第七二三研究所 | Ultra-wideband PDW real-time fusion method |
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