CN106375658B - A kind of very high-precision image processing VLSI verification method - Google Patents
A kind of very high-precision image processing VLSI verification method Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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Abstract
A kind of general very high-precision image processing VLSI verification method, parameter configuration is carried out according to Current camera type first, it obtains camera source images and is converted to the artwork data and standard solution data of TEXTIO format, then along the data/address bus or data signal line that artwork data is successively sent to camera by effective edge of pixel clock in multiple duplicate row effective periods, very high-precision image processing and reading are carried out to the data on data/address bus or data signal line, obtain the very high-precision image processing result data of TEXTIO format, finally processing result data is compared with standard solution data, obtain the position of error pixel, gray value difference, and then it is adjusted image and verification result after threshold value distribution.
Description
Technical field
The present invention relates to technical field of image processing, especially a kind of very high-precision image processing VLSI verification method.
Background technique
Traditional very high-precision imaging super large-scale integration (very large scale integration) VLSI
The image data amount that product is related to is big, and generally 1024*1024 to 2048*2048 pixel size, the Image Processing Simulation time is long,
The functional simulation for carrying out a sub-picture takes around 7 hours time, and time stimulatiom takes around 6 days or so time, and not
Different with camera standard, there are data rounding error, traditional test envelopes with theoretical calculation for VLSI Project Realization in addition
TESTBENCH emulation assertion statement customization coding and the verification mode of artificial interpretation will expend a large amount of manpowers and time cost, main
There are problems to have following aspects:
First, very high-precision imager class VLSI product type type and quantity constantly rise at present, and different task uses
Different type camera will be directed to different demands and the individually designed TESTBENCH of different images standard demand, simulation code every time
Reusability is low, simulating, verifying inefficiency.Found through analysis, although different cameral standard is different, substantially all by row field synchronization,
The baseband signals such as pixel clock, data are constituted, and difference is only deposited in data bit width, row field signal significant level height, image size
In difference, therefore parameter configuration can be carried out for the application demand of different systems camera, directly generate the simulation of different systems
The code emulation file of imager and image acquisition device, makes it have design versatility, improve simulation document code efficiency and
Encode correctness.
Second, the source images that algorithm engineering teacher provides are different according to type of imager different systems, and according to individual
Coding habit is different to deposit bitmap-format difference, and source images meet VHDL-TEXTIO format standard after needing to carry out form collator,
The use of TESTBENCH emulation platform could be added, therefore the source images of different-format can be subjected to image according to configuration data
Format conversion generates the data file addition TESTBENCH emulation platform for meeting VHDL-TEXTIO standard, flat with simulating, verifying
The analog imaging device simulation code that platform generates is used in combination, and completes the function of analog imaging device.
Third, image processing algorithm use MATLAB and VC to realize more in algorithm principle simulation stage, generally use 64bit
Bit wide double-precision floating point format carries out operation, and practical VLSI realization is limited by resource, is only capable of using not higher than 32bit bit wide
Fixed-point calculation is realized.The influence of the data rounding error will make VLSI Project Realization result can not be complete with algorithm simulating standard solution
Complete consistent, so the error to algorithm simulating standard solution and VLSI Project Realization result is needed to measure, whether assessment design
Meet mission requirements, result images, which will directly be carried out boolean's judgement with standard solution, by TESTBENCH assertion statement frequently to report
Mistake can not intuitively reflect the correctness of image procossing.
4th, HDL code emulation cannot intuitively obtain image, and display is only able to display 8bit bit wide RGB figure at present
Picture, and very high-precision camera product is generally 12bit or 14bit bit wide, directly cannot observe imaging effect by display.
Summary of the invention
Technical problem solved by the present invention is having overcome the deficiencies of the prior art and provide a kind of very high-precision image processing
VLSI verification method.
The technical solution of the invention is as follows: a kind of very high-precision image processing VLSI verification method includes the following steps:
(1) the current corresponding camera type of image for carrying out very high-precision image processing is obtained, if camera type is CCD
Mode then obtains row signal HEN significant level, the field signal LEN significant level, pixel clock, single-frame images of CCD mode camera
Corresponding line number H, single-frame images correspond to columns L, row latent period respective pixel clock cycle number FOT, every pixel and occupy byte
Number c obtains APS mode camera pixel clock, single-frame images corresponds to line number H, single frames figure if camera type is APS mode
As corresponding columns L, every pixel occupy byte number c, wherein H, L, FOT, c are positive integer；
(2) image shot by camera and as source images is obtained, source image data is read by byte and is converted to binary system
Data format, every L*c byte data are once entered a new line, finally with the storage of TXT text formatting, until source image data quilt time
It goes through, obtains TEXTIO format artwork data, be transferred to step (3)；Standard solution figure is obtained after carrying out image simulation to source images simultaneously
Picture is read by byte and is converted to binary data format to standard solution image, and every L*c byte data is once entered a new line,
Finally TEXTIO format standard solution data are obtained, step is transferred to until standard solution image is traversed with the storage of TXT text formatting
(5)；
(3) if camera type is CCD mode, when the bat figure enabling signal that very high-precision image processing VLSI is generated rises
Along when arriving, setting field signal LEN waits end line after FOT*PCLK_T pixel clock length to disappear effectively and into row latent period
The hidden phase, at the same by row signal HEN be set to effectively, control row signal HEN continue L*PCLK_T pixel clock length postposition be it is invalid,
Complete a row effective period, after repeating H row effective period, be arranged field signal LEN be it is invalid, in H row effective period
TEXTIO format artwork data is successively sent to the data/address bus of CCD mode camera and is transferred to step by effective edge of pixel clock
(4), wherein PCLK_T is pixel clock length；The figure enabling signal of clapping is the high pulsewidth that width is greater than 2 pixel clocks
Signal, when for rising edge, the image data transmission that representative is sent to CCD mode camera starts；
If camera type is APS mode, controls very high-precision image processing VLSI and generate frame request signal F_Q letter
Number, when frame request signal F_Q signal rising edge arrives, setting field marker V_L waits FOT* effectively and into row latent period
Terminate blanking interval after PCLK_T pixel clock length, while line identifier position V_H being set to effectively, continues L*PCLK_T clock length
Postposition line identifier position V_H be it is invalid, complete a row effective period, after repeating H row effective period, setting field marker V_L
To be invalid, pixel clock is effectively sent after TEXTIO format artwork data is carried out parallel-serial conversion in H row effective period
To APS mode camera data signal wire, and it is transferred to step (4)；
(4) data on the data/address bus to CCD mode camera or APS mode camera data signal wire carry out very high-precision
Image procossing is spent, then data-signal, every L*c byte of reading are changed after the rising edge of pixel clock reads acquisition process
Row storage, is finally stored as txt format, obtains the very high-precision image processing result data of TEXTIO format and be transferred to step 5；
(5) the TEXTIO format that will be generated in the very high-precision image processing result data of TEXTIO format and step (2)
Standard solution data are compared, the position of output error pixel, gray value difference, by the position of error pixel, gray value difference
Object as a result, and it is transferred to step (6)；The error pixel is in very high-precision image processing result data and standard solution
During comparing, the unequal pixel of gray value；
(6) data bit width of pixel each in result images is denoted as Mbit, sets up 2MA histogram register, and respectively
It is denoted as label 0, label 1, label 2 ..., label (2M- 1) number of pixels that gray value difference in result object is Z, is stored in mark
Number be Z histogram register, wherein Z ∈ [0,1,2 ..., (2M-1)]；
(7) histogram register is pressed into the sequence of label from small to large, then since 0 histogram register of label successively
Data in histogram register are added up, when sum of all pixels ratio is 0.1% in accumulated value and result images, record is last
Cumulative histogram register label, and it is denoted as Dmin, when sum of all pixels ratio is 99.9% in accumulated value and result images, note
The finally cumulative histogram register label of record, and it is denoted as Dmax；
(8) position is that the gray value g (x, y) of the pixel of (x, y) is in the image after adjustment threshold value distribution is calculated
Wherein, f (x, y) is that location of pixels is (x, y) in the very high-precision image processing result data of TEXTIO format
The gray value of pixel；
And then it is adjusted the image after threshold value distribution, the maximum value of gray value difference in result data is chosen as error
Then maximum value, the minimum value of gray value difference choose the singular point of gray value difference in result data as error minimum value
And judged, it is if max value of error, error minimum value, singular point gray value difference are in [- 2,2], then current very high-precision
Degree image procossing VLSI is verified, and is otherwise verified and is not passed through.
Described is that C or MATLAB is emulated to the method for obtaining standard solution image after source images progress image simulation.
The advantages of the present invention over the prior art are that:
(1) verification method of the present invention can carry out parameter configuration according to different type standard image mission requirements, and then complete
The verifying of the image procossing VLSI processing result of pairs of different type standard image has preferable logical compared with prior art
With property and applied value；
(2) verification method of the present invention compared with prior art, can not only realize source images and image procossing VLSI processing
The quick comparison of result images, can also maximum value to pixel data precision, minimum value, singular point position count, it is real
Now to image procossing VLSI, treated that picture quality is assessed.
Detailed description of the invention
Fig. 1 is the present invention very high-precision image processing VLSI verification method flow diagram；
Fig. 2 is the present invention very high-precision image processing VLSI verification method organizational structure schematic diagram；
Fig. 3 is control channel signal frame format structure schematic diagram in the present invention.
Specific embodiment
The present invention proposes a kind of very high-precision image processing VLSI verification method, mainly real using MATLAB and HDL language
It is existing, it is as shown in Figure 1 the present invention very high-precision image processing VLSI verification method flow diagram, is illustrated in figure 2 the present invention
Very high-precision image processing VLSI verification method organizational structure schematic diagram, the method for the present invention concrete principle process and realization framework packet
It includes:
(1) parameter configuration: camera type (including CCD mode camera, APS mode camera) is first determined whether and according to camera-type
Type completes video standard parameter configuration, and for CCD mode camera, image parameter includes the significant level of row signal HEN, field signal
Significant level, effective edge of CCD mode camera pixel clock PCLK, the single frames CCD mode camera image of LEN corresponds to line number H, list
Frame CCD mode camera image corresponds to columns L, CCD mode camera row latent period respective pixel clock cycle number FOT, data simultaneously
String switch endpoint mode (including high-order preceding big terminal, the preceding small terminal of low level), every pixel occupy byte number c.It is right
In APS mode camera, image parameter includes the control channel signal significant level, data channel number N, instruction of APS mode camera
Practicing control word, (APS type camera parameter detects the instruction for completing the search of image data acquiring window in control channel
After sequence of practising handwriting, image data can correctly be acquired by indicating current image data acquiring window), single-frame images correspond to line number H,
Single-frame images corresponds to columns L, control channel signal frame format, the position row synchronization character V_H, the position field synchronization word V_L, data and goes here and there
Switch endpoint mode (including high-order preceding big terminal, the preceding small terminal of low level), every pixel occupy byte number c, every picture
Element occupies bit several k.Parameter is determining and after configuring, and is transferred to step (2), (3), (4), wherein control channel signal is
One of APS mode camera three classes interface signal, three classes interface signal is respectively pixel clock signal, data-signal and control channel
Signal, control channel signal are list bit signal wire, and continuous 10bit is a complete transmission period, and it is same that 10bit respectively corresponds row
Word V_H, field synchronization word V_L and 8 reserved words are walked, therefore control channel signal frame format structure is as shown in Figure 3.
(2) TEXTIO of image data is formatted: obtain image shot by camera and as source images, while by source images into
The notional result image that row C or MATLAB algorithm level emulates presses byte as standard solution image, while to source image data
It reads, and is converted to binary data format, every L*c byte data is once entered a new line, and is finally deposited with TXT text formatting
Storage obtains TEXTIO format artwork data, is transferred to step (3) until all source image datas are traversed；To standard solution picture number
It is read according to by byte, and is converted to binary data format, every L*c byte data is once entered a new line, finally with TXT text
Format storage obtains TEXTIO format standard solution data, is transferred to step (5) until all standard solution image datas are traversed.
(3) multi-mode analog imaging device Code Design method: PCLK_T is set as a pixel of camera in the method for the present invention
Clock cycle length, if camera type is CCD mode, when very high-precision image processing VLSI is sent to multi-mode analog imaging
When the rising edge of the bat figure enabling signal of device arrives, setting field signal LEN is effective, while entering row latent period, waits FOT picture
After plain clock, i.e., row signal HEN is set to effectively after FOT*PCLK_T clock length, row signal HEN continues L*PCLK_T clock
Length postposition be it is invalid, be again introduced into row latent period, in cycles, keep two effective rows between interval be FOT*PCLK_T
Clock.After undergoing H (H is positive integer) a row effective period, setting field signal LEN is invalid.So, it is ensured that when row signal
When effective simultaneously with field signal, data effective time is exactly H*L*PCLK_T clock, and the method for the present invention has pixel clock
Edge is imitated, the byte data stored in TEXTIO format artwork data is once sent to the data/address bus of CCD mode camera simultaneously
It is transferred to step (4), wherein bat figure enabling signal is a high pulse width signal, and width is greater than 2 pixel clocks, when detecting it
When rising edge, indicate that a frame image transmitting formally starts, row refers to the transmission of a line image data (containing blanking interval) institute effective period
The pixel period number needed.
If camera type is APS mode, camera interface has pixel clock PCLK all the way, all the way control channel signal
(single bit), N circuit-switched data signal (per being all the way single bit).The configuration mode of APS mode camera default conditions is training mode,
Under APS mode camera training mode, in each hopping edge of pixel clock PCLK, cycle through and go here and there conversion after single bit instruction
Practice in control word to the control channel signal wire of APS mode camera.When very high-precision image processing VLSI is sent to multi-mode mould
After the frame request signal F_Q signal rising edge of quasi- imager arrives, APS mode camera enters blit mode from configuration mode, control
Channel signal processed according to control channel frame format, cycle through and go here and there conversion after single bit row synchronization character V_H or field synchronization word
(row synchronization character V_H is 1 to V_L and field synchronization word V_L is that the corresponding 10bit data of the current 10bit control channel signal of 1 mark are
Valid data；Row synchronization character V_H is 0 and field synchronization word V_L is the corresponding 10bit number of the current 10bit control channel signal of 1 mark
According to for invalid row latent period data；Row synchronization character V_H is 0, and field synchronization word V_L is the current 10bit control channel letter of 0 mark
Number corresponding 10bit data are invalid data) on APS mode camera control channel signal line.
By taking k=8bit bit wide row field synchronization word as an example, effective information is only that line identifier position V_H (is located in row field synchronization word
First bit) and field marker V_L (be located at the 2nd bit), remaining reserved bit fills out 0, PCLK_T as the corresponding picture of a pixel
Plain clock cycle length, if camera type is APS mode and current-configuration mode is blit mode, when waiting FOT pixel
Line identifier position V_H in row field synchronization word is set to effectively by Zhong Hou that is, after FOT*PCLK_T clock length, and continues L*PCLK_T
Clock length postposition be it is invalid, be again introduced into row latent period, in cycles, keep rower show position be set effective twice between interval
It is FOT*PCLK_T clock, after undergoing H row effective period, it is invalid that row field synchronization word midfield marker V_L, which is arranged,.Such as
This, it is ensured that when row signal and field signal are effective simultaneously, data effective time is exactly H*L*PCLK_T clock, n-th of APS
Mode camera data channel (setting current channel as n (0 < n < N-1)) data respectively correspond in every row (n*L/N) to (n+1) *
L/N data effectively store in TEXTIO format artwork data along will correspond to when row field mark position is effective in pixel clock
It after data press small (big) terminal parallel-serial conversion, is placed on the data signal line in n-th of APS mode camera data channel, and turns
Enter step (4).
(4) Image Acquisition Code Design: under APS mode, after the completion of training process, DUT will start image processing process, hair
It send F_Q frame request signal and enters image transfer mode, be directly entered image transfer mode under CCD mode.Image Acquisition code
By the line number H of a frame image in configuration parameter, columns L and every pixel occupy byte number c and carry out image storage, very high-precision
Pixel clock signal and data-signal after processing, store for Image Acquisition code after image procossing VLSI offer processing.It is handling
Data-signal after the rising edge reading process of pixel clock signal afterwards, every reading very high-precision image processing VLSI output data
L*c byte pixel data carry out line feed storage, and result images are stored with txt document format to local hard drive, are obtained
The very high-precision image processing result data of TEXTIO format is simultaneously transferred to step (5).
(5) module is integrated: the very high-precision that TEXTIO format standard solution data, the step (4) that step (2) is obtained generate
Image procossing VLSI output data is integrated, and the specific method is as follows:
If a) being currently configured as APS mode, the control channel signal of multi-mode analog imaging device code, pixel clock are believed
Number, data-signal be connected with very high-precision image processing VLSI code to induction signal, as very high-precision image processing VLSI
Image data motivate input.By data-signal after pixel clock signal after the very processing of high-precision image processing VLSI and processing
It is connected with the acquisition clock of Image Acquisition code with acquisition data signal line, thus to the very processing of high-precision image processing VLSI
Result data is acquired, and obtains result images, and the TEXTIO format standard skill that will be generated in result images and step (2)
According to being compared, the position of output error pixel, gray value difference, and it is transferred to step (6)；
If b) being currently configured as CCD mode, by row signal, field signal, the pixel clock of multi-mode analog imaging device code
Signal, data-signal are connected to induction signal with very high-precision image processing VLSI code, as very high-precision image processing
The image data of VLSI motivates input.By data after pixel clock signal after the very processing of high-precision image processing VLSI and processing
Signal is connected with the acquisition clock of Image Acquisition code with acquisition data signal line, thus to very high-precision image processing VLSI's
Processing result data is acquired, and obtains result images, and the TEXTIO format standard that will be generated in result images and step (2)
Solution data are compared, the position of output error pixel, gray value difference, and be transferred to step (6), wherein error pixel be than
The different pixel of centering gray value；
(6) position for the error pixel for obtaining step (5), gray value difference object as a result, to result images into
Column hisgram statistics, the method is as follows: set each pixel data bit wide of result images as M bit, then need to set up marked as 0~
(2M- 1) totally 2MThe number of pixels that gray value difference in the result object of TEXTIO format is Z is stored in mark by a histogram register
Number register for being Z, wherein [0~(2 Z ∈M- 1)], 0~(2MIt -1) is the possibility gray value difference of pixel in result object, most
Afterwards according to above 2MA histogram register as a result, carrying out gray threshold conversion as follows, conversion formula is as follows:
Wherein, DminFor adaptively determining minimum threshold, acquisition methods are as follows: by the sequence of label from small to large, from mark
Number for 0 histogram register originate, data in histogram register are added up, when accumulated value and total number of pixels accounting
When reaching 0.1%, current histogram register label D is recordedmin, as adaptively determining minimum threshold；DmaxIt is adaptive
Determining max-thresholds, acquisition methods are as follows: by the sequence of label from small to large, originated from the histogram register marked as 0,
Data in histogram register are added up, when accumulated value reaches 99.9% with total number of pixels accounting, record is current straight
Square figure register label Dmax, as adaptively determining max-thresholds.F (x, y) is at the very high precision image of TEXTIO format
The pixel value that location of pixels in result data is (x, y) is managed, g (x, y) is to adjust pixel position in 8 bit wide images after threshold value is distributed
It is set to the pixel value of (x, y), is handled by this, intuitively can observe display source images and processing result image in display,
Script invisible image is shown on display, it then can also be by report output function by by standard solution data
Make the difference and compare with processing result data, output error maximum value, minimum value and singular point position, when max value of error, error most
Small value, singular point gray value difference are within [- 2,2], and currently very high-precision image processing VLSI is verified.
The content that description in the present invention is not described in detail belongs to the well-known technique of those skilled in the art.
Claims (2)
1. a kind of very high-precision image processing VLSI verification method, it is characterised in that include the following steps:
(1) the current corresponding camera type of image for carrying out very high-precision image processing is obtained, if camera type is CCD mould
Formula then obtains row signal HEN significant level, the field signal LEN significant level, pixel clock, single-frame images pair of CCD mode camera
It answers line number H, single-frame images to correspond to columns L, row latent period respective pixel clock cycle number FOT, every pixel and occupies byte number
C obtains APS mode camera pixel clock, single-frame images corresponds to line number H, single-frame images if camera type is APS mode
Corresponding columns L, every pixel occupy byte number c, wherein H, L, FOT, c are positive integer；
(2) image shot by camera and as source images is obtained, source image data is read by byte and is converted to binary data
Format, every L*c byte data are once entered a new line, finally with the storage of TXT text formatting, until source image data is traversed,
TEXTIO format artwork data is obtained, step (3) are transferred to；Standard solution image is obtained after carrying out image simulation to source images simultaneously,
Binary data format is read and is converted to by byte to standard solution image, and every L*c byte data is once entered a new line, finally
TEXTIO format standard solution data are obtained, step (5) are transferred to until standard solution image is traversed with the storage of TXT text formatting；
(3) if camera type is CCD mode, when the bat figure enabling signal rising edge that very high-precision image processing VLSI is generated arrives
When coming, setting field signal LEN terminates horizontal blanking after waiting FOT*PCLK_T pixel clock length effectively and into row latent period
Phase, at the same by row signal HEN be set to effectively, control row signal HEN continue L*PCLK_T pixel clock length postposition be it is invalid, it is complete
At a row effective period, after repeating H row effective period, it is invalid, the picture in H row effective period that field signal LEN, which is arranged,
TEXTIO format artwork data is successively sent to the data/address bus of CCD mode camera and is transferred to step by effective edge of plain clock
(4), wherein PCLK_T is pixel clock length；The figure enabling signal of clapping is the high pulsewidth that width is greater than 2 pixel clocks
Signal, when for rising edge, the image data transmission that representative is sent to CCD mode camera starts；
If camera type is APS mode, controls very high-precision image processing VLSI and generate frame request signal F_Q signal, when
When frame request signal F_Q signal rising edge arrives, setting field marker V_L waits FOT*PCLK_ effectively and into row latent period
Terminate blanking interval after T pixel clock length, while line identifier position V_H being set to effectively, continues L*PCLK_T clock length postposition
Line identifier position V_H be it is invalid, complete a row effective period, after repeating H row effective period, setting field marker V_L is nothing
Effect, pixel clock is effectively sent to APS after by TEXTIO format artwork data progress parallel-serial conversion in H row effective period
On mode camera data signal wire, and it is transferred to step (4)；
(4) data on the data/address bus to CCD mode camera or APS mode camera data signal wire carry out very high-precision and scheme
As processing, then data-signal, every L*c byte of reading carry out line feed and deposit after the rising edge of pixel clock reads acquisition process
Storage, is finally stored as txt format, obtains the very high-precision image processing result data of TEXTIO format and be transferred to step 5；
(5) the TEXTIO format standard that will be generated in the very high-precision image processing result data of TEXTIO format and step (2)
Solution data be compared, the position of output error pixel, gray value difference, using the position of error pixel, gray value difference as
Result object, and it is transferred to step (6)；The error pixel is in very high-precision image processing result data and standard solution data
In comparison process, the unequal pixel of gray value；
(6) data bit width of pixel each in result object is denoted as M bit, sets up 2MA histogram register, and remember respectively
For label 0, label 1, label 2 ..., label (2M- 1) number of pixels that gray value difference in result object is Z, is stored in label
For the histogram register of Z, wherein Z ∈ [0,1,2 ..., (2M-1)]；
(7) histogram register is pressed into the sequence of label from small to large, it then successively will be straight since 0 histogram register of label
Data add up in square figure register, when sum of all pixels ratio is 0.1% in accumulated value and result images, record last cumulative
Histogram register label, and be denoted as Dmin, when sum of all pixels ratio is 99.9% in accumulated value and result images, record is most
Cumulative histogram register label afterwards, and it is denoted as Dmax；
(8) position is that the gray value g (x, y) of the pixel of (x, y) is in the image after adjustment threshold value distribution is calculated
Wherein, f (x, y) is the pixel that location of pixels is (x, y) in the very high-precision image processing result data of TEXTIO format
Gray value；
And then it is adjusted the image after threshold value distribution, choose ash in the very high-precision image processing result data of TEXTIO format
The maximum value of angle value difference, as error minimum value, is then chosen as max value of error, the minimum value of gray value difference
The singular point of gray value difference and judged in the very high-precision image processing result data of TEXTIO format, if error is most
Big value, error minimum value, singular point gray value difference are in [- 2,2], then current very high-precision image processing VLSI verifying is logical
It crosses, otherwise verifies and do not pass through.
2. a kind of very high-precision image processing VLSI verification method according to claim 1, it is characterised in that: pair
Source images obtain the method for standard solution image after carrying out image simulation as C or MATLAB emulation.
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| CN101826050A (en) * | 2010-02-03 | 2010-09-08 | 北京龙芯中科技术服务中心有限公司 | Random verification method and device for verifying processor chip after manufacturing |
| CN105893685A (en) * | 2016-04-11 | 2016-08-24 | 浪潮电子信息产业股份有限公司 | VLSI (Very Large Scale Integration) formal verification platform and method |
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