CN106328620B - Integrated circuit package and method of manufacturing the same - Google Patents

Integrated circuit package and method of manufacturing the same Download PDF

Info

Publication number
CN106328620B
CN106328620B CN201610730365.9A CN201610730365A CN106328620B CN 106328620 B CN106328620 B CN 106328620B CN 201610730365 A CN201610730365 A CN 201610730365A CN 106328620 B CN106328620 B CN 106328620B
Authority
CN
China
Prior art keywords
chip
integrated circuit
package
circuit package
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201610730365.9A
Other languages
Chinese (zh)
Other versions
CN106328620A (en
Inventor
李威弦
吴云燚
李菘茂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Riyuexin semiconductor (Suzhou) Co.,Ltd.
Sun moonlight Semiconductor Manufacturing Co., Ltd
Original Assignee
Suzhou ASEN Semiconductors Co Ltd
Advanced Semiconductor Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou ASEN Semiconductors Co Ltd, Advanced Semiconductor Engineering Inc filed Critical Suzhou ASEN Semiconductors Co Ltd
Priority to CN201610730365.9A priority Critical patent/CN106328620B/en
Publication of CN106328620A publication Critical patent/CN106328620A/en
Application granted granted Critical
Publication of CN106328620B publication Critical patent/CN106328620B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention relates to an integrated circuit package and a manufacturing method thereof. An integrated circuit package according to an embodiment of the present invention includes: a package substrate having a first surface and a second surface, wherein the second surface has a plurality of internal pins; a first chip disposed on the first surface of the package substrate; a first insulating shell for shielding the first surface of the packaging substrate and the first chip; a second chip disposed on the second surface of the package substrate, wherein the first chip and the second chip are respectively configured to be electrically connected to respective ones of the plurality of internal pins; a lead frame disposed on the second surface of the package substrate and configured to be electrically connected to each of the plurality of internal pins; and a second insulating housing at least shielding the second surface of the package substrate, the second chip and the lead frame. The embodiment of the invention can solve the technical problems of the prior art such as the falling or collapse of the solder ball, the thermal deformation of the packaging substrate and the like.

Description

Integrated circuit package and method of manufacturing the same
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to an integrated circuit package and a method for manufacturing the same.
Background
In a conventional integrated circuit package, for a dual-sided module package using a package substrate, external pins or internal pins are generally formed by using Solder balls (Solder balls), conductive pillars, Stud bumps (Stud bumps), Stacked bumps (Stacked bumps), and the like, and are electrically connected to the package substrate, and used as external signal transmission terminals of the integrated circuit package. However, the above-described pin structure has the following drawbacks when applied:
first, during reflow bonding, the raised solder balls or bumps are prone to fall off or collapse, which causes problems such as missing balls or inconsistent ball heights in the integrated circuit package, and thus, the integrated circuit package using the solder balls has the defects of low yield and product stability during the production process.
Secondly, when the chip to be packaged is a high-power chip, such as a power amplifier chip, the ic package is likely to generate a large amount of heat during the use process, and the contact area between the leads and the package substrate, represented by solder balls, is small, which cannot provide good heat dissipation, and is likely to cause the high-power chip to be burned due to overheating. Further, the package substrate is also prone to thermal deformation (warp) due to the accumulation of heat.
Therefore, there is a need for an improved integrated circuit package and method of manufacturing the same to solve the problems of the prior art.
Disclosure of Invention
An objective of the present invention is to provide an integrated circuit package and a method for manufacturing the same, which can solve the technical problems of the prior art, such as solder ball falling or collapse, thermal deformation of a package substrate, etc.
An embodiment of the invention provides an integrated circuit package. The integrated circuit package includes: a package substrate having a first surface and a second surface, wherein the second surface is provided with a plurality of internal pins; a first chip disposed on the first surface of the package substrate; a first insulating shell which shields the first surface of the packaging substrate and the first chip; a second chip disposed on the second surface of the package substrate, wherein the first chip and the second chip are respectively configured to be electrically connected to corresponding ones of the plurality of internal pins; a lead frame disposed on the second surface of the package substrate and configured to be electrically connected to each of the plurality of internal leads; and a second insulating housing at least covering the second surface of the package substrate, the second chip, and the lead frame.
According to another embodiment of the present invention, the lead frame includes a chip accommodating seat having an accommodating space for accommodating the second chip, and a plurality of leads arranged around the chip accommodating seat. The internal pins are formed by brushing solder paste on the second surface and are electrically connected with the lead frame. The integrated circuit package may further include a mounting element disposed on the first surface of the package substrate. The integrated circuit package may further include a shielding metal layer configured to shield the upper surface and sidewalls of the first insulating case, the sidewalls of the package substrate, and the sidewalls of the second insulating case. The shielding metal layer is formed by a surface coating process or a surface sputtering process. The first chip and the second chip are high-power chips.
An embodiment of the present invention further provides a method for manufacturing an integrated circuit package, including: providing a packaging substrate, wherein the packaging substrate is provided with a first surface and a second surface; forming a plurality of internal pins on the second surface; disposing a first chip on the first surface of the package substrate, wherein the first chip is configured to be electrically connected to a respective one of the plurality of internal leads; injecting to form a first insulating shell for shielding the first surface of the packaging substrate and the first chip; disposing a second chip on the second surface of the package substrate, wherein the second chip is configured to be electrically connected to a respective one of the plurality of internal pins; disposing a lead frame on the second surface of the package substrate, wherein the lead frame is pre-injection molded and configured to electrically connect to each of the plurality of internal pins; and forming a second insulating shell for shielding the second surface of the packaging substrate, the second chip and the lead frame by injection molding. The pre-injection treatment comprises an injection molding process, digging by a planer tool and stamping and molding by a mold.
The integrated circuit package and the manufacturing method thereof provided by the embodiment of the invention utilize the lead frame and the plurality of internal pins to replace the traditional structures such as the solder balls, the conductive columns, the columnar bulges, the bulge stacking and the like, effectively avoid the technical problems of the prior art such as the falling or collapse of the solder balls, the thermal deformation of the package substrate and the like, are particularly suitable for the field of the package of high-power chips, and improve the quality, the reliability and the qualification rate of products.
Drawings
FIG. 1 is a schematic diagram of a longitudinal cross-section of an integrated circuit package according to an embodiment of the invention
FIGS. 2-8 are schematic process diagrams illustrating a method for manufacturing an integrated circuit package according to an embodiment of the invention
Detailed Description
In order that the spirit of the invention may be better understood, some preferred embodiments of the invention are described below.
Fig. 1 is a schematic longitudinal cross-sectional view of an integrated circuit package 10 according to one embodiment of the invention.
As shown in fig. 1, an integrated circuit package 10 according to an embodiment of the present invention includes a package substrate 11, a first chip 13, a first insulating case 14, a second chip 15, a lead frame 16, and a second insulating case 17. The package substrate 11 has a first surface 110 and a second surface 111, and the second surface 111 is provided with a plurality of inner leads 12. The first chip 13 and the second chip 15 may be high power chips, wherein the first chip 13 is disposed on the first surface 110 of the package substrate 11, the second chip 15 is disposed on the second surface 111 of the package substrate 11, and the first chip 13 and the second chip 15 are respectively configured to be electrically connected to corresponding ones of the plurality of internal leads 12. The first insulating housing 14 shields the first surface 110 of the package substrate 11 and the first chip 13. The lead frame 16 is disposed on the second surface 111 of the package substrate 11 and is configured to be electrically connected to each of the plurality of internal leads 12. The second insulating housing 17 covers at least the second surface 111 of the package substrate 11, the second chip 15, and the lead frame 16.
Further, the lead frame 16 of the integrated circuit package 10 includes a chip-receiving socket 18 and a plurality of leads 19. The chip-accommodating base 18 has a first surface 181 and a second surface 182, the first surface 181 is configured to form an accommodating space 183 for accommodating the second chip 15 (in the figure, besides accommodating the second chip 15, the accommodating space is filled with an injection molding material of the second insulating housing 17, see also fig. 6), and the plurality of pins 19 are configured to be arranged around the chip-accommodating base 18.
In the present embodiment, several internal leads 12 of the integrated circuit package 10 may be formed by printing solder paste.
As shown in fig. 1, in the present embodiment, the integrated circuit package 10 may further include a mounting component 21. The mounted component 21 is disposed on the first surface 110 of the package substrate 11 and is also shielded by the first insulating case 14.
Furthermore, in the present embodiment, the integrated circuit package 10 may further include a shielding metal layer 22 to further improve the anti-electromagnetic interference performance. The shielding metal layer 22 may be formed by a surface coating process or a surface sputtering process, and shields the upper surface and the sidewalls of the first insulating housing 14, the sidewalls of the package substrate 11, and the sidewalls of the second insulating housing 17.
The present embodiment uses the lead frame 16 and the plurality of inner leads 12 in the integrated circuit package 10 to replace the conventional lead structure such as solder ball, conductive post, etc. to obtain many advantages: first, the lead frame 16 and the inner leads 12 replace the conventional lead structure, so as to effectively prevent the raised solder balls or bumps from falling or collapsing during the reflow bonding process, thereby improving the yield and stability of the product. Secondly, the chip accommodating seat 18 of the lead frame 16 not only provides the accommodating space 183 for the second chip 15, but also provides a larger heat dissipation area. Therefore, even if the second chip 15 is a high-power chip, it is possible to prevent the second chip from being burned due to overheating caused by poor heat dissipation in an operating state, and to prevent the package substrate 11 from being thermally deformed due to the heat accumulated continuously. Furthermore, the size of the lead frame 16 and the location of the leads 19 thereof can be designed with respect to the size of the integrated circuit package 10 and the location of the internal leads 12, and thus the design flexibility is large. Accordingly, the lead frame 16 may be adapted for use with a variety of different sizes and configurations of integrated circuit packages 10, and more particularly for use in a two-sided modular packaging process on a package substrate 11.
Fig. 2-8 are process diagrams of a method of manufacturing an integrated circuit package that can manufacture the integrated circuit package 10 of fig. 1, according to one embodiment of the invention.
Fig. 2 is a schematic longitudinal cross-sectional view of a package substrate array 20 to be packaged. The package substrate array 20 to be packaged includes a plurality of package units 30 to be packaged, and each package unit 30 corresponds to an integrated circuit package 10 after being packaged. Due to layout constraints, fig. 2 shows only two packaging units 30 to be packaged, similar to fig. 3-8. Each package unit 30 includes a package substrate 11 having a first surface 110 and a second surface 111. The first chip 13 and the mounted device 21 are disposed on the first surface 110 of the package substrate 11 by a packaging means such as wire bonding, so that the first chip 13 and the mounted device 21 are disposed to be electrically connected to the package substrate 11.
Next, as shown in fig. 3, the first insulating case 14 shielding the first surface 110 of the package substrate 11, the first chip 13, the mounted component 21, and the like is injection-molded, thereby basically realizing the module package on the first surface 110 side of the package substrate 11. The above encapsulation process is common knowledge in the art, and therefore, will not be described herein.
Solder paste is printed on the second surface 111 of the package substrate 11 according to the design requirements of the internal leads 12 to form a plurality of internal leads 12 on the second surface 111 as shown in fig. 4.
As shown in fig. 5, the second chip 15 is disposed on the second surface 111 of the package substrate 11. As will be appreciated by those skilled in the art, conventional flip chip mounting is used herein and will not be described in detail.
After the inner leads 12 are formed and the second chip 15 is mounted to the second surface 111 of the package substrate 11, the pre-molded lead frame 16 may be secured to the second surface 111 of the package substrate 11, as shown in fig. 6. The pre-molded lead frame 16 may be formed by a conventional molding process, a planer tool, and a mold press, which are not described herein. The lead frame 16 includes a chip receiving pocket 18 and a plurality of leads 19. the pre-injection process secures the discrete chip receiving pockets 18 and leads 19 of the lead frame 16 together. The chip-receiving seat 18 has a first surface 181 and a second surface 182, the first surface 181 is configured to form a receiving space 183 for receiving the second chip 15, and the plurality of leads 19 are configured to be arranged around the chip-receiving seat 18. The leads 19 of the lead frame 16 and the solder paste corresponding to the inner leads 12 on the second surface 111 of the package substrate 11 can be soldered together by reflow, so that the first chip 13, the mounted component 21 and the second chip 15 can be electrically connected to corresponding ones of the inner leads 12 respectively, and further can be connected to an external circuit through the inner leads 12 via the leads 19 of the lead frame 16.
Similarly, as shown in fig. 7, after the electrical components on the second surface 111 of the package substrate 11 are arranged, a second insulating housing 17 covering the second surface 111 of the package substrate 11, the second chip 15, the lead frame 16, and the like may be formed by injection molding, so as to protect the electrical components and the connection arrangement packaged on the second surface 111 of the package substrate 11. The above processes are common knowledge in the art, and therefore are not described herein.
Next, similarly to the conventional operation, as shown in fig. 8, the package substrate array 20 is cut to separate the package units 30. In the present embodiment, to achieve better shielding effect, the shielding metal layer 22 may be formed by a surface coating process or a surface sputtering process, which requires that the inner leads 12 with the grounding configuration in each of the package units 30 after cutting are exposed to the sidewall of the second insulating housing 17. The shielding metal layer 22 shields the upper surface and the sidewalls of the first insulating housing 14, the sidewalls of the package substrate 11, and the sidewalls of the second insulating housing 17, so as to obtain a plurality of integrated circuit packages 10 as shown in fig. 1.
The manufacturing method of the integrated circuit package according to the embodiment of the invention does not need special processes such as half-cutting, avoids high cost caused by repeated processing, and is easy to combine with the process of forming the shielding metal layer, thereby realizing shielding of electromagnetic interference.
While the foregoing has been with reference to the disclosure of the present invention, it will be appreciated by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the protection scope of the present invention should not be limited to the disclosure of the embodiments, but should include various alternatives and modifications without departing from the invention, which are covered by the claims of the present patent application.

Claims (12)

1. An integrated circuit package, comprising:
the package substrate is provided with a first surface and a second surface, wherein the second surface is provided with a plurality of internal pins;
a first chip disposed on the first surface of the package substrate;
the first insulating shell covers the first surface of the packaging substrate and the first chip;
a second chip disposed on the second surface of the package substrate, wherein the first chip and the second chip are each configured to be electrically connected to a respective one of the number of internal pins;
a lead frame disposed on the second surface of the package substrate and configured to be electrically connected to each of the plurality of internal leads; and
and the second insulating shell at least shields the second surface of the packaging substrate, the second chip and the lead frame.
2. The integrated circuit package of claim 1, wherein the leadframe comprises:
the chip accommodating seat is provided with an accommodating space for accommodating the second chip; and
the pins are arranged around the chip containing seat.
3. The integrated circuit package of claim 1, wherein the number of internal pins are formed by brushing solder paste on the second surface and make electrical connection with the leadframe.
4. The integrated circuit package of claim 1, further comprising:
and the mounting component is arranged on the first surface of the packaging substrate.
5. The integrated circuit package of claim 1, further comprising:
a shielding metal layer configured to shield an upper surface and sidewalls of the first insulating case, sidewalls of the package substrate, and sidewalls of the second insulating case.
6. The integrated circuit package of claim 5, wherein the shield metal layer is formed by a surface coating process or a surface sputtering process.
7. The integrated circuit package of claim 1, wherein the first chip and the second chip are high power chips.
8. A method of manufacturing an integrated circuit package, comprising:
providing a packaging substrate, wherein the packaging substrate is provided with a first surface and a second surface;
forming a plurality of internal pins on the second surface;
disposing a first chip on the first surface of the package substrate, wherein the first chip is configured to be electrically connected with a respective one of the number of internal pins;
injecting to form a first insulating shell for shielding the first surface of the packaging substrate and the first chip;
disposing a second chip on the second surface of the package substrate, wherein the second chip is configured to be electrically connected with a respective one of the number of internal pins;
disposing a leadframe on the second surface of the package substrate, wherein the leadframe is pre-injection molded and configured to electrically connect with each of the number of internal pins; and
and injection molding is carried out to form a second insulating shell for shielding the second surface of the packaging substrate, the second chip and the lead frame.
9. The method of manufacturing an integrated circuit package of claim 8, further comprising:
and forming a shielding metal layer for shielding the upper surface and the side wall of the first insulating shell, the side wall of the packaging substrate and the side wall of the second insulating shell by using a surface coating process or a surface sputtering process.
10. The method of manufacturing an integrated circuit package of claim 8, wherein the leadframe comprises:
the chip accommodating seat is provided with an accommodating space for accommodating the second chip; and
the pins are arranged around the chip containing seat.
11. The method of manufacturing an integrated circuit package as recited in claim 8, wherein forming internal pins on the second surface is by brushing solder paste on the second surface.
12. The method of claim 8, wherein the pre-injection molding process comprises an injection molding process, a router bit digging process, and a mold press forming process.
CN201610730365.9A 2016-08-26 2016-08-26 Integrated circuit package and method of manufacturing the same Active CN106328620B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610730365.9A CN106328620B (en) 2016-08-26 2016-08-26 Integrated circuit package and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610730365.9A CN106328620B (en) 2016-08-26 2016-08-26 Integrated circuit package and method of manufacturing the same

Publications (2)

Publication Number Publication Date
CN106328620A CN106328620A (en) 2017-01-11
CN106328620B true CN106328620B (en) 2021-03-09

Family

ID=57790494

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610730365.9A Active CN106328620B (en) 2016-08-26 2016-08-26 Integrated circuit package and method of manufacturing the same

Country Status (1)

Country Link
CN (1) CN106328620B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111415913B (en) * 2020-04-09 2021-10-01 环维电子(上海)有限公司 Selective packaging SIP module with electromagnetic shielding structure and preparation method thereof
CN113923936B (en) * 2021-08-30 2023-08-25 国网安徽省电力有限公司枞阳县供电公司 Power electronic module and power electronic component packaging substrate

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2528113Y (en) * 2002-01-18 2002-12-25 胜开科技股份有限公司 Multi-chip packaging assembly
US7141874B2 (en) * 2003-05-14 2006-11-28 Matsushita Electric Industrial Co., Ltd. Electronic component packaging structure and method for producing the same
CN101989581B (en) * 2009-07-31 2012-07-04 日月光半导体制造股份有限公司 Packaging structure and packaging method
US8409922B2 (en) * 2010-09-14 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect
CN102163590A (en) * 2011-03-09 2011-08-24 中国科学院上海微系统与信息技术研究所 Three-dimensional multi-chip encapsulation module based on buried substrate and method
TWI419270B (en) * 2011-03-24 2013-12-11 Chipmos Technologies Inc Package on package structure
CN102709260B (en) * 2012-05-08 2015-05-20 日月光半导体制造股份有限公司 Semiconductor packaging structure
CN105720021B (en) * 2016-01-25 2020-02-11 苏州日月新半导体有限公司 Integrated circuit package and method of manufacturing the same
CN206163478U (en) * 2016-08-26 2017-05-10 苏州日月新半导体有限公司 Integrated circuit package

Also Published As

Publication number Publication date
CN106328620A (en) 2017-01-11

Similar Documents

Publication Publication Date Title
US10566320B2 (en) Method for fabricating electronic package
US10211190B2 (en) Semiconductor packages having reduced stress
US6570249B1 (en) Semiconductor package
US7960827B1 (en) Thermal via heat spreader package and method
US20200120810A1 (en) Board-level architecture, method for manufacturing board-level architecture, and mobile terminal
US7489044B2 (en) Semiconductor package and fabrication method thereof
TWI517333B (en) Integrated circuit package system with dual connectivity
JP2008537333A (en) Layered structure of integrated circuits on other integrated circuits
JPH11312764A (en) Area array type semiconductor package and its manufacture
CN112234048B (en) Electromagnetic shielding module packaging structure and electromagnetic shielding module packaging method
KR20110124065A (en) Stack type semiconductor package
CN106328620B (en) Integrated circuit package and method of manufacturing the same
CN112018055B (en) Electromagnetic shielding heat dissipation packaging structure and preparation method thereof
US10886235B2 (en) Integrated shield package and method
KR100913171B1 (en) The fabrication method of stack package
US11869831B2 (en) Semiconductor package with improved board level reliability
JP4435756B2 (en) Semiconductor device
US20080185698A1 (en) Semiconductor package structure and carrier structure
CN101271888A (en) Integrated circuit package and manufacturing method thereof
US20180240738A1 (en) Electronic package and fabrication method thereof
CN111554674B (en) Package body with electromagnetic shielding function and packaging process
JP5302234B2 (en) Semiconductor device
KR20140147528A (en) semiconductor package and connection structure of a semiconductor package and mounting method of semiconductor packages
US8853849B2 (en) Package arrangement and a method of manufacturing a package arrangement
KR20150014282A (en) Semiconductor chip package module and manufacturing method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CP03 Change of name, title or address
CP03 Change of name, title or address

Address after: No. 188, Suhong West Road, Suzhou Industrial Park, Suzhou, Jiangsu

Patentee after: Riyuexin semiconductor (Suzhou) Co.,Ltd.

Patentee after: Sun moonlight Semiconductor Manufacturing Co., Ltd

Address before: 215026 No.188 Suhong West Road, Suzhou Industrial Park, Suzhou City, Jiangsu Province

Patentee before: SUZHOU ASEN SEMICONDUCTORS Co.,Ltd.

Patentee before: Sun moonlight Semiconductor Manufacturing Co., Ltd