CN106301746A - Clock recovery method and device - Google Patents
Clock recovery method and device Download PDFInfo
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- CN106301746A CN106301746A CN201510284136.4A CN201510284136A CN106301746A CN 106301746 A CN106301746 A CN 106301746A CN 201510284136 A CN201510284136 A CN 201510284136A CN 106301746 A CN106301746 A CN 106301746A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
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Abstract
The invention discloses a kind of clock recovery method and device, described method includes: read the water level controlling caching；The described water level of caching that controls is for characterizing the write data volume of data buffer storage and writing out the difference of data volume；According to the described water level controlling caching, form recovered clock.
Description
Technical field
The present invention relates to the simultaneous techniques of the communications field, particularly relate to a kind of clock recovery method and device.
Background technology
When carrying out data transmission, might typically relate to clock recovery, if receiving side cannot recover transmission
The clock of side, may result in the difficulty of data demodulation, and causes Data reception errors.If receiving side to be recovered
Recovered clock accurate not, the problem such as the error rate of data receiver can be caused high.
The method of clock recovery in the prior art includes that the data to receiving side transmission carry out a period of time
Data volume accumulates, and the water level conversion of described data buffer storage in reading this period, according to described data
The water level conversion of caching and the time interval of this period, estimate the clock frequency of sending side, this
Mode there is the problem that the accumulation carrying out data with the water level of data buffer storage, at this moment may require described
The spatial cache of data buffer storage is relatively big, if the spatial cache of data buffer storage is inadequate, at described data buffer storage
When writing rate is bigger, the phenomenon that data are overflowed may occur within this period, so obviously can shadow
Ring the result of clock recovery, it is clear that the resources such as the caching of consumption are bigger.
Summary of the invention
In view of this, embodiment of the present invention expectation provides a kind of clock recovery method and device, with at least partly
Solve the problem that the precision of the clock recovery that the phenomenons such as data spilling in data buffer storage cause is low.
For reaching above-mentioned purpose, the technical scheme is that and be achieved in that: embodiment of the present invention first party
Face provides a kind of clock recovery method, and described method includes:
Read the water level controlling caching；The described water level of caching that controls is for characterizing the write data of data buffer storage
Measure and write out the difference of data volume；
According to the described water level controlling caching, form recovered clock.
Based on such scheme, the described water level according to described control caching, form recovered clock, including:
The cycle count of the described water level and local clock controlling caching is compared, forms comparative result；
The cycle count of described local clock is the described data buffer storage sampling period according to local clock write data
Cycle count；
According to described comparative result, form described recovered clock.
Based on such scheme, the described cycle count by the described water level and local clock controlling caching compares
Relatively, form comparative result, including:
When the described water level controlling caching is more than the cycle count of described local clock, it is output as logic high electricity
Flat adjustment signal；
When the described water level controlling caching is less than the cycle count of described local clock, it is output as logic low electricity
Flat adjustment signal；
Described according to described comparative result, form recovered clock, including:
According to described adjustment signal, form described recovered clock.
Based on such scheme, described method also includes:
The average writing rate of described data buffer storage in the statistics appointment time；
Wherein, the water level of described average writing rate and described data buffer storage is used for being collectively forming described control and delays
The water level deposited.
Based on such scheme, described method also includes:
The water level of described average writing rate and described data buffer storage is smoothed, forms smoothing processing
As a result, so that the write data volume of described data buffer storage is evenly distributed to each time period；
Described smoothing processing result is for forming the described water level controlling caching.
Based on such scheme, described method also includes:
According to the described water level controlling caching, by adjusting described recovered clock to adjust described data buffer storage
Write out speed.
Based on such scheme, described method also includes:
When the described water level variable controlling caching is maintained in the range of first threshold, detects described data and delay
The water level deposited；The water level of described data buffer storage characterizes data volume to be write out in described data buffer storage；
When the water level of described data buffer storage be positioned at Second Threshold scope outer time, by adjust described recovered clock with
Adjust described data buffer storage writes out speed, so that the water level of described data buffer storage is in described Second Threshold model
In enclosing.
Embodiment of the present invention second aspect provides a kind of clock recovery device, and described device includes:
Read unit, for reading the water level controlling caching；The described water level controlling caching is used for characterizing data
The write data volume of caching and the difference writing out data volume；
Comparison module recovery unit, for the comparative result according to the described water level controlling caching, is formed and recovers
Clock.
Based on such scheme, described recovery unit also includes:
Comparison module, for the cycle count of the described water level and local clock controlling caching is compared,
Form comparative result；The cycle count of described local clock is that described data buffer storage writes number according to local clock
According to the cycle count in sampling period；
Recover module, specifically for according to described comparative result, form described recovered clock.
Based on such scheme, described comparison module, including:
First output sub-module, by being more than based on the circulation of described local clock when the described water level controlling caching
During number, it is output as the adjustment signal of logic high；
Second output sub-module, by being less than based on the circulation of described local clock when the described water level controlling caching
During number, it is output as the adjustment signal of logic low；
Described recovery module, specifically for according to logic high in described adjustment signal and logic low
Ratio, determines the frequency of described recovered clock.
Based on such scheme, described device also includes:
Statistic unit, the average writing rate of described data buffer storage in adding up the appointment time；
Wherein, the water level of described average writing rate and described data buffer storage is used for being collectively forming described control and delays
The water level deposited.
Based on such scheme, described recovery unit, for described average writing rate and described data buffer storage
Water level be smoothed, formed smoothing processing result so that the write data volume of described data buffer storage is equal
Even it is distributed to each time period；
Described smoothing processing result is for forming the described water level controlling caching.
Based on such scheme, described recovery unit, for according to the described water level controlling caching, by adjusting
Described recovered clock writes out speed with the described data buffer storage of adjustment.
Based on such scheme, described determine module, for being maintained at when the described water level variable controlling caching
Time in the range of first threshold, detect the water level of described data buffer storage；The water level of described data buffer storage characterizes described
Data volume to be write out in data buffer storage；When outside the water level of described data buffer storage is positioned at Second Threshold scope,
Speed is write out with adjust described data buffer storage by adjusting described recovered clock, so that described data buffer storage
In the range of water level is in described Second Threshold.
Clock recovery method described in the embodiment of the present invention and device, the foundation when carrying out described clock recovery
It is the water level controlling caching, rather than the water level of data buffer storage；When thus avoiding described data buffer storage spilling
There is recovered clock accuracy and the poor accuracy changing, and then result in greatly in the water level causing data buffer storage
Problem.Meanwhile, accuracy and the accuracy of the effect of flood recovered clock of data buffer storage need not be prevented again,
Can be suitable reduce the buffer memory capacity that described data buffer storage is corresponding such that it is able to reduce the system such as buffer memory capacity
Resource.
Accompanying drawing explanation
Fig. 1 a is one of schematic flow sheet of clock recovery method described in the embodiment of the present invention；
Fig. 1 b is the two of the schematic flow sheet of the clock recovery method described in the embodiment of the present invention；
Fig. 2 is the effect schematic diagram of comparative result described in the embodiment of the present invention；
Fig. 3 is the state transformation schematic diagram of the clock recovery described in the embodiment of the present invention；
Fig. 4 a is one of structural representation of clock recovery device described in the embodiment of the present invention；
Fig. 4 b is the two of the structural representation of the clock recovery device described in the embodiment of the present invention；
Fig. 5 is the three of the schematic flow sheet of the clock recovery described in the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with Figure of description and specific embodiment technical scheme done and further explain in detail
State.
As shown in Figure 1a, the present embodiment provides a kind of clock recovery method, and described method includes:
Step S110: read the water level controlling caching；The described water level controlling caching is used for characterizing data buffer storage
Write data volume and write out the difference of data volume；
Step S120: according to the described water level controlling caching, form recovered clock.
Clock recovery method described in the present embodiment, for being applied in the device of data receiver side, concrete such as light
In the reception equipment such as the receiving terminal of signal.
Described data buffer storage for receiving data and caching, simultaneously by the most slow in described data buffer storage from sending side
The data deposited are write out.The described caching that controls is for characterizing the write data volume of described data buffer storage and writing out data
The difference of amount.
Described control caching can be equivalent to a forward-backward counter, can be used for when described data buffer storage writes one
Add 1 during unit data；Subtract 1 when described data buffer storage writes out the data of a unit.Like this, if institute
State data buffer storage normally to work, thus can accurately indicate when described data buffer storage works, in data buffer storage
Write and the data volume write out.Certainly, described data buffer storage is occurred by the described control caching in the present embodiment
During the situations such as spilling, it is not that data are normally write out that the data of described data buffer storage are overflowed, and does not affect described control
The water level of caching.Such as, if the current water level controlling caching is S1；If data buffer storage overflows S2 unit
Data, this part overflow data can not affect described control caching water level, described control caching
Water level, after the data overflowing S2 unit, keeps S1.
The data of 1 unit described in the present embodiment can be regarded as the data that an employing cycle can sample
Amount is concrete such as the data of 1 bit.
The present embodiment utilize the water level controlling caching be simply aware of data buffer storage writing within a period of time
Enter speed and the difference writing out between speed.If the writing rate of described data buffer storage is more than described data buffer storage
Write out speed, it is clear that such described control caching water level can uprise；Described data buffer storage is when this section
Interior writing rate is less than writing out speed, and the most described water level controlling caching can step-down.The most so institute
State the water level controlling to cache can show the write data of described data buffer storage accurately and write out between speed
Difference.By read control caching water level determine described data buffer storage writing rate and write out speed it
Between relation, it is clear that will cause clock recovery degree of accuracy that relatively large deviation occurs because of the spilling of data buffer storage
Problem, it is clear that improve the precision of clock recovery.And for need not specially prevent overflowing of described data buffer storage
Go out, can be suitable reduce buffer area corresponding to described data buffer storage such that it is able to reduce in clock recovery
The system resources such as the caching taken.
The most how to control clock recovery according to the described water level controlling caching, have a variety of mode, below
A kind of optional mode is provided.
As shown in Figure 1 b, described step S120 includes:
Step S121: the cycle count of the described water level and local clock controlling caching is compared, is formed
Comparative result；The cycle count of described local clock is that described data buffer storage writes data according to local clock
The cycle count in sampling period；
Step S122: according to described comparative result, forms recovered clock.
When described data buffer storage carries out data buffer storage, it is to use local clock to carry out data sampling, described number
Data sampling one described sampling period of formation is carried out according to caching each local clock.During described this locality
The cycle count of clock just meter 1.As described in data buffer storage before carrying out this data sampling, described this locality
The cycle count of clock is N, and the most described data buffer storage performs this data acquisition and uses afterwards, described local ten
The cycle count in week is M.The described water level controlling caching is then to have a unit data at described data buffer storage
During write, counting adds 1.If current data caching uses local clock to sample, n times of having sampled, its
Sample data middle n time, (tables of data that samples here is shown with data and is written to described data buffer storage),
The cycle count of the most described local clock is N, and the water level of described control caching adds n.
In the present embodiment the sampling number of described data buffer storage is by cycle count, i.e. when described number
Reaching maximum count value according to count value, the most described local clock cycle count resets.Described in the present embodiment
The value of the water level controlling caching also has the upper limit, the most described upper limit, the water of described control caching
Saturated process is done in position.Described saturated process herein by: if the writing rate of data buffer storage continues more than being write
Going out data, the water level of described control caching no longer rises and maintains count upper-limit.The most optional
For the maximum count value of the described upper limit controlling caching and described local cycle count is both configured to same taking
Value.
In the present embodiment by the cycle count of relatively described local clock and the described water level controlling caching, shape
Become comparative result；This comparative result will act on formation and the generation of recovered clock.
Described step S121 comprises the steps that
When the described water level controlling caching is more than the cycle count of described local clock, it is output as logic high electricity
Flat adjustment signal；
When the described water level controlling caching is less than the cycle count of described local clock, it is output as logic low electricity
Flat adjustment signal.
Logic high described in the present embodiment and described logic low are comparatively speaking, here logic high electricity
When gentle described logic low is relative to same datum, the level that described logic high is corresponding is higher than
The corresponding level of described logic low.Described logic high and described logic low form described tune
Entire signal.If the maximum count value of the cycle-index of described local clock is K, then adjust described in one
The time span that entire signal is corresponding is equal to the cycle of K described local clock.
Described step S122 comprises the steps that according to described adjustment signal, forms described recovered clock.Herein, tool
Body comprises the steps that the dutycycle calculating described adjustment signal, forms described recovered clock according to described dutycycle.
As in figure 2 it is shown, a described adjustment signal is T1 for time of logic high, for logic low electricity
The flat time is T2；The most described dutycycle can be T1/ (T1+T2).
The concrete method producing described recovered clock, is operated in target frequency including employing in the step s 120
The clock source of f1 produces target clock f1.Adjust described f1 according to described dutycycle, form described recovered clock
f2.Clock source herein can be the structure of various types of generation clock, ties such as voltage controlled oscillator VCXO etc.
Structure.Described VCXO crystal oscillator under Control of Voltage produces clock.Assume to meet between described f2 and described f1
Following functional relationship:
F2=f1+2{T1/ (T1+T2)-0.5}*X
Like this, when described dutycycle is 1, described f2=f1+X*f1；Described X can be that clock adjusts
Scope, the span of described X may generally be and is arbitrarily designated value, and the most such as, the value of described X is
100PPM.If described dutycycle is 0, described f2=f1-X*f1.If described dutycycle is 0.5, institute
State f2=f1.The most like this, the described water level controlling caching will determine the adjustment of described recovered clock.
The precision of described recovered clock is equal to 2X*f1/K.
As further improvement of this embodiment, described method also includes:
The average writing rate of described data buffer storage in the statistics appointment time；
Wherein, the water level of described average writing rate and described data buffer storage is used for being collectively forming described control and delays
The water level deposited.Now, what the described water level controlling caching characterized not only includes writing data volume and writing out data
The difference of amount, also includes described average writing rate.
The described water level controlling caching can characterize the data volume that described data buffer storage is to be write out.
Side joint is received data and sent data is to there is certain rule, and the most described reception side will be to finger
The write data of interior described data reception data of fixing time are added up, thus know that described receiving terminal sends number
According to substantially rule.Average writing rate in the appointment time that this rule is just presented as said write data.
The condition information of write data described here can be regarded as this locality of substantially every M the described receiving terminal of receiving terminal
It is roughly the same that clock cycle sends data volume.
Described timing statistics in the present embodiment be according to time period of determining of the rule of described data, specifically
Such as M local clock cycles.
Assume that described data buffer storage write data volume is P as in M local clock cycles.But can
Can there is a case in which, in described M local clock cycles, only having m1 clock above has number
According to write, if without described smoothing processing, then the described water level of caching that controls can be caused because of front m1
There are data to write in the individual cycle, and rise rapidly.Said write data volume will be done flat in the present embodiment
Sliding process, and the smoothing processing result formed.Described smoothing processing result is so that write data mean allocation
In each time period.The described appointment time can be the historical time before current time.The most described M basis
The ground clock cycle can be M local clock cycles before current time.
When carrying out clock recovery, if the described water level controlling caching is only used for characterizing writing of described data buffer storage
Enter data volume and write out data volume, then according to the described water level controlling caching carry out clock recovery to sending side
Data source clock differ appointment in the range of, although clock adjustment can be carried out, but the slowest.?
By the average writing rate in the statistics appointment time in the present embodiment, when the most probably knowing sending side clock source
Clock, if the described water level controlling caching is the water level according to described data buffer storage and the common shape of average writing rate
Become, then the water level according to controlling caching carries out clock recovery, just quickly recovers to and sending side clock source
In close clock ranges, thus improve the speed of clock capture.
Improving further as the present embodiment, described method also includes:
The water level of described average writing rate and described data buffer storage is smoothed, forms smoothing processing
As a result, so that the write data volume of described data buffer storage is evenly distributed to each time period；
Described smoothing processing result is for forming the described water level controlling caching.
In the present embodiment by the water level of average writing rate and data buffer storage is smoothed, such
Words are not result in that the water level controlling caching sends sudden change at certain time point, if not being smoothed, directly
Carrying out clock recovery according to the water level controlling caching of sudden change, this causes the frequency of recovered clock in correspondence
Time point also can change.This sudden change of recovered clock can cause other in DRP data reception process bad
Problem.
Such as, front 50 clocks in 100 local clock cycles have data to write, then be smoothed
Can make to write data afterwards is having data to write every a local clock cycles.Like this, the 1st, 3,
5,7,99 local clock cycles in 9 ... have data to write, rather than are front 50 local clocks.Due to
The regularity of the transmission data of sending side, this regularity embodies the data source of sending side to a certain extent
Clock, by the condition information of the write data in the statistics appointment time in the present embodiment, described extensive being formed
During multiple clock, just can estimate out the substantially frequency of clock source clock such that it is able to quickly form one more
Close to the recovered clock of described clock source, follow-up only need carries out trickle tune by the water level cached according to control
Whole, it is clear that to accelerate to be formed the clock capture speed of the accurate recovered clock close with described clock source clock
Rate.And due to smoothing processing can avoid according to the water level that controls caching smooth carry out described recovered clock
Frequency adjusts.
Described method also includes:
According to the described water level controlling caching, by adjusting described recovered clock to adjust described data buffer storage
Write out speed.
When the described water level controlling caching is the highest or based on the current writing rate of described data buffer storage with write out
Speed, when causing the described water level controlling caching to be progressively increased to certain threshold value, is at this moment accomplished by adjusting institute
State the speed of writing out of data buffer storage, thus reduce the described water level controlling caching.
The speed of writing out of certain described data buffer storage is formed based on recovered clock, a usual recovered clock
Cycle writes out data.Need exist for writing out speed described in adjustment to be equivalent to adjust described recovered clock.
Described data buffer storage and the state controlling to cache are divided into three states and include: trapped state, locking shape
State and tracking mode.Aforesaid according to the described water level controlling caching, adjust writing out of described data buffer storage
Speed, when usually occurring in the described state controlling to cache for capture and tracking.
As it is shown on figure 3, described control caching and data buffer storage can trapped state, lock-out state and
Switch between three states of tracking mode.Described control caching can perform lock operation from trapped state
After, enter lock-out state, it is also possible to from lock-out state by returning to trapped state after performing solution latching operation,
Gravity treatment is needed to adjust clock.Described data buffer storage can be switched to tracking mode from lock-out state, and from tracking
State by solve latching operation laggard enter lock-out state, through solution latching operation or enter trapped state.
Generally when reception side apparatus just starts, described control caching and described data buffer storage are all in capture shape
State, forms the recovered clock identical with the data source clock of sending side in trapped state by attempting.
When trapped state, the variable quantity δ of the described water level controlling caching in the statistics appointment time, according to institute
δ estimates the difference of recovered clock and sending side data source clock.
If δ>th1, write out rate N adj=N+ Δ n1, if δ<-th1, Nadj=N-be Δ n1.Described
Nadj be unit time upper described data buffer storage write out data volume；Described Δ n1 is unit time upper described number
The adjustment amount of data volume is write out according to caching；Described N is that the unit time is interior from receiving the write data volume that side joint is received,
It is aforesaid average writing rate；Described th1 is to control the threshold value that the water level of caching adjusts.Obviously at this
In example, when the variable quantity of the described water level controlling caching is between [-th1, th1], described control caches
Water level in a safe condition under, persistently follow the tracks of described control caching water level, according to control caching water level
Carry out follow-up clock recovery.Like this, by making the conversion writing out speed of data buffer storage, thus soon
The water level adjusting described control caching of speed, thus reach to control at the converted quantity of the described water level controlling caching
Purpose in safe condition.
Certainly, if-th1 < δ < th1, illustrate when reception side apparatus forms recovered clock with sending side data source
Clock is close, then can control caching and can enter lock-out state.At acquisition phase, only depend on control slow
Deposit and reach locking condition, data buffer storage state, the buffer zone that therefore data buffer storage is corresponding can be indifferent to
Can be made very small, thus reduce the use of the system resources such as cache resources.
If after described control caching is in the lock state, be equivalent to recovered clock and sending side that sending side is formed
Clock source clock very close to or identical, but the water level of described data buffer storage is the highest, if suddenly data buffer storage
Writing rate increases, and may result in the rapid spilling of data buffer storage, thus causes the phenomenon that data abandon；With
The water level of data buffer storage described in Shi Ruo is the lowest, and the speed of writing out of data buffer storage adjusts the most timely, still protects
Holding and higher write out speed, the data that may may result in data buffer storage are all written out, and occur that data are write
The problems such as the termination gone out.In order to solve these problems, the most also said method is done following changing
Enter.
Described method also includes:
When the described water level variable controlling caching is maintained in the range of first threshold, detects described data and delay
The water level deposited；The water level of described data buffer storage characterizes data volume to be write out in described data buffer storage；Here
The variable quantity of water level controlled, can be the variable quantity of described controlling water level in the unit time；Or in appointment duration
The variable quantity of described controlling water level.
When the water level of described data buffer storage be positioned at Second Threshold scope outer time, by adjust described recovered clock with
Adjust described data buffer storage writes out speed, so that the water level of described data buffer storage is in described Second Threshold model
In enclosing.
It is concrete that such as the water level data_fifo_level of data buffer storage is more than th2, Nadj=N+ Δ n2, if
Data_fifo_level < th3, Nadj=N-Δ n2 so that control caching SEA LEVEL VARIATION, adjusts VCXO and recovers
The frequency of clock, finally makes control caching and data buffer storage reach plateau, data buffer storage water level
th3<data_fifo_level<th2.Th2 with th3 is arranged on buffer zone corresponding to data buffer storage can store data
Near the intermediate value of amount, in order to make data buffer storage be in safe condition.When the water level of data buffer storage meets
< th2 makes th3 < data_fifo_level, shows that data buffer storage performs lock operation, enters tracking mode.
Δ n2 described in the present embodiment is the step value writing out speed described in described adjustment, is also adjustment institute
State the step value of recovered clock.The first threshold scope described in the present embodiment of it should be noted that can be front
[-th1, the th1] stated.
Speed is write out according to what described recovered clock accelerated described data buffer storage, and in making described data buffer storage
Water level reduces, and vacates more remaining cache space.The most described water level controlling caching also can be rapid
Reduce.According to described recovered clock reduce described data buffer storage write out speed, in keeping described data buffer storage
Water level be in certain height, it is to avoid do not have data to write out the phenomenon writing out termination caused in data buffer storage.
After described data buffer storage enters tracking mode, control caching and data buffer storage both sides read-write speed is complete
Complete consistent, depend on the drift controlling caching SEA LEVEL VARIATION situation tracking data source clock.If writing rate
Drift cause the water level of data buffer storage to exceed the locking condition of data buffer storage, i.e. data_fifo_level > th2 or
Data_fifo_level < th3, can jump to lock-out state, makes data buffer storage again reach locking condition entrance
Lock-out state, it is ensured that the safety of data buffer storage.Data buffer storage and control caching are in dynamic equilibrium shape all the time
State, it is ensured that the stability of system longtime running.
Clock recovery method described in summary the present embodiment, when using the water level according to control caching to carry out
The capture of clock and formation, it is possible to quickly capture sending side data source clock, it is possible to significantly improve capture speed
Rate.Secondly as be to carry out clock capture based on the water level controlling caching, do not considering described data
Under the situation of the spilling of caching, it is possible to reduce the buffer size of described data buffer storage.
In the most described clock recovery method, can be at trapped state, lock-out state and tracking shape
Switch between state, it is achieved follow the tracks of continuously, effectively solve sudden the drift with sending side clock source of short-term and lead
The bursting problem caused.Use the water level controlling caching, it is to avoid it is extensive that data buffer storage overflows suddenly the clock caused
Multiple error is big etc. manifests, thus the recovered clock formed, there is the advantage that shake is little and degree of accuracy is high.Data
The speed of writing out of caching will affect the described water level controlling caching；And described control caching water level will affect extensive
The frequency of multiple clock, thus react on described data buffer storage write out speed, it is achieved thereby that clock recovery
Closed loop adjust such that it is able to realize control steady in a long-term and the tune of described recovered clock based on this closed loop
Whole, improve the stability of recovered clock.
Apparatus embodiments:
As shown in fig. 4 a, the present embodiment provides a kind of clock recovery device, and described device includes:
Read unit 110, for reading the water level controlling caching；The described water level controlling caching is used for characterizing
The write data volume of data buffer storage and the difference writing out data volume；
Comparison module 121 recovery unit 120, for the water level according to described control caching, when forming recovery
Clock.
Clock recovery device described in the present embodiment is to apply receiving the clock recovery device of side or be included in institute
State the clock recovery device receiving side.
Described reading unit 110 can include having processor or the process chip that information reads.Described processor
Can be by performing the reading that appointment codes realizes the water level of above-mentioned control caching with processing chip.Described process
Device can be application processor AP, digital signal processor DSP, programmable array PLC, central processing unit
The structure such as CPU or Micro-processor MCV.
Recovery unit 120 described in comparison module 121 can include that the crystal oscillator isochronon that can form clock forms knot
Structure, will be connected with described comparison module 121, be formed described extensive according to the output of described comparison module 121
Multiple clock.
It is extensive that the water level that the most described clock recovery device direct basis controls to cache controls clock
Multiple, thus the water level of the data buffer storage of the phenomenons such as spilling easily occurs to carry out clock recovery relative to foundation
Controlling, the recovered clock of formation has accuracy and the high advantage of accuracy.
As described in Fig. 4 b, described recovery unit 120 includes:
Comparison module 121, for comparing the cycle count of the described water level and local clock controlling caching
Relatively, comparative result is formed；The cycle count of described local clock is for characterizing the number that described data buffer storage reads
According to amount；
Recover module 122, for according to described comparative result, form described recovered clock.
The concrete structure of described comparison module 121 can include various types of comparator or have comparing function
Processor, forms described comparative result.
Described recovery module 122 includes the structures such as crystal oscillator or the VCXO of generation recovered clock.
Described comparison module 121, including:
First output sub-module, by being more than based on the circulation of described local clock when the described water level controlling caching
During number, it is output as the adjustment signal of logic high；
Second output sub-module, by being less than based on the circulation of described local clock when the described water level controlling caching
During number, it is output as the adjustment signal of logic low；
Described recovery unit 120, specifically for according to logic high in described adjustment signal and logic low electricity
Flat ratio, determines the frequency of described recovered clock.
Comparison module 121 described in the present embodiment includes the first output sub-module and the second output sub-module, this
Two output modules are respectively used to logic high and logic low.Like this, described recovery module 122
The adjustment signal received from comparison module 121, is logic high time possible, time and be logic low.
Described recovery module 122, according to described adjustment signal, adjusts the frequency of its clock formed.
It should be noted that adjustment and recovery clock in this application, refer to the frequency of adjustment and recovery clock.
Additionally, described device also includes:
Statistic unit, the average writing rate of described data buffer storage in adding up the appointment time；Wherein, institute
State the water level of average writing rate and described data buffer storage for being collectively forming the described water level controlling caching.
Described statistic unit concrete structure can include the structures such as enumerator or the processor with tally function, can
To pass through writing data statistics of variables in the appointment time, thus write data buffer storage in evaluating the appointment time
Average writing rate.
By increasing statistic unit at clock recovery device in the present embodiment, it is possible to achieve quickly adjust described
The frequency of recovered clock, it is achieved the fast Acquisition of recovered clock.
Clock recovery device described in the present embodiment also includes smoothing processing unit.
Described smoothing processing unit, for carrying out the water level of described average writing rate and described data buffer storage
Smoothing processing, forms smoothing processing result, so that the write data volume of described data buffer storage is evenly distributed to respectively
The individual time period；
Described smoothing processing result is for forming the described water level controlling caching.The knot of described smoothing processing unit
Structure can include can forming the circuit of various control signal, processor or processing the structures such as chip.
Device described in the present embodiment passes through smoothing processing unit, it is possible to when avoiding recovering in clock recovery process
The phenomenon that clock frequency hopping is excessive.
Described recovery unit 120, is additionally operable to according to the described water level controlling caching, by adjusting described recovery
Clock writes out speed with the described data buffer storage of adjustment.
Described adjusting module can include clock-generating device, the most such as includes the various crystal oscillator that can form clock
Or the structure such as VCXO.What the recovered clock produced by adjustment can adjust described data buffer storage writes out speed,
It is thus possible to lower the water level of described data buffer storage and control the water level of caching.
Additionally, described recovery unit 120, it is additionally operable to when the described water level variable controlling caching is maintained at the
Time in one threshold range, detect the water level of described data buffer storage；The water level of described data buffer storage characterizes described number
According to data volume to be write out in caching；When outside the water level of described data buffer storage is positioned at Second Threshold scope, adjust
Speed is write out described in whole, so that in the range of the water level of described data buffer storage is in described Second Threshold.
The most described recovery unit 120 by the frequency of adjustment and recovery clock thus adjusts described number
Speed is write out according to caching, thus the purpose that the water level that reaches to control described data buffer storage is in a safe condition.
Below in conjunction with the scheme described in above-mentioned any embodiment, it is provided that a concrete example.
The flow chart utilizing clock recovery method described in the embodiment of the present application shown in Fig. 5.
Clock recovery method described in this example includes:
Data buffer storage carries out data sampling reception data according to write clock and carries out data write.When receiving one
During data, also can receive and be written with valid flag；Said write effective marker is input simultaneously to carry out data system
The statistic unit of meter carries out the write data statistics of variables in the appointment time.Intervalometer in figure is used for calculating
The described appointment time, described timing statistics can be M local clock cycles.
Statistical result N is formed after data statistics.This N is to determine according to the write data volume of timing statistics Ei
Unit interval in write described data buffer storage data volume, be i.e. equivalent to previous embodiment averagely writes speed
Rate.
Statistical result adjusts, and carries out described N according to the water level of the water level and data buffer storage that control caching and is adjusted to
Nadj。
Described Nadj is done smoothing processing, exports the effective mark of data.Before the effective flag of described data is
State smoothing processing result.
Control caching and receive write clock and the effective flag of described data；To said write clock and described number
Result after carrying out logical AND process according to flag carries out adding 1 operation.The water level so controlling caching is determined soon
Fixed and the write data volume of data buffer storage and write out data volume, also will be dependent on statistical result N.Control simultaneously
Caching also by receptions recovered clock with write out marker bit；Recovered clock and write out marker bit and carry out logical AND process
The result obtained afterwards shows that data buffer storage has write out data.Now, described control caching will do and subtract 1
Process.
Generate according to the water level controlling caching and adjust signal.Described adjustment signal includes logic high and logic
Low level；After low-pass filtering LPF processes, form one and control voltage.This control voltage can be used in
Control the frequency of the recovered clock that VCXO produces.
In several embodiments provided herein, it should be understood that disclosed equipment and method,
Can realize by another way.Apparatus embodiments described above is only schematically, such as,
The division of described unit, is only a kind of logic function and divides, and actual can have other division when realizing
Mode, such as: multiple unit or assembly can be in conjunction with, or are desirably integrated into another system, or some are special
Levy and can ignore, or do not perform.It addition, the coupling each other of shown or discussed each ingredient,
Or direct-coupling or communication connection can be the INDIRECT COUPLING by some interfaces, equipment or unit or logical
Letter connect, can be electrical, machinery or other form.
The above-mentioned unit illustrated as separating component can be or may not be physically separate, makees
The parts shown for unit can be or may not be physical location, i.e. may be located at a place,
Can also be distributed on multiple NE；Can select according to the actual needs therein partly or entirely
Unit realizes the purpose of the present embodiment scheme.
It addition, each functional unit in various embodiments of the present invention can be fully integrated into a processing module
In, it is also possible to it is that each unit is individually as a unit, it is also possible to two or more unit collection
Become in a unit；Above-mentioned integrated unit both can realize to use the form of hardware, it would however also be possible to employ
Hardware adds the form of SFU software functional unit and realizes.
One of ordinary skill in the art will appreciate that: realize all or part of step of said method embodiment
Can be completed by the hardware that programmed instruction is relevant, aforesaid program can be stored in a computer-readable
Taking in storage medium, this program upon execution, performs to include the step of said method embodiment；And it is aforementioned
Storage medium include: movable storage device, read only memory (ROM, Read-Only Memory),
Random access memory (RAM, Random Access Memory), magnetic disc or CD etc. are various
The medium of program code can be stored.
The above, the only detailed description of the invention of the present invention, but protection scope of the present invention is not limited to
In this, any those familiar with the art, can be easily in the technical scope that the invention discloses
Expect change or replace, all should contain within protection scope of the present invention.Therefore, the protection of the present invention
Scope should be as the criterion with described scope of the claims.
Claims (14)
1. a clock recovery method, it is characterised in that described method includes:
Read the water level controlling caching；The described water level of caching that controls is for characterizing the write data of data buffer storage
Measure and write out the difference of data volume；
According to the described water level controlling caching, form recovered clock.
Method the most according to claim 1, it is characterised in that
The described water level according to described control caching, forms recovered clock, including:
The cycle count of the described water level and local clock controlling caching is compared, forms comparative result；
The cycle count of described local clock is the described data buffer storage sampling period according to local clock write data
Cycle count；
According to described comparative result, form described recovered clock.
Method the most according to claim 2, it is characterised in that
The described cycle count by the described water level and local clock controlling caching compares, and is formed and compares knot
Really, including:
When the described water level controlling caching is more than the cycle count of described local clock, it is output as logic high electricity
Flat adjustment signal；
When the described water level controlling caching is less than the cycle count of described local clock, it is output as logic low electricity
Flat adjustment signal；
Described according to described comparative result, form recovered clock, including:
According to described adjustment signal, form described recovered clock.
4. according to the method described in any one of claims 1 to 3, it is characterised in that
Described method also includes:
The average writing rate of described data buffer storage in the statistics appointment time；
Wherein, the water level of described average writing rate and described data buffer storage is used for being collectively forming described control and delays
The water level deposited.
Method the most according to claim 4, it is characterised in that
Described method also includes:
The water level of described average writing rate and described data buffer storage is smoothed, forms smoothing processing
As a result, so that the write data volume of described data buffer storage is evenly distributed to each time period；
Described smoothing processing result is for forming the described water level controlling caching.
Method the most according to claim 5, it is characterised in that
Described method also includes:
According to the described water level controlling caching, by adjusting described recovered clock to adjust described data buffer storage
Write out speed.
Method the most according to claim 6, it is characterised in that
Described method also includes:
When the described water level variable controlling caching is maintained in the range of first threshold, detects described data and delay
The water level deposited；The water level of described data buffer storage characterizes data volume to be write out in described data buffer storage；
When the water level of described data buffer storage be positioned at Second Threshold scope outer time, by adjust described recovered clock with
Adjust described data buffer storage writes out speed, so that the water level of described data buffer storage is in described Second Threshold model
In enclosing.
8. a clock recovery device, it is characterised in that described device includes:
Read unit, for reading the water level controlling caching；The described water level controlling caching is used for characterizing data
The write data volume of caching and the difference writing out data volume；
Comparison module recovery unit, for the comparative result according to the described water level controlling caching, is formed and recovers
Clock.
Device the most according to claim 8, it is characterised in that
Described recovery unit also includes:
Comparison module, for the cycle count of the described water level and local clock controlling caching is compared,
Form comparative result；The cycle count of described local clock is that described data buffer storage writes number according to local clock
According to the cycle count in sampling period；
Recover module, specifically for according to described comparative result, form described recovered clock.
Device the most according to claim 9, it is characterised in that
Described comparison module, including:
First output sub-module, by being more than based on the circulation of described local clock when the described water level controlling caching
During number, it is output as the adjustment signal of logic high；
Second output sub-module, by being less than based on the circulation of described local clock when the described water level controlling caching
During number, it is output as the adjustment signal of logic low；
Described recovery module, specifically for according to logic high in described adjustment signal and logic low
Ratio, determines the frequency of described recovered clock.
11. according to Claim 8 to the device described in 10 any one, it is characterised in that
Described device also includes:
Statistic unit, the average writing rate of described data buffer storage in adding up the appointment time；
Wherein, the water level of described average writing rate and described data buffer storage is used for being collectively forming described control and delays
The water level deposited.
12. devices according to claim 11, it is characterised in that
Described recovery unit, for smoothing the water level of described average writing rate and described data buffer storage
Process, form smoothing processing result, during so that the write data volume of described data buffer storage is evenly distributed to each
Between section；
Described smoothing processing result is for forming the described water level controlling caching.
13. devices according to claim 12, it is characterised in that
Described recovery unit, for according to described control caching water level, by adjust described recovered clock with
Adjust described data buffer storage writes out speed.
14. devices according to claim 13, it is characterised in that
Described determine module, in the range of being maintained at first threshold when the described water level variable controlling caching
Time, detect the water level of described data buffer storage；The water level of described data buffer storage characterizes in described data buffer storage to be written
The data volume gone out；When outside the water level of described data buffer storage is positioned at Second Threshold scope, described extensive by adjusting
Multiple clock writes out speed with adjust described data buffer storage, so that the water level of described data buffer storage is in described the
In two threshold ranges.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510284136.4A CN106301746A (en) | 2015-05-28 | 2015-05-28 | Clock recovery method and device |
| PCT/CN2015/097061 WO2016188090A1 (en) | 2015-05-28 | 2015-12-10 | Clock recovery method and apparatus, and computer storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510284136.4A CN106301746A (en) | 2015-05-28 | 2015-05-28 | Clock recovery method and device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106301746A true CN106301746A (en) | 2017-01-04 |
Family
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510284136.4A Withdrawn CN106301746A (en) | 2015-05-28 | 2015-05-28 | Clock recovery method and device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN106301746A (en) |
| WO (1) | WO2016188090A1 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107272822A (en) * | 2017-06-16 | 2017-10-20 | 郑州云海信息技术有限公司 | A kind of system clock monitoring method and device |
| CN108964748A (en) * | 2018-08-21 | 2018-12-07 | 中国科学院空间应用工程与技术中心 | A kind of clock recovery method under maximum Doppler frequency shift |
| CN109286482A (en) * | 2017-07-19 | 2019-01-29 | 深圳市中兴微电子技术有限公司 | A kind of method and device for realizing clock recovery |
| CN110569203A (en) * | 2019-08-09 | 2019-12-13 | 华为技术有限公司 | input control method and device and storage equipment |
| CN112052204A (en) * | 2020-08-20 | 2020-12-08 | 浙江树人学院（浙江树人大学） | Non-homologous clock data transmission system |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114499728A (en) * | 2020-11-11 | 2022-05-13 | 迈普通信技术股份有限公司 | Associated clock jitter suppression method and device for E1 link and electronic equipment |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1543100A (en) * | 2003-04-30 | 2004-11-03 | 华为技术有限公司 | Method and apparatus for producing TDM service recovery clock |
| CN101072335A (en) * | 2007-06-07 | 2007-11-14 | 上海交通大学 | System clock feeding and recovering method for railway television single frequency network |
| CN101820324A (en) * | 2010-04-30 | 2010-09-01 | 中兴通讯股份有限公司 | Synchronous transmission method and system for asynchronous data |
| CN102013970A (en) * | 2010-12-23 | 2011-04-13 | 北京北方烽火科技有限公司 | Clock synchronization method and device thereof as well as base station clock device |
| CN102387369A (en) * | 2010-09-02 | 2012-03-21 | 瑞昱半导体股份有限公司 | Device for receiving signal and method for receiving clock signal |
| CN104486020A (en) * | 2014-12-12 | 2015-04-01 | 成都朗锐芯科技发展有限公司 | Network data counting method for clock recovery |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5563891A (en) * | 1995-09-05 | 1996-10-08 | Industrial Technology Research Institute | Waiting time jitter reduction by synchronizer stuffing threshold modulation |
| US7460629B2 (en) * | 2001-06-29 | 2008-12-02 | Agere Systems Inc. | Method and apparatus for frame-based buffer control in a communication system |
| CN101354878B (en) * | 2007-07-27 | 2010-11-03 | 瑞昱半导体股份有限公司 | Receiving apparatus and clock signal rate calibration method |
| CN104410483B (en) * | 2014-12-12 | 2017-06-09 | 成都朗锐芯科技发展有限公司 | One kind receives packet sequencing and invalid bag processing system |
-
2015
- 2015-05-28 CN CN201510284136.4A patent/CN106301746A/en not_active Withdrawn
- 2015-12-10 WO PCT/CN2015/097061 patent/WO2016188090A1/en active Application Filing
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1543100A (en) * | 2003-04-30 | 2004-11-03 | 华为技术有限公司 | Method and apparatus for producing TDM service recovery clock |
| CN101072335A (en) * | 2007-06-07 | 2007-11-14 | 上海交通大学 | System clock feeding and recovering method for railway television single frequency network |
| CN101820324A (en) * | 2010-04-30 | 2010-09-01 | 中兴通讯股份有限公司 | Synchronous transmission method and system for asynchronous data |
| CN102387369A (en) * | 2010-09-02 | 2012-03-21 | 瑞昱半导体股份有限公司 | Device for receiving signal and method for receiving clock signal |
| CN102013970A (en) * | 2010-12-23 | 2011-04-13 | 北京北方烽火科技有限公司 | Clock synchronization method and device thereof as well as base station clock device |
| CN104486020A (en) * | 2014-12-12 | 2015-04-01 | 成都朗锐芯科技发展有限公司 | Network data counting method for clock recovery |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107272822A (en) * | 2017-06-16 | 2017-10-20 | 郑州云海信息技术有限公司 | A kind of system clock monitoring method and device |
| CN109286482A (en) * | 2017-07-19 | 2019-01-29 | 深圳市中兴微电子技术有限公司 | A kind of method and device for realizing clock recovery |
| CN109286482B (en) * | 2017-07-19 | 2021-12-28 | 深圳市中兴微电子技术有限公司 | Method and device for realizing clock recovery |
| CN108964748A (en) * | 2018-08-21 | 2018-12-07 | 中国科学院空间应用工程与技术中心 | A kind of clock recovery method under maximum Doppler frequency shift |
| CN110569203A (en) * | 2019-08-09 | 2019-12-13 | 华为技术有限公司 | input control method and device and storage equipment |
| CN110569203B (en) * | 2019-08-09 | 2021-11-30 | 华为技术有限公司 | Input control method and device and storage equipment |
| CN112052204A (en) * | 2020-08-20 | 2020-12-08 | 浙江树人学院（浙江树人大学） | Non-homologous clock data transmission system |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2016188090A1 (en) | 2016-12-01 |
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