CN106289256A - Signal calculated processing system based on two CSTR Yu FPGA architecture - Google Patents
Signal calculated processing system based on two CSTR Yu FPGA architecture Download PDFInfo
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- CN106289256A CN106289256A CN201610590927.4A CN201610590927A CN106289256A CN 106289256 A CN106289256 A CN 106289256A CN 201610590927 A CN201610590927 A CN 201610590927A CN 106289256 A CN106289256 A CN 106289256A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
- G01C21/00—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00
- G01C21/20—Instruments for performing navigational calculations
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Abstract
The present invention discloses a kind of signal calculated processing system based on two CSTR Yu FPGA architecture, including: bottom circuit module, including angular velocity signal collecting unit, acceleration signal collecting unit, framing signal collecting unit, mileage signal collecting unit, elevation signal gathering unit, temperature signal collection unit, power conversion unit, CAN communication unit and RS422 communication unit；Signal pre-processing module；Navigation calculation module, including the first DSP unit and the second DSP unit.One aspect of the present invention arranges signal pre-processing module and the signal gathered is carried out pretreatment, on the other hand by the first DSP unit, the data signal of signal pre-processing module pretreatment carried out navigation operations, by the pretreatment of the data signal of the second DSP unit control signal pretreatment module and the transmission of communication signal, it carries out clarification in certain roles to signal processing, be conducive to improving processing speed and processing accuracy, it is ensured that the reliability of navigation operations.
Description
Technical field
The present invention relates to signal processing technology, especially relate at a kind of signal calculated based on two CSTR with FPGA architecture
Reason system.
Background technology
Initially, navigational computer use PC is as its core information processing platform, but has been rarely used now.Mesh
Before, using is PC/104 industrial computer assembly more widely, and it is embedding that the control bus standard of this industrial computer is that one aims at
Entering formula control and define, it has that volume is little, low in energy consumption, reliability is high and the remarkable advantage such as extensibility is strong, from the nineties
Just it is widely used the most always.
The domestic integrated navigation computer information processing platform also experienced by from PC to the development course of PC/104 assembly.
At present, PC/104 assembly is widely used in all kinds of engineering.But, due to PC/l04 assembly relevant interface to be carried out
Extension, and for microminiature navigation computer, its volume and size are also unsatisfactory for its requirement.In recent years, along with numeral
Signal processing technology and the fast development of FPGA Technology, utilizing DSP to carry out Design Navigation computer system becomes
Current study hotspot.
At present, navigational computer workload is big, and information processing capacity increases, and single dsp processor is difficult to meet mission requirements,
Systematic function also cannot all play.In this case, many dsp processors system is arisen at the historic moment, and it is good to present it
Application effect.And onboard combined navigation system needs data acquisition, inertial navigation calculating, data within a certain period of time to melt
The functions such as conjunction, fault detect, data communication, this requires that processor has the strongest calculating and processing capability in real time, its software and hardware
Platform selection is most important to whole system performance.Along with Integrated Navigation Algorithm complexity increases, Riming time of algorithm is caused to increase
Adding, data updating rate reduces, and existing signal processing system can not meet its needs.
Summary of the invention
It is an object of the invention to overcome above-mentioned technical deficiency, propose a kind of calculating letter based on two CSTR with FPGA architecture
Number processing system, solves that the conversion speed of navigation system in prior art is slow, processes time length, to process accuracy rate low
Technical problem.
For reaching above-mentioned technical purpose, technical scheme provides a kind of calculating based on two CSTR Yu FPGA architecture
Signal processing system, including,
Bottom circuit module, including the angular velocity signal for gathering gyroscope angular velocity signal collecting unit, for
Gather the acceleration signal collecting unit of the acceleration signal of accelerometer, for gathering the framing signal of the framing signal of GPS
Collecting unit, for gather speedometer mileage signal mileage signal collecting unit, for gathering the elevation signal of altimeter
Elevation signal gathering unit, for collecting temperature sensor temperature signal temperature signal collection unit, be used for changing confession
The power conversion unit of piezoelectric voltage and be used to carry out CAN communication unit and the RS422 of communication signal transmission with communicator
Communication unit；
Signal pre-processing module, for carrying out pretreatment to the data signal of bottom circuit module collection；
Navigation calculation module, it includes the first DSP unit and the second DSP unit, and described first DSP unit is for signal
The data signal of pretreatment module pretreatment carries out navigation operations, and described second DSP unit is used for control signal pretreatment module
The pretreatment of data signal, the transmission of communication signal and the first DSP unit navigation operations process.
Preferably, described signal pre-processing module include FPGA unit, A/D controlling of sampling unit, the first impulse scaler,
Second impulse scaler, crystal oscillator unit, described A/D controlling of sampling unit, the first impulse scaler, the second impulse scaler are homogeneous
End be connected with described FPGA unit, the other end respectively with temperature signal collection unit, acceleration signal collecting unit, mileage signal
Collecting unit connects, and described crystal oscillator unit is connected with described FPGA unit.
Preferably, described first DSP unit and the second DSP unit are connected by I2C communication unit.
Preferably, described angular velocity signal collecting unit include RS422 receptor that input is connected with gyroscope and
The first isolator that RS422 receptor outfan connects, the outfan of described first isolator and the pin of described FPGA unit
Connect.
Preferably, described acceleration collecting unit includes one second isolator, the input of described second isolator
Be connected with accelerometer, outfan and the first impulse scaler connect.
Preferably, described framing signal collecting unit includes RS232 receptor and the use of the location data for receiving GPS
The 3rd isolator in the pulse per second (PPS) data of the location data and GPS processing the reception of RS232 receptor.
Preferably, described mileage signal collecting unit includes one the 4th isolator, the input of described 4th isolator with
Speedometer connection, outfan and the second impulse scaler connect.
Preferably, described elevation signal gathering unit include MAX3232 receptor that an input is connected with altimeter and
One the 5th isolator being connected with the outfan of MAX3232 receptor, described 5th isolator is connected with described FPGA unit.
Preferably, described temperature signal collection unit includes an A/D change-over circuit, the input of A/D change-over circuit and temperature
Degree sensor connects, outfan is connected with A/D controlling of sampling unit.
Preferably, described CAN communication unit include level conversion transceiver that an input is connected with communicator and
One the 6th isolator being connected with level conversion transceiver outfan, described 6th isolator is mono-with FPGA unit and the 2nd DSP
Unit connects.
Compared with prior art, one aspect of the present invention arranges signal pre-processing module and the signal gathered is carried out pretreatment,
On the other hand by the first DSP unit, the data signal of signal pre-processing module pretreatment is carried out navigation operations, by second
The pretreatment of the data signal of DSP unit control signal pretreatment module and the transmission of communication signal, signal processing is carried out by it
Clarification in certain roles, is conducive to improving processing speed and processing accuracy, it is ensured that the reliability of navigation operations.
Accompanying drawing explanation
Fig. 1 is the connection block diagram based on two CSTR Yu the signal calculated processing system of FPGA architecture of the present invention；
Fig. 2 is the angular velocity signal acquisition process schematic diagram of the present invention；
Fig. 3 is the acceleration signal acquisition process schematic diagram of the present invention；
Fig. 4 is the framing signal acquisition process schematic diagram of the present invention；
Fig. 5 is the mileage signal acquisition process schematic diagram of the present invention；
Fig. 6 is the elevation signal acquisition process schematic diagram of the present invention；
Fig. 7 is that the temperature signal collection of the present invention processes schematic diagram；
Fig. 8 is that the CAN communication signal of the present invention processes schematic diagram.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, right
The present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, and
It is not used in the restriction present invention.
Please participate in Fig. 1, The embodiment provides a kind of signal calculated based on two CSTR with FPGA architecture and process system
System, including,
Bottom circuit module 1, including angular velocity signal collecting unit 11, the use of the angular velocity signal for gathering gyroscope
In the acceleration signal collecting unit 12 of the acceleration signal gathering accelerometer, for gathering the location of the framing signal of GPS
Signal gathering unit 13, for gather speedometer mileage signal mileage signal collecting unit 14, for gathering altimeter
The elevation signal gathering unit 15 of elevation signal, the temperature signal collection unit of temperature signal for collecting temperature sensor
16, for changing the power conversion unit 17 of supply voltage and being used to carry out the CAN of communication signal transmission with communicator
Communication unit 18 and RS422 communication unit 19；
Signal pre-processing module 2, carries out pretreatment for the data signal gathering bottom circuit module 1；
Navigation calculation module 3, it includes the first DSP unit 31 and the second DSP unit 32, and described first DSP unit 31 is used
In the data signal of signal pre-processing module 2 pretreatment carries out navigation operations, described second DSP unit 32 is for control signal
The navigation operations of the pretreatment of the data signal of pretreatment module 2, the transmission of communication signal and the first DSP unit 31 processes.
Concrete, bottom circuit module 1 be mainly used in gathering gyroscope in navigation system, accelerometer, GPS, speedometer,
The signal of the detection such as altimeter, temperature sensor, and with the transmission carrying out communication data of external communicator.Wherein, a DSP
Unit 31 uses TMS320C6713 type dsp chip, and it can perform integrated navigation filtering operation, and the second DSP unit 32 can use
TMS320F2808 type dsp chip, the transmission of pretreatment, the calculation process of the first DSP unit 31 and communication signal can be carried out by it
Controlling, it realizes the clarification in certain roles to signal processing, it is ensured that treatment effeciency.And the first DSP unit 31 and the second DSP unit 32
Can be communicatively coupled by its I2C communication unit carried.
Wherein, signal pre-processing module 2 described in the present embodiment includes FPGA unit 21, A/D controlling of sampling unit 22, first
Impulse scaler the 23, second impulse scaler 24, crystal oscillator unit 25, described A/D controlling of sampling unit the 22, first impulse scaler
23, second equal one end of impulse scaler 24 is connected with described FPGA unit 21, the other end respectively with temperature signal collection unit 16,
Acceleration signal collecting unit 12, mileage signal collecting unit 14 connect, and described crystal oscillator unit 25 is with described FPGA unit 21 even
Connect.
As shown in Figure 1 and Figure 2, described in the present embodiment, angular velocity signal collecting unit 11 includes that input is connected with gyroscope
The first isolator 112 of being connected with RS422 receptor 111 outfan of RS422 receptor 111, described first isolator 112
Outfan be connected with the pin of described FPGA unit 21.Concrete, gyroscope can be directly by interface and RS422 receptor
111 connect, and by interface, differential data signals is sent to RS422 receptor 111, and RS422 receptor 111 output voltage is
The single-ended Transistor-Transistor Logic level standard of VCC-0.3V to+0.3V；The single-ended signal of RS422 receptor 111 output is by the first isolator
112 carry out isolating, Schmidt's waveform shaping, and by the LVTTL level signal that signal voltage transitions is 0V to 3.3V, Jin Eryu
The interface level of the external pin of FPGA unit 21 matches；LVTTL level signal enters FPGA unit 21, FPGA unit 21 generation
Realize asynchronous serial data for special chip to receive, and on this basis, according to certain form packet is identified and
Verification, and therefrom extracted valid data, in the special RAM resource being stored in FPGA unit 21；Last by data processing core
First DSP unit 31 reads the valid data carried out required for navigation calculation from FPGA unit 21.
As shown in Figure 1, Figure 3, acceleration collecting unit 12 described in the present embodiment includes one second isolator 121, institute
The input stating the second isolator 121 is connected with accelerometer, outfan and the first impulse scaler 23 connect.Concrete, add
The pulse signal of velometer is entered the second isolator 121 by electrical connector interface, and by the second isolator 121 carry out electrically every
From, Schmidt's waveform shaping and the LVTTL level signal that pulse signal voltage transitions is 0V to 3.3V, the first impulse scaler
Positive and negative values two-way pulse is counted by 23 respectively according to the sampling interval set, and carries out difference operation also by FPGA unit 21
It is stored in the middle of the depositor of FPGA unit 21, then from FPGA unit, is read difference by the first DSP unit 31 and be used for navigating
Resolve.
As Figure 1 and Figure 4, framing signal collecting unit 13 described in the present embodiment includes the location data for receiving GPS
RS232 receptor 131 and for process RS232 receptor 131 receive location data and GPS pulse per second (PPS) data the 3rd
Isolator 132.Concrete, the output signal of GPS includes positioning data and pulse per second (PPS) data, and the location data of GPS output are passed through
RS232 receptor 131 enters, and carry out isolating through the 3rd isolator 132, level conversion and Schmidt's shaping, the 3rd isolation
The LVTTL level signal that device 132 exports after processing can be sent directly into FPGA unit 21 and carry out the identification of packet, extraction and school
Test, finally give the first DSP unit 31 and carry out data process.It addition, the pulse per second (PPS) data of GPS output are directly over the 3rd isolation
Device 132 carries out isolating, enter FPGA unit 21 after level conversion and Schmidt's shaping processes.
As shown in Figure 1, shown in Figure 5, mileage signal collecting unit 14 described in the present embodiment includes one the 4th isolator 141, described
The input of the 4th isolator 141 is connected with speedometer, outfan and the second impulse scaler 24 connect.The two of speedometer output
Road signal is DTUP+ and DTUP-, carries out isolating through the 4th isolator 141, Schmidt's waveform shaping be converted to LVTTL electricity
Ordinary mail number, then it is counted and verifies by FPGA unit 21, and stores in a register.Finally, the first DSP unit 31 from
Depositor reads related data and carries out navigation calculation.
As shown in Fig. 1, Fig. 6, elevation signal gathering unit 15 described in the present embodiment includes that an input is connected with altimeter
MAX3232 receptor 151 and the 5th isolator 152 being connected with the outfan of MAX3232 receptor 151, the described 5th
Isolator 152 is connected with described FPGA unit 21.Concrete, the signal of altimeter output is directly fed to MAX3232 receptor 151
And changed into Transistor-Transistor Logic level signal by it, carry out signal isolation, level conversion and Schmidt by the 5th isolator 152 the most again
Shaping, is converted into LVTTL level signal, send into afterwards FPGA unit 21 realize serial data communication and carry out identification of data packets and
Verification, is stored concurrently in the corresponding depositor of FPGA unit 21.Finally, the first DSP unit 31 takes out relevant from depositor
Data also carry out navigation calculation.
As shown in Figure 1, Figure 7 shows, temperature signal collection unit 16 described in the present embodiment includes an A/D change-over circuit 161, A/D
The input of change-over circuit 161 is connected with temperature sensor, outfan is connected with A/D controlling of sampling unit 22.Temperature sensor
Including temperature double-way circuit, amplifying circuit and filter circuit, temperature double-way circuit is responsible for external temperature signal is converted into correspondence
Voltage analog signal, this analogue signal is carried out at amplification and the filtering of certain multiple by amplifying circuit and filter circuit respectively
Reason, is converted into corresponding digital signal by A/D change-over circuit 161 afterwards, and the first DSP unit 31 is by FPGA unit 21
Bus control logic A/D controlling of sampling unit 22 gatherer process is controlled and data transmission, thus complete to temperature believe
Number collection.
As shown in Fig. 1, Fig. 8, CAN communication unit 18 described in the present embodiment includes what an input was connected with communicator
Level conversion transceiver 181 and the 6th isolator 182 being connected with level conversion transceiver 181 outfan, the described 6th every
It is connected with FPGA unit 21 and the second DSP unit 32 from device 182.Concrete, the CAN physical bus of CAN communication unit 18
Can be connected with PC by interface, the communication signal of PC is accessed level conversion transceiver 181, this level conversion transceiver 181 is CAN
Physical bus provides certain differential transmitting-receiving ability, and the CAN controller for CAN communication unit provides single-ended transmitting-receiving energy
Power, the receiving and transmitting signal of level conversion transceiver 181 output is carried out isolating by the 6th isolator 182, waveform shaping and level conversion,
Then by the second DSP unit 32, external data is done corresponding resolving to process.Wherein, level conversion transceiver 181 preferably employs
SN65HVD252 type transceiver.
Wherein, first isolator the 112, second isolator the 121, the 3rd isolator the 132, the 4th isolator in the present embodiment
141, the 5th isolator the 152, the 6th isolator 182 all uses ADUM1400 type isolator.
In on-board navigation computer system, altogether need five kinds of different power supplys, be respectively+5V ,+3.3V ,+1.2V ,+
1.8V and+2.5V, and external interface input power only has+5V one kind, therefore the present embodiment arranges power conversion unit 17 to outside
Input power is changed, to provide in signal calculated processing system power supply needed for different parts.Concrete, navigation calculation module
In power up, the i.e. first DSP unit and the second DSP unit are in power up, it should allow its internal core components and parts first
Powering on, power on after I/O interface, core component also to power on I/O interface simultaneously at the latest.The reason of requirement power supply order is:
If only CPU core obtains power supply, periphery I/O interface is not powered, and does not has any infringement to chip, simply do not input,
Output function.Otherwise, if periphery I/O interface obtains power supply, CPU core is not powered, then the buffering of chip/drive three poles
Pipe will be in unknown duty, and it is easily caused danger.For ensureing rational electric sequence, the enable of 3.3V power supply chip
End EN is controlled by 1.2V power supply chip.After 1.2V kernel power supply is stable, PWRGD pin becomes high level,
3DK103C type triode ON, enables 3.3V power supply chip, and around I/O interface just obtains power supply.
In Design of Navigation Computer, the signal processing logic functional module completed needed for FPGA unit 21 mainly has: (1)
Universal asynchronous serial interface UART logic functional block；(2) gyroscope, the identification of GPS protocol packet, verify and extract effectively
Data；(3) pulse signal of accelerometer, the synchronous counting of GPS second pulse data isopulse signal；(4) A/D change-over circuit
Control logical analysis；(5) clock division circuits logical design.
The core control portions of UART sending module uses finite state machine (FSM, Finite State Machines)
Realize, control the transmission process of data, make control clear logic, flexibly, design and debugging efficiency are greatly improved.
The pulse signal of accelerometer and GPS second pulse is the another kind of data signal that navigational computer is received.For
Pulse signal has two kinds of modes received: Asynchronous Reception mode and synchronize reception mode.In Asynchronous Reception mode, pulse signal is straight
Connect the triggering signal with enumerator to be connected.At the rising edge of pulse signal, enumerator carries out adding 1 counting, but this asynchronous counting
Mode is easy to by noise jamming.As in counting process, owing to by outside electromagnetic interference, counter trigger signal end occurs
Spiking, spiking rising edge meeting false triggering enumerator so that it is add 1 counting, thus cause final miscount.In order to keep away
Exempting from the problems referred to above occur, the present embodiment the first impulse scaler 23 and the second impulse scaler 24 all have employed impulsive synchronization and receive
Mode.
Book uses the core processor that two CSTR processes as data in time, and wherein the second DSP unit 32 is mainly used
In realizing control and correspondence with foreign country function, the first DSP unit 32 mainly performs combined filter algorithm.Lead between two pieces of dsp chips
Letter is mainly completed by self I2C unit, so can simplify hardware circuit design, it is ensured that communicate reliable and stable.
Wherein, the second DSP unit 32 uses TMS320F2808 type dsp chip, and RS422 communication unit 19 is main to outside
Signal carries out level conversion and isolation circuit, then arranges the asynchronous serial communication interface being arranged in parallel in FPGA unit 21
UART, CAN2.0 standard protocol interface and RS422 interface, asynchronous serial communication interface UART, CAN2.0 standard protocol interface and
The equal one end of RS422 interface is connected with isolation circuit, the other end and the second DSP unit 32 connect.Level conversion and isolation circuit are complete
Becoming the level conversion with external equipment interactive signal and isolation, CAN2.0 standard protocol interface realizes the second DSP unit 32 and passes through
CAN and the communication function of external equipment, RS422 interface realizes the second DSP unit 32 by 422 interfaces and external equipment
Communication function, UART interface realizes second DSP unit 32 communication function by RS232 interface with external equipment.
Compared with prior art, one aspect of the present invention arranges signal pre-processing module and the signal gathered is carried out pretreatment,
On the other hand by the first DSP unit, the data signal of signal pre-processing module pretreatment is carried out navigation operations, by second
The pretreatment of the data signal of DSP unit control signal pretreatment module and the transmission of communication signal, signal processing is carried out by it
Clarification in certain roles, is conducive to improving processing speed and processing accuracy, it is ensured that the reliability of navigation operations.
The detailed description of the invention of present invention described above, is not intended that limiting the scope of the present invention.Any basis
Various other that the technology design of the present invention is made change and deformation accordingly, should be included in the guarantor of the claims in the present invention
In the range of protecting.
Claims (10)
1. a signal calculated processing system based on two CSTR Yu FPGA architecture, it is characterised in that include,
Bottom circuit module, including the angular velocity signal collecting unit of the angular velocity signal for gathering gyroscope, for gathering
The acceleration signal collecting unit of the acceleration signal of accelerometer, for gathering the framing signal collection of the framing signal of GPS
Unit, for gather speedometer mileage signal mileage signal collecting unit, for gathering the height of the elevation signal of altimeter
Journey signal gathering unit, for collecting temperature sensor temperature signal temperature signal collection unit, be used for changing power supply electricity
The power conversion unit of pressure and be used to carry out CAN communication unit and the RS422 communication of communication signal transmission with communicator
Unit；
Signal pre-processing module, for carrying out pretreatment to the data signal of bottom circuit module collection；
Navigation calculation module, it includes the first DSP unit and the second DSP unit, and described first DSP unit is used for place pre-to signal
The data signal of reason module pretreatment carries out navigation operations, and described second DSP unit is for the number of control signal pretreatment module
The navigation operations of the pretreatment of the number of it is believed that, the transmission of communication signal and the first DSP unit processes.
Signal calculated processing system the most according to claim 1, it is characterised in that described signal pre-processing module includes
FPGA unit, A/D controlling of sampling unit, the first impulse scaler, the second impulse scaler, crystal oscillator unit, described A/D samples control
Unit processed, the first impulse scaler, second equal one end of impulse scaler are connected with described FPGA unit, the other end respectively with temperature
Signal gathering unit, acceleration signal collecting unit, mileage signal collecting unit connect, and described crystal oscillator unit is mono-with described FPGA
Unit connects.
Signal calculated processing system the most according to claim 2, it is characterised in that described first DSP unit and the 2nd DSP
Unit is connected by I2C communication unit.
4. according to the signal calculated processing system described in Claims 2 or 3, it is characterised in that described angular velocity signal gathers single
Unit includes the first isolator that the RS422 receptor that input is connected is connected with RS422 receptor outfan, institute with gyroscope
The pin of the outfan and described FPGA unit of stating the first isolator is connected.
Signal calculated processing system the most according to claim 4, it is characterised in that described acceleration collecting unit includes
Include one second isolator, the input of described second isolator is connected with accelerometer, outfan and the first impulse scaler even
Connect.
Signal calculated processing system the most according to claim 5, it is characterised in that described framing signal collecting unit includes
For receiving the RS232 receptor of the location data of GPS and for processing location data and the GPS that RS232 receptor receives
3rd isolator of pulse per second (PPS) data.
Signal calculated processing system the most according to claim 6, it is characterised in that described mileage signal collecting unit includes
One the 4th isolator, the input of described 4th isolator is connected with speedometer, outfan and the second impulse scaler connect.
Signal calculated processing system the most according to claim 7, it is characterised in that described elevation signal gathering unit includes
The 5th isolation that the MAX3232 receptor and that one input is connected with altimeter is connected with the outfan of MAX3232 receptor
Device, described 5th isolator is connected with described FPGA unit.
Signal calculated processing system the most according to claim 8, it is characterised in that described temperature signal collection unit includes
One A/D change-over circuit, the input of A/D change-over circuit is connected with temperature sensor, outfan connects with A/D controlling of sampling unit
Connect.
Signal calculated processing system the most according to claim 9, it is characterised in that described CAN communication unit includes
The 6th isolation that the level conversion transceiver and that one input is connected with communicator is connected with level conversion transceiver outfan
Device, described 6th isolator is connected with FPGA unit and the second DSP unit.
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| CN107817783A (en) * | 2017-10-23 | 2018-03-20 | 天津市英贝特航天科技有限公司 | Method and system for detecting recovery of output signal of rail transit |
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| CN113253639A (en) * | 2021-04-22 | 2021-08-13 | 深圳市天辰防务通信技术有限公司 | Navigation processor |
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| 滕飞: "双DSP结构的嵌入式系统设计及应用", 《中国优秀硕士学位论文全文数据库信息科技辑》 * |
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| CN107678349A (en) * | 2017-10-23 | 2018-02-09 | 天津市英贝特航天科技有限公司 | Rail transit signal acquisition system |
| CN107817783A (en) * | 2017-10-23 | 2018-03-20 | 天津市英贝特航天科技有限公司 | Method and system for detecting recovery of output signal of rail transit |
| CN107861417A (en) * | 2017-10-23 | 2018-03-30 | 天津市英贝特航天科技有限公司 | Rail transit output signal control system |
| CN109470244A (en) * | 2018-12-21 | 2019-03-15 | 中国船舶重工集团公司第七0七研究所 | Fiber strapdown inertial navigation system multi information synchronous and method based on FPGA |
| CN112925393A (en) * | 2021-03-11 | 2021-06-08 | 深圳市天辰防务通信技术有限公司 | Positioning and orienting controller |
| CN113253639A (en) * | 2021-04-22 | 2021-08-13 | 深圳市天辰防务通信技术有限公司 | Navigation processor |
| CN113483756A (en) * | 2021-07-13 | 2021-10-08 | 北京信息科技大学 | Data processing method and system, storage medium and electronic equipment |
| CN117553786A (en) * | 2024-01-04 | 2024-02-13 | 深圳市天辰防务通信技术有限公司 | Navigation device |
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