CN106230541B - A kind of Site synch system and method for Industrial Ethernet - Google Patents
A kind of Site synch system and method for Industrial Ethernet Download PDFInfo
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- CN106230541B CN106230541B CN201610642303.2A CN201610642303A CN106230541B CN 106230541 B CN106230541 B CN 106230541B CN 201610642303 A CN201610642303 A CN 201610642303A CN 106230541 B CN106230541 B CN 106230541B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/4026—Bus for use in automation systems
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- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a kind of Site synch system and methods for Industrial Ethernet, it can solve the problems, such as that the shake due to operating system and protocol stack causes the time inaccurate, pass through the Industrial Ethernet packet periodically given out a contract for a project and real time parsing receives, it eliminates processor and handles the process given out a contract for a project and unpacked, improve the processing capacity of whole system, solving the problems, such as the shake due to operating system and Software Protocol Stack causes processing capability in real time low, main website timing function can also be provided, the simultaneously operating between slave station is cooperateed with.The present invention includes：Clock counter is arranged in FPGA, and main website connects main control processor, and reference clock parameter is provided from clock counter to main website, and the reference clock parameter that main website is used to send by clock counter is synchronized into row clock；It is additionally operable to corresponding slave station tranmitting data register synchronous package；The clock synchronous package that the corresponding slave station of main website is used to be sent according to main website is synchronized into row clock.The present invention is controlled suitable for website.
Description
Technical field
The present invention relates to electronic information technical field more particularly to a kind of Site synch system for Industrial Ethernet and
Method.
Background technology
In currently used Ethernet auto-control technology (EtherCAT) scheme, reached using ASIC by slave station
When strong, and main website is then the soft solution based on high-performance CPU so that the minimal circulation week of system in the process of running
Phase is limited by CPU in master station, if cpu performance used by main website is not high enough or operating system real-time is insufficient, may result in it
Cycle period increases.
The many because being known as of operating system real-time are influenced, such as in the application based on current EtherCAT agreements,
Master station protocol needs constantly to obtain timer clock from operating system, since there are clock jitters to cause main website to open for operating system
The shake of time jitter, process cycle data and aperiodic data time that dynamic message is sent out.Main website is directly sent out by NIC
EtherCAT messages will cause data frame to send out the shake of time every time, to influence the real-time performance of master device.And
Due to the diversity of control device in system, in practical applications, whole system needs to integrate based on the industry under different agreement
Ethernet device is synchronized using the same main website based on the processing of cpu softwares, inevitably there is prodigious tremble at this time
It is dynamic so that the net synchronization capability between different agreement is very poor, it is difficult to meet the real-time performance of master device.
Invention content
The embodiment of the present invention provides a kind of Site synch system and method for Industrial Ethernet, can solve due to
The shake of operating system and protocol stack leads to the problem of time inaccuracy.
In order to achieve the above objectives, the embodiment of the present invention uses a kind of Site synch system for Industrial Ethernet, packet
It includes：Main control processor, FPGA, NIOS, clock counter, main website and the main website pair being connected by bus with the main control processor
The slave station answered, the NIOS are at least used for the calculating acceleration or described of the speed ring and position ring of the website control system
Main control processor carries out the calculating of speed ring and position ring for device；
The clock counter is arranged in the FPGA, and the main website passes through Avalon-MM (Avalon Memory
Map bus interface is the system bus standard for a set of completion that Altera is provided, and in FPGA products) interface connection institute
Main control processor is stated, reference clock parameter is provided from the clock counter to the main website, and the main website is used for by described
The reference clock parameter that clock counter is sent is synchronized into row clock；
The main website is connected by network interface with corresponding slave station, and the main website is used to send to the corresponding slave station of the main website
Too net frame, and the ethernet frame returned for parsing the corresponding slave station of the main website, the main website are additionally operable to corresponding slave station
Tranmitting data register synchronous package；
The clock synchronous package that the corresponding slave station of the main website is used to be sent according to the main website is into row clock synchronization.
Wherein, the main control processor includes ARM, and the main control processor is used for the initial configuration of each main website, and
For sending mailbox data, it is additionally operable to the carry out initialization operation to each slave station, and calculate the required director data of slave station,
The data of the control register of each slave station are by the main control processor read and write access.
And each main website is connected by network interface at least one corresponding slave station, each network interface is correspondingly connected with different watch
Equipment and/or I/O device are taken, specifically, there can be the network interface of part main website to be not connected to slave station, main website can be configured to close mould
Formula；Each network interface is used for transmission corresponding small data packets.
And the website control system, using at least one industrial ethernet protocol, different industrial ethernet protocols corresponds to
It is carried to different network interfaces；The reference clock of each industrial ethernet protocol is the clock count being arranged in the FPGA
Device.
In the website control system of the existing agreement based on EtherCAT, due to trembling for operating system and protocol stack
It moves, there are prodigious errors for timestamp of traditional main website on data frame, cause timestamp inaccurate.And first slave station makes
With ASIC, it is substantially not present and beats the problem of timestamp will appear shake, so beating timestamp on from first slave station toward data frame
It is relatively accurate；And all data that traditional main website is sent can all pass through first slave station, be forwarded to follow-up slave station again later,
To which the temporal information of first slave station is sent to follow-up all slave stations, therefore generally use first slave station as reference
Clock synchronizes follow-up all EtherCAT slave station clocks.Site synch system and method provided in an embodiment of the present invention, makes
The timer for using the time source and periodic data packet of clock counter as time service in FPGA to send, it is ensured that give out a contract for a project
Timestamp in time and data packet is accurate, solves in the prior art since the shake of operating system and protocol stack causes
The problem of timestamp inaccuracy.And the cycle period of periodic data is shortened, periodically give out a contract for a project and work that real time parsing receives
Industrial Ethernet packet, processor greatly improve the processing capacity of entire main station system, solve without being concerned about the process given out a contract for a project and unpacked
The problem for causing processing capability in real time low due to the shake of operating system and Software Protocol Stack, additionally it is possible to which main website time service work(is provided
Can, cooperate with the simultaneously operating between slave station.
Description of the drawings
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to needed in the embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1-3 is system architecture schematic diagram provided in an embodiment of the present invention；
Fig. 4 is the schematic diagram of the specific example distributed the task time of periodic data provided in an embodiment of the present invention；
Fig. 5 a are the flow diagram of the transmission control of main website provided in an embodiment of the present invention；
Fig. 5 b are the flow diagram of the reception control of main website provided in an embodiment of the present invention；
Fig. 6 is a kind of schematic diagram of the specific example of transmission timing provided in an embodiment of the present invention；
Fig. 7 is a kind of specific example of periodic data and aperiodicity data transmission collision provided in an embodiment of the present invention
Schematic diagram；
Fig. 8 is the schematic diagram that a kind of aperiodicity message provided in an embodiment of the present invention split transmission；
Fig. 9 is the flow diagram that a kind of periodic data provided in an embodiment of the present invention is sent；
Figure 10 is the flow diagram that a kind of aperiodicity data provided in an embodiment of the present invention are sent.
Specific implementation mode
To make those skilled in the art more fully understand technical scheme of the present invention, below in conjunction with the accompanying drawings and specific embodiment party
Present invention is further described in detail for formula.Embodiments of the present invention are described in more detail below, the embodiment is shown
Example is shown in the accompanying drawings, and in which the same or similar labels are throughly indicated same or similar element or has identical or class
Like the element of function.It is exemplary below with reference to the embodiment of attached drawing description, is only used for explaining the present invention, and cannot
It is construed to limitation of the present invention.Those skilled in the art of the present technique are appreciated that unless expressly stated, odd number shape used herein
Formula " one ", "one", " described " and "the" may also comprise plural form.It is to be further understood that the specification of the present invention
The middle wording " comprising " used refers to that there are the feature, integer, step, operation, element and/or component, but it is not excluded that
Other one or more features of presence or addition, integer, step, operation, element, component and/or their group.It should be understood that
When we say that an element is " connected " or " coupled " to another element, it can be directly connected or coupled to other elements, or
There may also be intermediary elements.In addition, " connection " used herein or " coupling " may include being wirelessly connected or coupling.Here make
Wording "and/or" includes any cell of one or more associated list items and all combines.The art
Technical staff is appreciated that unless otherwise defined all terms (including technical terms and scientific terms) used herein have
Meaning identical with the general understanding of the those of ordinary skill in fields of the present invention.It should also be understood that such as general
Term, which should be understood that, those of defined in dictionary has a meaning that is consistent with the meaning in the context of the prior art, and
Unless being defined as here, will not be explained with the meaning of idealization or too formal.
The embodiment of the present invention provides a kind of Site synch system for Industrial Ethernet, as shown in Figure 1, including：Master control
Processor, FPGA (Field-Programmable Gate Array, the scene being connected by bus with the main control processor
Programmable gate array), NIOS (it is a kind of using Harvard structure, the programmable soft core of the second generation on piece with 32 bit instruction collection at
Manage device), clock counter, the corresponding slave station of main website and main website, the NIOS at least be used for the website control system speed
The calculating of ring and position ring accelerates or the main control processor carries out the calculating of speed ring and position ring for device, and can be with
The treatment effeciency of system is improved by the acceleration function of NIOS.
In the present embodiment, the FPGA provided with multiple main websites is alternatively referred to as FPGA main websites, and slave station is referred to as
EtherCAT (Ethernet auto-control technology) slave station.Specifically, the clock counter of main website is used as with reference to clock and is used for
Equipment on synchronous all-network, such as EtherCAT/PowerLink；Main website is mainly used for the unpacking of giving out a contract for a project of data packet；Main website
Control register data by ARM (Advanced RISC Machine, advanced compacting instruction set processor) be written；It adopts
Multiaxis speed ring/position ring is carried out with the NIOS of FPGA calculate to accelerate, directly can also carry out speed ring and position ring with ARM
It calculates.To improve real-time and mitigate the burden of the sides ARM；FPGA timings, which generate, to be interrupted to NIOS and ARM, obtains hair next time later
The data of packet；Main website configurable period property transmission distribution clock synchronous package, especially the present embodiment are applied longer in servo period
Scene in；
The clock counter is arranged in the FPGA, as shown in Figure 2, the main website passes through Avalon-MM interfaces
The main control processor is connected, reference clock parameter is provided from the clock counter to the main website, and the main website is for leading to
The reference clock parameter that the clock counter is sent is crossed to synchronize into row clock.
It should be noted that the case where only using single network interface for FPGA main websites can in the concrete application of the present embodiment
To use main station time as the time is referred to, corresponding first slave station for supporting DC functions in a dc mode of main website can also be used
Time be used as refer to the time, recommend here main station time be used as refer to the time；And for FPGA main websites, there are Multi-netmouths
The case where, then the time of main website must be used to be used as and refer to the time.
In the present embodiment, the main website is connected by network interface with corresponding slave station, and the main website is used for the main website
Corresponding slave station sends too net frame, and the ethernet frame returned for parsing the corresponding slave station of the main website, and the main website also uses
In to corresponding slave station tranmitting data register synchronous package.The clock synchronization that the corresponding slave station of the main website is used to be sent according to the main website
It wraps and is synchronized into row clock.
In the present embodiment, ARM may be used in the main control processor, and the main control processor is for the first of each main website
Beginningization configures, and for sending mailbox data, is additionally operable to the carry out initialization operation to each slave station, and calculate the required of slave station
Director data, the data of the control register of each slave station are by the main control processor read and write access.Wherein, FPGA main websites match
It is set to the pattern of the fixed data packet of periodicity sending, ARM then configures corresponding periodical descriptor.
Specifically, frame head register may be used as the register in the present embodiment.Such as：According to Ethernet protocol,
Ethernet frame includes destination address, source address, frame type, data and FCS (Frame Check Sequence, frame check sequence
Row).In the present embodiment use frame head register as shown in Table 1, mainly include destination address, source address, frame type (such as：
EtherCAT is 0x88A4), Ethercat information devices.Destination address, source address, frame type only need initialization definitions one
It is secondary.
Table 1
Wherein it is possible to store the operation content of every a sub- message and the address of data storage by descriptor buffer
(the Descriptor buffer of similar DMA (Directional Memory Access, direct memory access)), descriptor is posted
Storage is as shown in table 2.In the present embodiment, the structure of periodical register and acyclic descriptor is substantially the same, and difference exists
A data frame is only corresponded in periodical descriptor, but aperiodic descriptor corresponds to multiple data frames.
Table 2
As shown in table 2, each descriptor corresponds to a sub- message, multiple descriptors from the description content of 0xN0-0xN0+10
It is stored in inside a RAM (Random-Access Memory, random access memory) and constitutes a descriptor buffer, often
Secondary ARM/NIOS is toward the corresponding descriptor of the sub- message of every of write-in inside descriptor Buffer, while FPGA parses these descriptions
Symbol, and the data write into slave will be needed to be read from WriteMemory Address and be organized into EtherCAT data frames hair
Toward slave station.It is parsed to start data then by the data frame real time parsing of return when data frame receives for parsing module
Journey, and the data parsed are written to the specified addresses Read Memory Address, to be realized by FPGA main websites
It unpacks in real time, the scheme just parsed after all being harvested relative to traditional data frame, the real-time of the present embodiment and flexibility are more
By force.
Wherein, for periodic transmission data, whether FPGA main websites have subsequent packet mark (M) according in descriptor
To determine to be inserted into FCS or continue to add subsequent packet.And for acyclic transmission data, FPGA main websites are according to descriptor
The sequence of the inside sends out data frame.
In the present embodiment, the calculating that the NIOS is at least used for the speed ring and position ring of the website control system adds
Speed or the main control processor carry out the calculating of speed ring and position ring for device.Specifically, FPGA main websites are in operational process
It is middle to generate different interruptions respectively to NIOS and ARM, periodic data is passed through after FPGA main websites complete the reception of data
The data that interrupt notification NIOS processing receives, after interruption is sent to NIOS, NIOS carries out the calculating of speed ring and position ring；It is right
The data received by interrupt notification ARM processing after aperiodicity data, the reception of FPGA main websites completion data.Meanwhile
FPGA main websites also send interrupt notification and give ARM processing in abnormal cases.In the present embodiment, the interrupt register in ARM
It is specific as shown in table 3
Table 3
In the present embodiment, excessive for the interstitial content of slave station in whole system, lead to that data packet is long, cycle period
The problem of becoming larger, using multiple network interface connections different servo or I/O device, to which the big data packet of data volume is resolved into not
It is sent out with the small data packets on network interface, the data volume of each network interface load is reduced, so as to shorten cycle period to improve system
Performance.Specific as shown in Figure 3, each main website is connected by network interface at least one corresponding slave station, each network interface pair
Different servosystems and/or I/O device should be connected；Specifically, can have the network interface of part main website to be not connected to slave station, main website can
To be configured to close pattern.Wherein, each network interface is used for transmission corresponding small data packets, the small data packets of corresponding each network interface by
The data packet that data volume is more than threshold value decomposes to obtain.
Further, as shown in figure 3, by multiple main websites of FPGA connections, each master device can be arranged one
A network interface, to which FPGA main websites have the framework of concurrent multiple network interfaces, to support the hot plug work(of Multi-netmouth redundancy and slave station
Energy.And multiple master devices therein are based on the same clock counter and are used as with reference to clock, row clock of going forward side by side synchronizes.And at this
In embodiment, different communication protocol can be respectively configured on multiple network interfaces, since the clock of the master device of each network interface is
Synchronous, it is achieved that the communication standard of multiple agreements simultaneously, is synchronously run.
In the present embodiment, the website control system is using at least one industrial ethernet protocol, different industry with
Too fidonetFido correspondence is carried to different network interfaces.Wherein, the reference clock of each industrial ethernet protocol is to be arranged described
The clock counter in FPGA.In the present embodiment, for the synchronization between different agreement, specifically by different industrial ether
FidonetFido corresponds on different network interfaces, and the reference clock of all agreements all uses the clock counter of FPGA main websites, makes
The slave stations of all agreements is all synchronized with the clock of main website, the clock between different agreement all by one accurately main website when
Clock realizes indirect synchronization, mixed dynamic between different agreement to realize.
In the website control system of the agreement based on EtherCAT, due to the shake of operating system and protocol stack, tradition
Main website timestamp is beaten on data frame there are prodigious error, cause timestamp inaccurate.And first slave station uses ASIC,
It is substantially not present and beats the problem of timestamp will appear shake, aligned so beating timestamp on from first slave station toward data frame
Really；And all data that traditional main website is sent can all pass through first slave station, be forwarded to follow-up slave station again later, thus will
The temporal information of first slave station is sent to follow-up all slave stations, therefore generally comes using first slave station as with reference to clock
Synchronize follow-up all EtherCAT slave station clocks.
And in the present embodiment, using FPGA as the main website under EtherCAT agreements, main website is given out a contract for a project and is unpacked etc. and patrolled
It collects and is hardened in FPGA, i.e., timing transmission data job contract work etc. is handled in FPGA, to which message hair be greatly decreased
Go out the shake of time.The clocks of all EtherCAT slave station equipments is all synchronized with master clock simultaneously, in this way it is also possible that
Almost synchronous between main website and slave station, the lock-out pulse shake between main website and slave station can be much smaller than 1us.And for FPGA
Main website, ARM are responsible for the flows such as initialization and the configuration of FPGA main websites, are responsible for sending mailbox data and the initialization to all slave stations
Operation.Wherein NIOS is responsible for speed ring and the calculating of position ring accelerates, to improve real-time.Greatly improve following for main website simultaneously
The performances such as ring period.So as to avoid the shake of traditional operating system and protocol stack, and the time of giving out a contract for a project is controllable and complete
It can measure entirely, to improve the accuracy of timestamp, avoid the shake in the prior art due to operating system and protocol stack
Lead to the problem of time inaccuracy.
The present embodiment also provides a kind of Site synch method for Industrial Ethernet, is specifically used for system, system tool
Body can refer in this implementation, website control system as shown in Figs. 1-3, including：At main control processor and the master control
FPGA, NIOS, clock counter, the corresponding slave station of main website and main website that device is connected by bus are managed, the NIOS is for described
The calculating of the speed ring and position ring of website control method accelerates.The clock counter is arranged in the FPGA, the master
It stands and the main control processor is connected by Avalon-MM interfaces.The main website is connected by network interface with corresponding slave station.
The method includes：
Reference clock parameter is obtained from the clock counter, and the reference clock parameter is issued to the main website,
And it controls the main website and is synchronized into row clock by the reference clock parameter that the clock counter is sent.
The main website is controlled again to corresponding slave station tranmitting data register synchronous package, and is controlled the main website and corresponded to the main website
Slave station send too net frame, and/or the control main website parses the ethernet frame that the corresponding slave station of the main website returns.
The corresponding slave station of the main website is controlled later to be synchronized into row clock according to the clock synchronous package that the main website is sent.
In the present embodiment, further include：It controls the main control processor and initial configuration is carried out to each main website, and send
Mailbox data.With to the carry out initialization operation of each slave station, and calculate the required director data of slave station, wherein the master
It includes ARM to control processor, and the data of the control register of each slave station are by the main control processor read and write access.
In the present embodiment, further include：The data packet that data volume is more than to threshold value is decomposed into the decimal of corresponding each network interface
According to packet.And pass through each network interface and transmit corresponding small data packets, wherein each main website by network interface with it is at least one corresponding
Slave station is connected, and each network interface is correspondingly connected with different servosystems and/or I/O device.
In the present embodiment, the data packet that data volume is more than to threshold value is decomposed into the small data packets of corresponding each network interface
Including：
According to the length of aperiodicity data, the sending time for detecting aperiodicity data and periodic data whether there is
Conflict.If exist conflict, first in the aperiodicity data and periodic data detected, screen and send there is no conflict
Data packet；And split the sub- message of aperiodicity data according to the message length that maximum is sent, and latent period
Data packet retransmits after distributing.Such as：The task time distribution of periodic data can be as shown in Figure 4, wherein upward arrow
Indicate that Interruption, Tcycle indicate cycle period.Since FPGA main websites transmit data to network according to EtherCAT agreements
On, need the data packet sent to be divided into periodic data and aperiodicity data, wherein the priority of periodic data is higher than
Aperiodicity data need to complete to send in window at the appointed time, and periodic data content can not be disassembled, and aperiodic
Property the not stringent timing requirements of data, only need to complete transmitting and receiving.
The periodicity of FPGA main websites in the present embodiment and acyclic transmission control, may be used as shown in Figure 5 a
Control logic, wherein data-moving logic is similar to dma controller, it is only necessary to by the data of designated position according to EtherCAT
Protocol packing is put into data frame, and FCS calculating logics are responsible for the calculating of the CRC32 of data frame, and the CRC32 of calculating is added to
Frame end.Sof generation modules then generate pulse signal at the time of Sof, and external logic can use this moment of sof signal latches
Timestamp is used for ARMW FRMW orders, is used for the calibration of synchronised clock.In a dc mode, FPGA main websites need to ensure
Data frame reaches slave station before SYNC, and transmission timing as shown in FIG. 6 may be used, wherein dotted arrow indicates main website hair
Data-frame times are sent, the dotted arrow with point indicates the SYNC times (or being synchronization time) of slave station.
Also, FPGA main websites according to PHY (physical layer) when the sides ordered pair PHY data received, and by the number of the sides PHY
Unpacking processing is carried out according to according to EtherCAT agreements.The block diagram of reception is as shown in Figure 5 b, wherein FPGA main websites need to check data frame
It is whether correct with FCS, and the data of return are write according to the content in descriptor by corresponding position.FPGA main websites need to pass through inspection
It looks into WKC (Working Count, job count) and judges slave station either with or without specified action is completed, if the WKC received and expection
WKC it is inconsistent, then need that ARM sides is notified to carry out respective handling.FPGA main websites can judge to be according to the Index for receiving data
Periodic data frame or aperiodicity data frame, frames of the Index less than 0x80 are periodic data frame, and Index is more than 0x80
Frame be aperiodicity data frame.
When an aperiodicity data frame request is sent, FPGA main websites are according to the required transmission of aperiodicity data frame
Time judges whether it with the transmission of periodic data frame has conflict.If time and week that the request of aperiodicity data frame is sent
The interval of the timed sending time of phase property data frame can not send first sub- message of aperiodicity data frame, then will be aperiodic
Property data frame transmission request be deferred to after periodic data is sent completely.If the time that the request of aperiodicity data frame is sent
The time interval sent with periodic data frame timing can complete the sub- message of one or more aperiodicity data frames still
It can not complete to send whole sub- messages, then need to send after being split aperiodicity data frame.Segmentation foundation is maximum
Can send sub- message time be less than aperiodicity data frame request send time and periodic data frame timing send when
Between be spaced.At the time of not enabled periodic data frame is sent, for example in initial phase, segmentation aperiodicity is not needed to
Data frame just needs to divide aperiodicity data frame only during periodic data is sent.If still having conflict after segmentation,
Then FPGA main websites needs report an error.Such as：The sequential of periodic data and aperiodicity data transmission collision is as shown in fig. 7, non-week
Phase property message split the sequential of transmission as shown in figure 8, in figures 7 and 8, solid box indicates periodic data frame, dotted line
Frame indicates aperiodicity data frame, shown in figure, is less than week when the most eldest son message of aperiodicity message sends required duration
When phase property data are sent to the interval time in next period, you can to avoid conflicting, reduction can be specifically taken in the present embodiment
The length of single sub- message, the length for reducing periodic data frame increase the scheme of cycle period to avoid conflicting.Alternatively,
The length of message or period can not also be modified in the present embodiment, but directly acquire the conflict time, and in conflict
Between other than at the time of send message, to avoid conflict the time.
By splitting after aperiodicity data avoid conflict, periodic data and aperiodicity data transmission flow are respectively such as
Shown in Fig. 9 and Figure 10.Further, aperiodic descriptor will be deleted after data frame correctly returns, and periodical descriptor will not
It is automatically deleted, the only sides ARM are modified.
Further, in the present embodiment, main website can be detected abnormal and be handled abnormal in real time, including：If
Data transmission collision, then main website, which is searched, sends the reason of conflicting, and contrasting data transmitting portion chapters and sections are solved；If data frame is lost
It loses, then main website notice ARM processing needs to retransmit under normal circumstances.If data frame exception or mistake, main website notice ARM
It is handled, needs to retransmit under normal circumstances；If WKC mistakes, main website notice ARM processing.
In the website control system of the existing agreement based on EtherCAT, due to trembling for operating system and protocol stack
Dynamic, timestamp is beaten on data frame by traditional main website, and there are prodigious errors, cause timestamp inaccurate.And first slave station makes
With ASIC, it is substantially not present and beats the problem of timestamp will appear shake, so beating timestamp on from first slave station toward data frame
It is relatively accurate；And all data that traditional main website is sent can all pass through first slave station, be forwarded to follow-up slave station again later,
To which the temporal information of first slave station is sent to follow-up all slave stations, therefore generally use first slave station as reference
Clock synchronizes follow-up all EtherCAT slave station clocks.Site synch system and method provided in an embodiment of the present invention, makes
The timer for using the time source and periodic data packet of clock counter as time service in FPGA to send, it is ensured that give out a contract for a project
Timestamp in time and data packet is accurate, solves in the prior art since the shake of operating system and protocol stack causes
The problem of timestamp inaccuracy.And the cycle period of periodic data is shortened, periodically give out a contract for a project and work that real time parsing receives
Industrial Ethernet packet, processor greatly improve the processing capacity of entire main station system, solve without being concerned about the process given out a contract for a project and unpacked
The problem for causing processing capability in real time low due to the shake of operating system and Software Protocol Stack, additionally it is possible to which main website time service work(is provided
Can, cooperate with the simultaneously operating between slave station.
Each embodiment in this specification is described in a progressive manner, identical similar portion between each embodiment
Point just to refer each other, and each embodiment focuses on the differences from other embodiments.Especially for equipment reality
For applying example, since it is substantially similar to the method embodiment, so describing fairly simple, related place is referring to embodiment of the method
Part explanation.The above description is merely a specific embodiment, but protection scope of the present invention is not limited to
This, any one skilled in the art in the technical scope disclosed by the present invention, the variation that can readily occur in or replaces
It changes, should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of claim
Subject to enclosing.
Claims (7)
1. a kind of Site synch system for Industrial Ethernet, which is characterized in that including：Main control processor and the master control
Processor is at least used by the connected FPGA, NIOS of bus, clock counter, the corresponding slave station of main website and main website, the NIOS
Accelerate in the calculating of the speed ring and position ring of the website control system or the main control processor is for carrying out speed ring
With the calculating of position ring；
The clock counter is arranged in the FPGA, and the main website connects the master control by Avalon-MM interfaces and handles
Device, reference clock parameter are provided from the clock counter to the main website, and the main website is used to pass through the clock counter
The reference clock parameter of transmission is synchronized into row clock；
The main website is connected by network interface with corresponding slave station, and the main website is used to send too net to the corresponding slave station of the main website
Frame, and the ethernet frame returned for parsing the corresponding slave station of the main website, the main website are additionally operable to send to corresponding slave station
Clock synchronous package；
The clock synchronous package that the corresponding slave station of the main website is used to be sent according to the main website is into row clock synchronization.
2. system according to claim 1, which is characterized in that the main control processor includes ARM, the main control processor
It for the initial configuration of each main website, and is used to send mailbox data, is additionally operable to the carry out initialization operation to each slave station,
And the required director data of slave station is calculated, the data of the control register of each slave station are read and write by the main control processor visits
It asks.
3. system according to claim 1, which is characterized in that each main website by network interface with it is at least one it is corresponding from
It stands and is connected, each network interface is correspondingly connected with different servosystems and/or I/O device；
Each network interface is used for transmission corresponding small data packets, wherein is decomposed into data volume more than the data packet of threshold value and corresponds to respectively
The small data packets of a network interface.
4. a kind of Site synch method for Industrial Ethernet, which is characterized in that the method is for a kind of website control system
System, the website control system include：Main control processor, the FPGA, NIOS being connected by bus with the main control processor, when
Clock counter, the corresponding slave station of main website and main website, speed rings and position ring of the NIOS for the website control method
It calculates；The clock counter is arranged in the FPGA, and the main website connects the master control by Avalon-MM interfaces and handles
Device；The main website is connected by network interface with corresponding slave station；
The method includes：
Reference clock parameter is obtained from the clock counter, and the reference clock parameter is issued to the main website, and is controlled
The main website is made to synchronize into row clock by the reference clock parameter that the clock counter is sent；
The main website is controlled to corresponding slave station tranmitting data register synchronous package, and controls the main website to the corresponding slave station of the main website
Too net frame is sent, and/or the control main website parses the ethernet frame that the corresponding slave station of the main website returns；
The corresponding slave station of the main website is controlled to be synchronized into row clock according to the clock synchronous package that the main website is sent.
5. according to the method described in claim 4, it is characterized in that, further including：
It controls the main control processor and initial configuration is carried out to each main website, and send mailbox data；
With to the carry out initialization operation of each slave station, and calculate the required director data of slave station, wherein at the master control
It includes ARM to manage device, and the data of the control register of each slave station are by the main control processor read and write access.
6. according to the method described in claim 4, it is characterized in that, further including：
The data packet that data volume is more than to threshold value is decomposed into the small data packets of corresponding each network interface；
Pass through each network interface and transmit corresponding small data packets, wherein each main website by network interface with it is at least one it is corresponding from
It stands and is connected, each network interface is correspondingly connected with different servosystems and/or I/O device.
7. according to the method described in claim 6, it is characterized in that, the data packet that data volume is more than to threshold value is decomposed into pair
The small data packets of each network interface are answered to include：
According to the length of aperiodicity data, the sending time of aperiodicity data and periodic data is detected with the presence or absence of punching
It is prominent；
If exist conflict, first in the aperiodicity data and periodic data detected, screen and send there is no conflict
Data packet；And split the sub- message of aperiodicity data according to the message length that maximum is sent, and latent period
Data packet retransmits after distributing.
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| CN109991887B (en) * | 2017-12-29 | 2021-08-31 | 沈阳高精数控智能技术股份有限公司 | Real-time optimization method of embedded real-time EtherCAT main station |
| CN110995613B (en) * | 2019-10-14 | 2023-06-27 | 广州虹科电子科技有限公司 | System and method for eliminating EtherCAT communication period jitter |
| CN111224864A (en) * | 2020-01-14 | 2020-06-02 | 平安国际智慧城市科技股份有限公司 | Message transmission method and device, computer equipment and storage medium |
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| JP2011124759A (en) * | 2009-12-10 | 2011-06-23 | Mitsubishi Electric Corp | Communication system, station-side communication device, and slave clock correction device |
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