CN106228944B - Level shift circuit and liquid crystal display panel - Google Patents

Level shift circuit and liquid crystal display panel Download PDF

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Publication number
CN106228944B
CN106228944B CN201610891410.9A CN201610891410A CN106228944B CN 106228944 B CN106228944 B CN 106228944B CN 201610891410 A CN201610891410 A CN 201610891410A CN 106228944 B CN106228944 B CN 106228944B
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signal
receiving
level shift
clock signal
module
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CN106228944A (en
Inventor
周娟
张先明
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TCL Huaxing Photoelectric Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3685Details of drivers for data electrodes
    • G09G3/3688Details of drivers for data electrodes suitable for active matrices only
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/0289Details of voltage level shifters arranged for use in a driving circuit

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

The present invention provides a kind of level shift circuit and liquid crystal display panel, and wherein level shift circuit includes: sequence controller, for exporting the logical signal for controlling driving circuit;Level shift chip is electrically connected with sequence controller, comprising: receiving module is electrically connected, for receiving logical signal with timing control;Judgment module, whether the reception timing for decision logic signal is correct, such as correct, then sends output signal, such as mistake, then send shutdown signal;Output module, for when receiving output signal, output logic signal, to control driving circuit;Closedown module, for closing level shift chip when receiving shutdown signal.Level shift circuit and liquid crystal display panel of the invention effectively prevents liquid crystal display panel and is destroyed, improve the safety of liquid crystal display panel by closing level shift chip in the reception timing error of logical signal.

Description

Level shift circuit and liquid crystal display panel
Technical field
The present invention relates to field of display technology, more particularly to a kind of level shift circuit and liquid crystal display panel.
Background technique
Currently, taking the liquid crystal display of GOA (Gate Driver onArray, the driving of array substrate row) framework becomes Most common display device.
GOA framework in the array substrate of liquid crystal display panel, needs gate switch circuit integration using film crystal Pipe (Thin Film Transistor, TFT) prepares gate drivers on the glass substrate, it is therefore desirable to pass through level shift (Level Shifter, LS) circuit converts the signal that sequence controller (TCON) exports, to drive in liquid crystal display panel TFT work.Wherein, when TCON is driving circuit (Source drive, gate driver and the control of VCOM polarity) offer on liquid crystal display Sequence control signal, to realize the display control of analog rgb signal.
In order to work normally driving circuit, TCON is needed to generate correct clock signal, once otherwise LS circuit receives To the signal of timing error, it will cause liquid crystal display picture exception and electric current excessive, even result in TFT damage.
Summary of the invention
The purpose of the present invention is to provide a kind of level shiftings for keeping liquid crystal display panel picture, electric current stable and highly-safe Position circuit and liquid crystal display panel, to solve the technical problem that existing picture is abnormal, electric current is excessive and safety is lower.
The embodiment of the present invention provides a kind of level shift circuit comprising:
Sequence controller, for exporting the logical signal for controlling driving circuit;
Level shift chip is electrically connected with the sequence controller, comprising:
Receiving module is electrically connected, for receiving the logical signal with the timing control;
Judgment module, whether the reception timing for judging the logical signal is correct, such as correct, then sends output letter Number, such as mistake, then send shutdown signal;
Output module, for when receiving the output signal, exporting the logical signal, to control driving circuit;
Closedown module, for when receiving the shutdown signal, closing the level shift chip.
In level shift circuit of the present invention, the logical signal includes multiple clock signals, the reception mould Block includes:
Multiple clock signal receiving units are respectively used to receive the multiple clock signal;
The judgment module is specifically used for judging whether just adjacent clock signal receiving unit receives the timing of clock signal Really, as correctly, then sent output signal, such as mistake, then sending shutdown signal.
In level shift circuit of the present invention, the closedown module is specifically used for receiving the shutdown signal When, the multiple clock signal is converted into high level clock signal, or be converted into low level clock signal, to close the electricity Translational shifting chip.
In level shift circuit of the present invention, the logical signal includes grid enabling signal, the receiving module Include:
Grid enabling signal receiving unit, for receiving the grid enabling signal;
The judgment module is specifically used for judging whether the reception timing of the grid enabling signal is correct, such as correct, then sends out Output signal, such as mistake are sent, then sends shutdown signal.
In level shift circuit of the present invention, the logical signal further includes multiple clock signals, the closing Module is specifically used for when receiving the shutdown signal, and the multiple clock signal is converted into high level clock signal, or It is converted into low level clock signal, to close the level shift chip.
In level shift circuit of the present invention, the output module includes:
Converting unit, for when receiving the output signal, the logical signal to be converted into high voltage logic letter Number;
Output unit exports the high voltage logic signal, to control driving circuit.
The embodiment of the present invention also provides a kind of liquid crystal display panel comprising level shift circuit and driving circuit;
Wherein, the level shift circuit includes:
Sequence controller, for exporting the logical signal for controlling driving circuit;
Level shift chip is electrically connected with the sequence controller, comprising:
Receiving module is electrically connected, for receiving the logical signal with the timing control;
Judgment module, whether the reception timing for judging the logical signal is correct, such as correct, then sends output letter Number, such as mistake, then send shutdown signal;
Output module, for when receiving the output signal, exporting the logical signal, to control driving circuit;
Closedown module, for when receiving the shutdown signal, closing the level shift chip.
In liquid crystal display panel of the present invention, the logical signal includes multiple clock signals, the receiving module Include:
Multiple clock signal receiving units are respectively used to receive the multiple clock signal;
The judgment module is specifically used for judging whether just adjacent clock signal receiving unit receives the timing of clock signal Really, as correctly, then sent output signal, such as mistake, then sending shutdown signal.
In liquid crystal display panel of the present invention, the closedown module is specifically used for receiving the shutdown signal When, the multiple clock signal is converted into high level clock signal, or be converted into low level clock signal, to close the electricity Translational shifting chip.
In liquid crystal display panel of the present invention, the logical signal includes grid enabling signal, the receiving module packet It includes:
Grid enabling signal receiving unit, for receiving the grid enabling signal;
The judgment module is specifically used for judging whether the reception timing of the grid enabling signal is correct, such as correct, then sends out Output signal, such as mistake are sent, then sends shutdown signal.
Compared to existing level shift circuit and liquid crystal display panel, level shift circuit of the invention and liquid crystal display Panel is by setting receiving module, judgment module, output module and closedown module, when the reception timing of logical signal is correct, The logical signal is exported, to control driving circuit;In the reception timing error of logical signal, level shift chip is closed. Cause liquid crystal display panel picture exception, electric current excessive so as to avoid the logical signal of wrong timing, or even causes liquid crystal The case where showing panel breakage;Solves the technical problem that existing picture is abnormal, electric current is excessive and safety is lower.
For above content of the invention can be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate institute's accompanying drawings, makees Detailed description are as follows:
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the first preferred embodiment of level shift circuit of the invention;
Fig. 2 is that the clock signal of level shift circuit of the invention receives timing diagram;
Fig. 3 is the structural schematic diagram of the second preferred embodiment of level shift circuit of the invention;
Fig. 4 is that the grid enabling signal of level shift circuit of the invention receives timing diagram.
Specific embodiment
The explanation of following embodiment is to can be used to the particular implementation of implementation to illustrate the present invention with reference to additional schema Example.The direction term that the present invention is previously mentioned, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outside", " side " Deng being only the direction with reference to annexed drawings.Therefore, the direction term used be to illustrate and understand the present invention, rather than to The limitation present invention.
The similar unit of structure is to be given the same reference numerals in the figure.
Fig. 1 is please referred to, Fig. 1 is the structural schematic diagram of the first preferred embodiment of level shift circuit of the invention.This is excellent The level shift circuit of embodiment is selected for the output by control logic signal to control corresponding driving circuit, originally The level shift circuit 1 of preferred embodiment includes sequence controller 2 and level shift chip 3.Wherein, sequence controller 2 are used out In the logical signal of control driving circuit;Level shift chip 3 and sequence controller 2 are electrically connected, including receiving module 31, are sentenced Disconnected module 32, output module 33 and closedown module 34.
Receiving module 31 is electrically connected, for receiving logical signal with timing control;Judgment module 32 is patrolled for judging Whether the reception timing for collecting signal is correct, such as correct, then sends output signal, such as mistake, then send shutdown signal;Output module 33, for when receiving output signal, output logic signal, to control driving circuit;Closedown module 34, for receiving When shutdown signal, level shift chip is closed.
When logical signal includes multiple clock signals, receiving module 31 includes clock signal receiving unit 311, the clock Signal receiving unit 311 includes the first clock signal receiving unit, second clock signal receiving unit ..., N clock signal Receiving unit, these clock signal receiving units are respectively used to receive multiple clock signals.
Output module 33 includes converting unit 331 and output unit 332, wherein converting unit 331, for receive it is defeated Out when signal, logical signal is converted into high voltage logic signal;Output unit 332, output HIGH voltage logical signal, with control Driving circuit.
The level shift circuit 1 of this preferred embodiment is in use, 2 output logic signal of sequence controller first, with control Driving circuit (Source drive, gate driver and the control of VCOM polarity) on liquid crystal display panel, to realize analog rgb signal Display control.
Wherein, logical signal specifically includes STH (row data commencing signal) for controlling Source drive, MPOL (data Reverse signal at once), the signals such as STV (grid enabling signal), CPV (grid movable signal) for controlling gate driver.These are patrolled The output for collecting signal all has certain timing requirements, wherein if timing mistake has occurred in the output of STV and CLK (clock signal) Accidentally, it will cause that liquid crystal display panel electric current is excessive, picture output abnormality, even result in the TFT damage of LCD display intralamellar part.
Simultaneously because the logical signal that sequence controller 2 exports is low voltage logic signal, it cannot be directly to LCD display Driving circuit on plate is controlled, it is therefore desirable to low voltage logic signal are converted into high pressure logic by level shift circuit 3 Signal is just able to achieve the control to driving circuit.
Then, level shift chip 3 receives the logical signal for the low-voltage that sequence controller 2 exports, by patrolling for low-voltage Collect the logical signal that signal is converted into high voltage.Liquid crystal display panel is because of 2 output error timing of sequence controller in order to prevent STV and CLK and be damaged, level shift circuit 3 be provided with receiving module 31, judgment module 32, output module 33 and close Otherwise module 34, the ability output logic signal when determining that STV and CLK output timing is correct are closed level shift chip, are forbidden defeated Logical signal out.
Specifically, receiving module 31 receives the logical signal that sequence controller 2 exports first, wherein receiving module 31 includes Clock signal receiving unit 311, the clock signal receiving unit 311 include the first clock signal receiving unit, second clock letter Number receiving unit ..., N clock signal receiving unit, these clock signal receiving units are respectively used to receive multiple clocks letters Number, such as the first clock signal receiving unit receives the first clock signal clk IN1N clock signal receiving unit receives N clock Signal CLKINn.Then judgment module 32 judges whether the timing of adjacent clock signal receiving unit reception clock signal is correct, As correct, then send and output signal to output module 33, such as mistake, then send shutdown signal to closedown module 34.
Specifically, referring to figure 2., it is assumed that the first clock signal receiving unit receives CLKIN1It is received with second clock signal Unit receives CLKIN2Time interval be Δ t1, second clock signal receiving unit reception CLKIN2And CLKIN3Time between It is divided into Δ t2, judgment module 32 is by judging Δ t1With Δ t2Between difference whether be within the scope of preset difference value come when determining Whether clock signal sequence is correct, if be not within the scope of preset difference value, determines clock signal timing error, sends and close letter Number give closedown module 34;If determining that clock signal timing is correct within the scope of preset difference value, transmission outputs signal to defeated Module 33 out.
After output module 33 receives output signal, in converting unit 331 patrolled what receiving module 31 received It collects signal and is converted into high voltage logic signal;Then it is exported by output unit 332 to driving circuit, to control driving circuit.
After closedown module 34 receives shutdown signal, by the received multiple clock signals of clock signal receiving unit 311 It is wholly converted into high level clock signal, or is wholly converted into low level clock signal, closes level shift core to reach The purpose of piece 3, to prevent the logical signal of wrong timing from damaging to liquid crystal display panel.
The level shift circuit of this preferred embodiment is by setting receiving module, judgment module, output module and closes mould Block, when the reception timing of logical signal is correct, output logic signal, to control driving circuit;In the reception of logical signal When sequence mistake, level shift chip is closed, causes liquid crystal display panel picture different so as to avoid the logical signal of wrong timing Often, electric current is excessive, and the case where damage, improves the safety of liquid crystal display panel.
Referring to figure 3., Fig. 3 is the structural schematic diagram of the second preferred embodiment of level shift circuit of the invention.This is excellent The level shift circuit 1 for selecting embodiment includes sequence controller 2 and level shift chip 3.Wherein, sequence controller 2 are used for out Control the logical signal of driving circuit;Level shift chip 3 and sequence controller 2 are electrically connected, including receiving module 31, judgement Module 32, output module 33 and closedown module 34.
On the basis of first preferred embodiment, the receiving module 31 of this preferred embodiment further includes that grid enabling signal receives Unit 312.The grid enabling signal receiving unit 312 is used for receiving grid enabling signal STVIN.
The level shift circuit 1 of this preferred embodiment in use, after 2 output logic signal of sequence controller, believe by grid starting Number receiving unit 312 receives the grid enabling signal in logical signal;Then judgment module 32 judges grid enabling signal receiving unit Whether the timing of 312 reception clock signals is correct, such as correct, then sends and output signal to output module 33, such as mistake, then send Shutdown signal is to closedown module 34.
Specifically, referring to figure 4., it is assumed that grid enabling signal receiving unit 312 receives the time interval of two adjacent S TVIN For Δ t3, judgment module 32 is by calculating Δ t3With a reference value Δ t4Difference DELTA t, and judge whether Δ t is greater than preset threshold, Whether the reception timing to determine STVIN is correct.If it is greater than preset threshold, then determines that STVIN receives timing error, send and close Signal is closed to closedown module 34;Such as it is not more than preset threshold, then judges that STVIN reception timing is correct, transmission outputs signal to defeated Module 33 out.
After output module 33 receives output signal, in converting unit 331 patrolled what receiving module 31 received It collects signal and is converted into high voltage logic signal;Then it is exported by output unit 332 to driving circuit, to control driving circuit.
After closedown module 34 receives shutdown signal, by the received multiple clock signals of clock signal receiving unit 311 It is wholly converted into high level clock signal, or is wholly converted into low level clock signal, closes level shift core to reach The purpose of piece 3, to prevent the logical signal of wrong timing from damaging to liquid crystal display panel.
The first of the concrete operating principle of the sequence controller of this preferred embodiment and above-mentioned level shift circuit is preferably The concrete operating principle of sequence controller described in embodiment is same or similar, specifically refers to above-mentioned level shift circuit Associated description in first preferred embodiment.
The present invention also provides a kind of liquid crystal display panels comprising level shift circuit and driving circuit;Wherein, level moves Position circuit includes sequence controller and level shift chip.
Sequence controller, for exporting the logical signal for controlling driving circuit;Level shift chip, with timing control Device is electrically connected.Wherein level shift chip includes receiving module, judgment module, output module and closedown module.
Receiving module is electrically connected, for receiving logical signal with timing control;Judgment module is believed for decision logic Number reception timing it is whether correct, it is such as correct, then send output signal, such as mistake, then send shutdown signal;Output module is used In when receiving output signal, output logic signal, to control driving circuit;Closedown module, for receiving closing letter Number when, close level shift chip.
Preferably, logical signal includes multiple clock signals, and receiving module includes multiple signal receiving units, is specifically described It is as follows:
Multiple clock signal receiving units are respectively used to receive multiple clock signals;
Judgment module is specifically used for judging whether the timing of adjacent clock signal receiving unit reception clock signal is correct, such as Correctly, then output signal, such as mistake are sent, then sends shutdown signal.
Preferably, closedown module is specifically used for when receiving shutdown signal, and multiple clock signals are converted into high level Clock signal, or it is converted into low level clock signal, to close level shift chip.
Preferably, logical signal includes grid enabling signal, and receiving module includes grid enabling signal receiving unit, is specifically described It is as follows:
Grid enabling signal receiving unit is used for receiving grid enabling signal;
Judgment module is specifically used for judging whether the reception timing of grid enabling signal is correct, such as correct, then sends output letter Number, such as mistake, then send shutdown signal.
In the concrete operating principle of liquid crystal display panel of the invention and the preferred embodiment of above-mentioned level shift circuit Description it is same or similar, specifically refer to the associated description in the preferred embodiment of above-mentioned level shift circuit.
Level shift circuit and liquid crystal display panel of the invention passes through setting receiving module, judgment module, output module And closedown module, when the reception timing of logical signal is correct, output logic signal, to control driving circuit;In logical signal Reception timing error when, close level shift chip.Logical signal so as to avoid mistake causes liquid crystal display panel to be drawn Face is abnormal, electric current is excessive, or even the case where cause liquid crystal display panel to damage, improves the safety of liquid crystal display panel;Solution It has determined the technical problem that existing picture is abnormal, electric current is excessive and safety is lower.
In conclusion although the present invention has been disclosed above in the preferred embodiment, but above preferred embodiment is not to limit The system present invention, those skilled in the art can make various changes and profit without departing from the spirit and scope of the present invention Decorations, therefore protection scope of the present invention subjects to the scope of the claims.

Claims (5)

1. a kind of level shift circuit characterized by comprising
Sequence controller, for exporting the logical signal for controlling driving circuit, the logical signal includes multiple clock letters Number, grid enabling signal;
Level shift chip is electrically connected with the sequence controller, comprising:
Receiving module is electrically connected with the sequence controller, and the receiving module includes multiple clock signal receiving units, The multiple clock signal receiving unit is respectively used to receive the clock signal, and the receiving module includes that grid enabling signal connects Unit is received, for receiving the grid enabling signal;
Judgment module, for judging whether the difference between adjacent time inter is within the scope of preset difference value, wherein when described Between between be divided into the time interval that corresponding adjacent clock signal receiving unit receives clock signal, as within the scope of preset difference value, Then determine that clock signal timing is correct, sends output signal, be such as not within the scope of preset difference value, then determine clock signal timing Mistake sends shutdown signal;Or
The judgment module was used to judge between the time that the grid enabling signal receiving unit receives two adjacent gate enabling signals Difference between a reference value, if be greater than preset threshold, be such as not more than preset threshold, then determining grid enabling signal timing just Really, output signal, such as larger than preset threshold are sent, then determines grid enabling signal timing error, sends shutdown signal;
Output module, for when receiving the output signal, exporting the logical signal, to control driving circuit;
Closedown module, for when receiving the shutdown signal, closing the level shift chip.
2. level shift circuit according to claim 1, which is characterized in that the closedown module is specifically used for receiving When the shutdown signal, the multiple clock signal is converted into high level clock signal, or be converted into low level clock signal, To close the level shift chip.
3. level shift circuit according to claim 1, which is characterized in that the output module includes:
Converting unit, for when receiving the output signal, the logical signal to be converted into high voltage logic signal;
Output unit exports the high voltage logic signal, to control driving circuit.
4. a kind of liquid crystal display panel characterized by comprising level shift circuit and driving circuit;
Wherein, the level shift circuit includes:
Sequence controller, for exporting the logical signal for controlling driving circuit, the logical signal includes multiple clock letters Number, grid enabling signal;
Level shift chip is electrically connected with the sequence controller, comprising:
Receiving module is electrically connected with the sequence controller, and the receiving module includes multiple clock signal receiving units, The multiple clock signal receiving unit is respectively used to receive the clock signal, and the receiving module includes that grid enabling signal connects Unit is received, for receiving the grid enabling signal;
Judgment module, for judging whether the difference between adjacent time inter is within the scope of preset difference value, wherein when described Between between be divided into the time interval that corresponding adjacent clock signal receiving unit receives clock signal, as within the scope of preset difference value, Then determine that clock signal timing is correct, sends output signal, be such as not within the scope of preset difference value, then determine clock signal timing Mistake sends shutdown signal;Or
The judgment module was used to judge between the time that the grid enabling signal receiving unit receives two adjacent gate enabling signals Difference between a reference value, if be greater than preset threshold, be such as not more than preset threshold, then determining grid enabling signal timing just Really, output signal, such as larger than preset threshold are sent, then determines grid enabling signal timing error, sends shutdown signal;
Output module, for when receiving the output signal, exporting the logical signal, to control driving circuit;
Closedown module, for when receiving the shutdown signal, closing the level shift chip.
5. liquid crystal display panel according to claim 4, which is characterized in that the closedown module is specifically used for receiving When the shutdown signal, the multiple clock signal is converted into high level clock signal, or be converted into low level clock signal, To close the level shift chip.
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CN107424578A (en) * 2017-08-15 2017-12-01 京东方科技集团股份有限公司 A kind of drive circuit, display panel, display device and its control method
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