CN106206333A - A kind of fan-out-type wafer-level packaging method - Google Patents
A kind of fan-out-type wafer-level packaging method Download PDFInfo
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- CN106206333A CN106206333A CN201610654528.XA CN201610654528A CN106206333A CN 106206333 A CN106206333 A CN 106206333A CN 201610654528 A CN201610654528 A CN 201610654528A CN 106206333 A CN106206333 A CN 106206333A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/43—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The present invention provides a kind of fan-out-type wafer-level packaging method, including: form releasing layer at a carrier surface；Groove is offered at the carrier surface being formed with releasing layer；Bare chip face down being put in described groove, make being partly embedded in described groove of described bare chip, the back side protrudes from described carrier surface；Form molding compound at the carrier surface being embedded with described bare chip, make described molding compound wrap up described bare chip and protrude from the part of described carrier surface；Remove described releasing layer, make described bare chip separate with described carrier, expose the front of described bare chip；And form again wiring layer and metal coupling is installed.The present invention utilizes the screens effect of groove to fix bare chip, it is to avoid or decrease the displacement of bare chip in encapsulation process, and make packaging part can have narrower device bonding pad gap and higher input and output number；And product yield and yield can be improved, reduce again live width and the line gap of wiring layer, reduce package dimension, reduce cost.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, particularly relate to a kind of fan-out-type wafer-level packaging method.
Background technology
Owing to the terminal units such as smart mobile phone are increasingly faster to the development of compactization, it is specifically designed in miniaturization, thin
The importance of the Wafer level packaging of membranization and cost degradation improves constantly.Fan-out-type wafer-level packaging (FOWLP:Fan-
Out WLP) technology is best suitable for the movement/wireless market of high request at present, and other paid close attention to high-performance and undersized city
, it may have the strongest captivation.Use this technology, can also seal even if the more chip of number of terminals does not reduce spacing
Dress, even if chip shrinks without change package dimension.Therefore, FOWLP can realize the standardization of package dimension, the most permissible
Realize multiple chip, can be the hybrid package of different cultivars chip so that it is in terms of functional realiey, attracted more concern.
In Embedded wafer-level packaging manufacturing process, during wafer sealing moulding, the displacement of bare chip (Die) is one
Relatively common problem.The shift value scope of bare chip is generally in 20～100 μm, and this can cause the dislocation of lithography alignment, resistance
Rc degradation, inner connecting structure lost efficacy, and limited the bonding pads separation of device.
Therefore, how to provide a kind of fan-out-type Wafer level packaging, to reduce the displacement of bare chip in encapsulation process,
Become the important technological problems that those skilled in the art are urgently to be resolved hurrily.
Summary of the invention
Prior art in view of the above, it is an object of the invention to provide a kind of fan-out-type wafer-level packaging method and envelope
Piece installing, bare chip displacement problem during for solving FOWLP encapsulated moulding in prior art.
For achieving the above object and other relevant purposes, the present invention provides a kind of fan-out-type wafer-level packaging method, including
Following steps:
One carrier is provided；
Releasing layer is formed at described carrier surface；
Groove is offered at the carrier surface being formed with described releasing layer；
The bare chip with contact pad is provided, described bare chip face down is put in described groove, makes described naked
Being partly embedded in described groove of chip, the back side protrudes from described carrier surface；
Form molding compound at the carrier surface being embedded with described bare chip, make described molding compound wrap up described naked core
Sheet protrudes from the part of described carrier surface；
Remove described releasing layer, make described bare chip separate with described carrier, expose the front of described bare chip；
Form wiring layer again, make described in again wiring layer electrically connect with the contact pad of described bare chip；
Metal coupling is installed, makes described metal coupling be electrically connected by the contact pad of described wiring layer again with described bare chip
Connect.
Alternatively, one or more in silicon, silicon oxide, metal, glass or pottery of the material of described carrier.
Alternatively, described carrier is plate.
Alternatively, the material of described releasing layer is inorganic material or polymeric material..
Alternatively, the method forming described releasing layer is chemical gaseous phase deposition or spin coating, the method removing described releasing layer
For laser ablation.
Alternatively, the thickness of described releasing layer is less than 1 μm.
Alternatively, the method offering groove is laser drill, machine drilling or deep reaction ion etching.
Alternatively, the width of described groove is consistent with the width of described bare chip and length with length, makes described bare chip
Just clamping is fixed in described groove.
Alternatively, described bare chip embeds the thickness of described groove part less than 5 μm.
Alternatively, described depth of groove is 5～20 μm.
Alternatively, when described bare chip face down being put in described groove, it is formed with guarantor in described bare chip front
Sheath；Remove described releasing layer, after making described bare chip separate with described carrier, expose and cover the described of described bare chip front
Protective layer, then removes described protective layer and exposes the front of described bare chip.
Still optionally further, described protective layer is pasty state or glue, or is solid film, or for ultraviolet release adhesive tape or
Heat release adhesive tape.
Still optionally further, the method forming described protective layer is spin coating, printing, chemical gaseous phase deposition or lamination.
Still optionally further, the thickness of described protective layer is 5～20 μm.
Still optionally further, the method removing described protective layer is laser ablation, stripping, dry or wet etch, chemistry
Agent dissolving, ultraviolet release or heat release.
Alternatively, the material forming described molding compound is epoxylite, liquid type thermosetting epoxy resin or moulds
Material mold compound.
Alternatively, the method forming described molding compound is compression forming, transfer modling, fluid-tight molding, vacuum lamination
Or spin coating.
Alternatively, described wiring layer again includes metal connecting line and is located at the dielectric layer around described metal connecting line, described
Metal connecting line is electrically connected with the contact pad of described bare chip by through hole, and electrically connects with described metal coupling.
Still optionally further, when forming wiring layer, described dielectric layer covers described bare chip and described molding is combined again
Thing.
Still optionally further, the material of described dielectric layer is SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2, polyimides
(Polyimide, PI), polybenzoxazole (Polybenzoxazole, PBO), benzocyclobutene (Benzocyclobutene,
BCB) one or more in.
Still optionally further, forming the method for described dielectric layer is that physical vapour deposition (PVD), chemical gaseous phase deposit, print, revolve
It is coated with, sprays, sinters or thermal oxide.
Still optionally further, the material of described metal connecting line include the one in Cu, Al, Ag, Au, Sn, Ni, Ti, Ta or
Multiple.
Still optionally further, the method forming described metal connecting line includes the one in electrolysis plating, chemical plating, silk screen printing
Or it is multiple.
Alternatively, forming Underbump metallization layer on described wiring layer again, described Underbump metallization layer passes through described cloth again
Line layer electrically connects with the contact pad of described bare chip, and described metal coupling is arranged on described Underbump metallization layer.
Alternatively, described metal coupling is solder ball, copper ball or gun-metal ball；The forming method of described metal coupling is
Electroplate or plant ball.
As it has been described above, the fan-out-type wafer-level packaging method of the present invention and packaging part, have the advantages that
The fan-out-type wafer-level packaging method of the present invention, by offering on carrier and the groove of bare chip consistent size, makes
Bare chip embeds in a groove just, such that it is able to utilize the screens effect of groove to fix bare chip position on carrier, keeps away
Exempt from or decrease the displacement of bare chip in encapsulation process.The displacement problem of bare chip during owing to solving encapsulated moulding, utilizes
The packaging part of the inventive method can have narrower device bonding pad gap and higher input and output number (I/O counts)；And
And the alignment efficiency of subsequent optical carving technology can be improved, thus product yield and yield can be improved；Wiring layer can be reduced again
Live width and line gap (LW/LS), reduce package dimension further, reduces cost.
Accompanying drawing explanation
Fig. 1 is shown as the schematic diagram of the fan-out-type wafer-level packaging method that the present invention provides.
Fig. 2 a-2g is shown as the process flow diagram of the fan-out-type wafer-level packaging method that the embodiment of the present invention provides.
Element numbers explanation
101 carriers
102 releasing layers
201 bare chips
2011 contact pads
202 protective layers
301 molding compound
400 wiring layers again
401 dielectric layers
402 metal connecting lines
501 metal couplings
502 Underbump metallization
S1～S8 step
Detailed description of the invention
Below by way of specific instantiation, embodiments of the present invention being described, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also be by the most different concrete realities
The mode of executing is carried out or applies, the every details in this specification can also based on different viewpoints and application, without departing from
Various modification or change is carried out under the spirit of the present invention.It should be noted that, in the case of not conflicting, following example and enforcement
Feature in example can be mutually combined.
It should be noted that the diagram provided in following example illustrates the basic structure of the present invention the most in a schematic way
Think, the most graphic in component count, shape and size time only display with relevant assembly in the present invention rather than is implemented according to reality
Drawing, during its actual enforcement, the kenel of each assembly, quantity and ratio can be a kind of random change, and its assembly layout kenel is also
It is likely more complexity.
Referring to Fig. 1, the present invention provides a kind of fan-out-type wafer-level packaging method, comprises the following steps:
S1 provides a carrier；
S2 forms releasing layer at described carrier surface；
S3 offers groove at the carrier surface being formed with described releasing layer；
S4 provides the bare chip with contact pad, described bare chip face down is put in described groove, makes described
Being partly embedded in described groove of bare chip, the back side protrudes from described carrier surface；
S5 forms molding compound at the carrier surface being embedded with described bare chip, makes described molding compound parcel described naked
Chip protrudes from the part of described carrier surface；
S6 removes described releasing layer, makes described bare chip separate with described carrier, exposes the front of described bare chip；
S7 forms wiring layer again, make described in again wiring layer electrically connect with the contact pad of described bare chip；
S8 installs metal coupling, makes described metal coupling by the contact pad electricity of described wiring layer again with described bare chip
Connect.
Bare chip, by offering groove on carrier, is embedded in a groove, such that it is able to utilize groove by this method for packing
Screens effect fix bare chip position on carrier, it is to avoid or decrease the displacement of bare chip in encapsulation process.
Technical scheme is described in detail below by concrete example.
Referring to Fig. 2 a-2g, the present embodiment provides a kind of fan-out-type wafer-level packaging method.
First, it is provided that a carrier 101, and at described carrier 101 surface formation releasing layer 102, as shown in Figure 2 a.Described load
The material of body 101 can be selected from one or more in silicon, silicon oxide, metal, glass or pottery, or other analog, preferably
For glass.Described carrier 101 can be plate.Carrier 101 described in the present embodiment is for having certain thickness glass plate.
The material of described releasing layer 102 can be inorganic material or polymeric material, or other analog.Form described releasing layer 102
Method can be chemical gaseous phase deposition or spin coating, the method for the described releasing layer of follow-up removal 102 can be laser ablation.This reality
Executing example preferably, the thickness of described releasing layer 102 is less than 1 μm.
As shown in Figure 2 b, groove is offered on carrier 102 surface being formed with described releasing layer 102.
The method offering groove can be laser drill, machine drilling, deep reaction ion etching or other applicable opening
Groove method.The width offering groove is consistent with the width of described bare chip and length with length, enables described bare chip lucky
Clamping is fixed in described groove, i.e. groove can limit bare chip position on its width and length direction, makes bare chip complete
Entirely can not shift.The degree of depth offering groove makes bare chip to be partially submerged into, for example, it is possible to be 5～20 μm.Described groove
Quantity can be one or more, and groove arrangement position on carrier 101 can be designed according to actual needs, the present invention
This is not restricted.
As shown in Figure 2 c, it is provided that there is the bare chip 201 of contact pad 2011, described bare chip 201 face down is put
Entering in described groove, make being partly embedded in described groove of described bare chip 201, the back side protrudes from described carrier 101 surface.
Bare chip 201 i.e. needs the chip naked core (Die) of encapsulation, can be to have the IC chip of multiple semiconductor device and circuit or divide
Vertical semiconductor device etc..When described bare chip 201 face down being put in described groove, it is little that described bare chip 201 only has one
It is partially submerged in described groove, it is preferable that described bare chip 201 embeds the thickness of described groove part less than 5 μm.Bare chip
The quantity of 201 can be one or more, and the arrangement position of multiple bare chips 201 matches with the groove location offered, permissible
It is designed according to actual needs, the invention is not limited in this regard.
The present embodiment preferably, when described bare chip 201 face down is put in described groove, at described bare chip
201 fronts are formed with protective layer 202.Described protective layer 202 1 aspect can protect the front face surface of bare chip 201 to avoid embedding
Damaging during entering or pollute, on the other hand protective layer 201 can help bare chip 201 to stick to, in groove, avoid further
The displacement of bare chip 201.Described protective layer 202 can be pasty state or glue, or is solid film, or discharges adhesive tape for ultraviolet
Or heat release adhesive tape.Formed the method for described protective layer 202 can be spin coating, printing, chemical gaseous phase deposition, lamination or other fit
The method closed.The thinner thickness of described protective layer 202, such as, can be 5～20 μm.
Then, as shown in Figure 2 d, form molding compound 301 on carrier 101 surface being embedded with described bare chip 201, make
Described molding compound 301 wraps up described bare chip 201 and protrudes from the part on described carrier 101 surface, thus by described naked core
Sheet 201 encapsulated moulding.Molding compound 301 described in the present embodiment covers the back side of described bare chip 201 and protrudes from carrier
The side of 101, makes bare chip 201 encapsulate in fixed-type complex 301.The material forming described molding compound 301 is permissible
For cure package material, such as, can be epoxylite, liquid type thermosetting epoxy resin, plastic molding compound or similar
Thing.The method forming described molding compound 301 can be compression forming, transfer modling, fluid-tight molding, vacuum lamination, spin coating
Or other methods being suitable for.
It follows that remove described releasing layer 102, make described bare chip 201 separate with described carrier 101, and expose described
The front of bare chip 201.Specifically, the method removing described releasing layer 102 can be laser ablation.Due to described releasing layer
102 between described bare chip 201 and described carrier 101, and after described releasing layer 102 melts, described bare chip 201 is with described
Carrier 101 gets final product natural separation.The front of bare chip 201 described in the present embodiment is additionally provided with protective layer 202, and releasing layer 102 disappears
The protective layer 202 covering described bare chip 201 can be firstly appeared out from after melting.Therefore, it is also desirable to remove described protective layer 202 to expose
Stating the front of bare chip 201, the structure obtained is as shown in Figure 2 e.Remove the method for described protective layer 202 can be laser ablation,
Stripping, dry or wet etch, chemical agent dissolving, ultraviolet release, heat release or other methods being suitable for.
As shown in figure 2f, form again wiring layer (RDL) 400, make described in the connecing of wiring layer 400 and described bare chip 201 again
Touch pad 2011 to electrically connect, to realize the redistribution of chip bonding pad.In the present embodiment, described wiring layer again 400 covers described naked
Chip 201 also extends on the surface of described molding compound 301.Specifically, described wiring layer again 400 can include metal connecting line
402 and be located at the dielectric layer 401 around described metal connecting line 402, described metal connecting line 402 is by through hole and described bare chip
The contact pad 2011 of 201 electrically connects, and electrically connects with the metal coupling of subsequent installation.In the present embodiment, it is preferable that formed
Again during wiring layer 400, described dielectric layer 401 covers described bare chip 201 and described molding compound 301, such that it is able to mend
Full difference in height between described bare chip 201 and described molding compound 301.
Wherein, described metal connecting line 402 can include that one layer or multilayer interconnection metal level, described dielectric layer 401 also may be used
To include one or more layers dielectric material.Preferably, when described metal connecting line 402 comprises multilayer interconnection metal level, given an account of
Electric material can be arranged between described multilayer interconnection metal level, thus can be separated by every layer of interconnecting metal layer.In described multilamellar
Electrical connection can be realized by the way of forming through hole between interconnecting metal layer.
Specifically, the material of described dielectric layer 401 can be SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2, polyamides sub-
Amine (Polyimide, PI), polybenzoxazole (Polybenzoxazole, PBO), benzocyclobutene (Benzocyclobutene,
BCB) one or more in, or other insulant being suitable for.The method forming described dielectric layer 401 can be physical vapor
Deposition, chemical gaseous phase deposition, printing, spin coating, spray, sinter, thermal oxide or other dielectric deposition process being suitable for.Described metal
The material of line 402 can include one or more in Cu, Al, Ag, Au, Sn, Ni, Ti, Ta, or other conductive gold being suitable for
Belong to material.Such as, metal connecting line 402 can be Cu line, and the Seed Layer making Cu line can be Ti/Cu layer.Form described metal
The method of line 402 can include one or more being electrolysed in plating, chemical plating, silk screen printing, or other metals being suitable for sink
Long-pending technique.
Finally, as shown in Figure 2 g, metal coupling 501 is installed, makes described metal coupling 501 by described wiring layer 400 again
Electrically connect with the contact pad 2011 of described bare chip 201.Specifically, can be formed under projection on described wiring layer again 400
Metal level (UBM) 502, described Underbump metallization layer 502 is by the Contact welding of described wiring layer again 400 with described bare chip 201
Dish 2011 electrically connects, and described metal coupling 501 is arranged on described Underbump metallization layer 502.Specifically, described metal coupling
The material of 501 can be selected from one or more in Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, and such as, described metal coupling 501 can
Think solder ball, copper ball or gun-metal ball.The forming method of described metal coupling 501 can be plating or plant ball.
In sum, the fan-out-type wafer-level packaging method of the present invention is by offering and bare chip consistent size on carrier
Groove, make bare chip just embed in a groove, such that it is able to utilize the screens effect of groove to fix bare chip on carrier
Position, it is to avoid or decrease the displacement of bare chip in encapsulation process.The displacement of bare chip during owing to solving encapsulated moulding
Problem, utilizes the packaging part of the inventive method can have narrower device bonding pad gap and higher input and output number (I/O
counts)；And the alignment efficiency of subsequent optical carving technology can be improved, thus product yield and yield can be improved；Can reduce
The live width of wiring layer and line gap (LW/LS) again, reduces package dimension further, reduces cost.So, the present invention effectively overcomes
Various shortcoming of the prior art and have high industrial utilization.
The principle of above-described embodiment only illustrative present invention and effect thereof, not for limiting the present invention.Any ripe
Above-described embodiment all can be modified under the spirit and the scope of the present invention or change by the personage knowing this technology.Cause
This, have usually intellectual such as complete with institute under technological thought without departing from disclosed spirit in art
All equivalences become are modified or change, and must be contained by the claim of the present invention.
Claims (25)
1. a fan-out-type wafer-level packaging method, it is characterised in that comprise the following steps:
One carrier is provided；
Releasing layer is formed at described carrier surface；
Groove is offered at the carrier surface being formed with described releasing layer；
The bare chip with contact pad is provided, described bare chip face down is put in described groove, makes described bare chip
Be partly embedded in described groove, the back side protrudes from described carrier surface；
Form molding compound at the carrier surface being embedded with described bare chip, make described molding compound wrap up described bare chip convex
Part for described carrier surface；
Remove described releasing layer, make described bare chip separate with described carrier, expose the front of described bare chip；
Form wiring layer again, make described in again wiring layer electrically connect with the contact pad of described bare chip；
Metal coupling is installed, makes described metal coupling be electrically connected with the contact pad of described bare chip by described wiring layer again.
Fan-out-type wafer-level packaging method the most according to claim 1, it is characterised in that: the material of described carrier is selected from
One or more in silicon, silicon oxide, metal, glass or pottery.
Fan-out-type wafer-level packaging method the most according to claim 1, it is characterised in that: described carrier is plate.
Fan-out-type wafer-level packaging method the most according to claim 1, it is characterised in that: the material of described releasing layer is nothing
Machine material or polymeric material.
Fan-out-type wafer-level packaging method the most according to claim 1, it is characterised in that: the method forming described releasing layer
Depositing for spin coating or chemical gaseous phase, the method removing described releasing layer is laser ablation.
Fan-out-type wafer-level packaging method the most according to claim 1, it is characterised in that: the thickness of described releasing layer is less than
1μm。
Fan-out-type wafer-level packaging method the most according to claim 1, it is characterised in that: the method offering groove is laser
Boring, machine drilling or deep reaction ion etching.
Fan-out-type wafer-level packaging method the most according to claim 1, it is characterised in that: the width of described groove and length
Consistent with the width of described bare chip and length, make the lucky clamping of described bare chip be fixed in described groove.
Fan-out-type wafer-level packaging method the most according to claim 1, it is characterised in that: described bare chip embeds described recessed
The thickness of slot part is less than 5 μm.
Fan-out-type wafer-level packaging method the most according to claim 1, it is characterised in that: described depth of groove is 5～20
μm。
11. fan-out-type wafer-level packaging methods according to claim 1, it is characterised in that: described bare chip is just faced
Under when putting in described groove, be formed with protective layer in described bare chip front；Remove described releasing layer, make described bare chip with
After described carrier separates, expose the described protective layer covering described bare chip front, then remove described protective layer and expose described
The front of bare chip.
12. fan-out-type wafer-level packaging methods according to claim 11, it is characterised in that: described protective layer be pasty state or
Glue, or be solid film, or discharge adhesive tape for ultraviolet release adhesive tape or heat.
13. fan-out-type wafer-level packaging methods according to claim 11, it is characterised in that: form the side of described protective layer
Method is spin coating, printing, chemical gaseous phase deposition or lamination.
14. fan-out-type wafer-level packaging methods according to claim 11, it is characterised in that: the thickness of described protective layer is
5～20 μm.
15. fan-out-type wafer-level packaging methods according to claim 11, it is characterised in that: remove the side of described protective layer
Method is laser ablation, stripping, dry or wet etch, chemical agent dissolves, ultraviolet discharges or heat release.
16. fan-out-type wafer-level packaging methods according to claim 1, it is characterised in that: form described molding compound
Material be epoxylite, liquid type thermosetting epoxy resin or plastic molding compound.
17. fan-out-type wafer-level packaging methods according to claim 1, it is characterised in that: form described molding compound
Method be compression forming, transfer modling, fluid-tight molding, vacuum lamination or spin coating.
18. fan-out-type wafer-level packaging methods according to claim 1, it is characterised in that: described wiring layer again includes gold
Belonging to line and be located at the dielectric layer around described metal connecting line, described metal connecting line is contacted by through hole and described bare chip
Pad electrically connects, and electrically connects with described metal coupling.
19. fan-out-type wafer-level packaging methods according to claim 18, it is characterised in that: when forming again wiring layer, institute
Give an account of electric layer and cover described bare chip and described molding compound.
20. fan-out-type wafer-level packaging methods according to claim 18, it is characterised in that: the material of described dielectric layer is
SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2, polyimides, polybenzoxazole, one or more in benzocyclobutene.
21. fan-out-type wafer-level packaging methods according to claim 18, it is characterised in that: form the side of described dielectric layer
Method is physical vapour deposition (PVD), chemical gaseous phase deposition, printing, spin coating, sprays, sinters or thermal oxide.
22. fan-out-type wafer-level packaging methods according to claim 18, it is characterised in that: the material of described metal connecting line
Including one or more in Cu, Al, Ag, Au, Sn, Ni, Ti, Ta.
23. fan-out-type wafer-level packaging methods according to claim 18, it is characterised in that: form described metal connecting line
Method includes one or more being electrolysed in plating, chemical plating, silk screen printing.
24. fan-out-type wafer-level packaging methods according to claim 1, it is characterised in that: shape on described wiring layer again
Becoming Underbump metallization layer, described Underbump metallization layer is electrically connected with the contact pad of described bare chip by described wiring layer again,
Described metal coupling is arranged on described Underbump metallization layer.
25. fan-out-type wafer-level packaging methods according to claim 1, it is characterised in that: described metal coupling is scolding tin
Ball, copper ball or gun-metal ball；The forming method of described metal coupling is for plating or plants ball.
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| CN110690868A (en) * | 2019-09-27 | 2020-01-14 | 无锡市好达电子有限公司 | Novel wafer-level packaging method for filter |
| CN111128982A (en) * | 2018-10-30 | 2020-05-08 | 联嘉光电股份有限公司 | Fan-out type wafer level light emitting diode packaging method and structure thereof |
| CN111370323A (en) * | 2018-12-26 | 2020-07-03 | 中芯集成电路（宁波）有限公司 | Method for manufacturing semiconductor device |
| CN112786540A (en) * | 2019-11-06 | 2021-05-11 | 富泰华工业（深圳）有限公司 | Fan-out type packaging structure and manufacturing method thereof |
| CN115565893A (en) * | 2022-12-06 | 2023-01-03 | 深圳宏芯宇电子股份有限公司 | Packaging method, packaging equipment and plastic package element |
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| CN111128982A (en) * | 2018-10-30 | 2020-05-08 | 联嘉光电股份有限公司 | Fan-out type wafer level light emitting diode packaging method and structure thereof |
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