CN106158045B - A kind of site selection system of the naked array of phase change memory - Google Patents
A kind of site selection system of the naked array of phase change memory Download PDFInfo
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- CN106158045B CN106158045B CN201610470708.2A CN201610470708A CN106158045B CN 106158045 B CN106158045 B CN 106158045B CN 201610470708 A CN201610470708 A CN 201610470708A CN 106158045 B CN106158045 B CN 106158045B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56004—Pattern generation
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C2029/1806—Address conversion or mapping, i.e. logical to physical address
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Abstract
The invention discloses a kind of site selection systems of the naked array of phase change memory, for providing addressing control when being tested for the property to phase change memory array；Including row selection circuit, line control circuit, column select circuit and column control circuit；One end of line control circuit is connect with the row selection circuit, and the other end of line control circuit with phase change memory array for connecting；One end of column control circuit is connect with column select circuit, and the other end of column control circuit with phase change memory array for connecting；When work, row selection circuit and column select circuit are connect with characteristic of semiconductor analyzer, test signal and pumping signal needed for characteristic of semiconductor analyzer is used to provide phase change memory array test；The gating that multiplexing High Speed Analog channel is realized by row selection circuit and column select circuit, the row address and column address of the phase change memory array are selected by binary address code.
Description
Technical field
The invention belongs to micro-nano electronic technology fields, and in particular to a kind of site selection system of the naked array of phase change memory.
Background technique
Phase transition storage be utilize the phase-change material based on chalcogenide compound that can occur between crystalline and amorphous can
The basic principle of reverse transformation carrys out storing data.Phase-change material has low-resistivity when being in crystalline state, shows low resistance state；In non-
There is high resistivity when crystalline state, show high-impedance state.Pulse pair phase-change material by applying different characteristics carries out heating can be real
Phase co-conversion between existing crystalline state and amorphous state.Significant difference between two kinds of high low resistance states of phase, therefore pass through high resistant and low-resistance
When current difference it is also significant, can effectively distinguish binary " 0 " and " 1 " two states, realize the storage and read-write of data.
Phase transition storage realizes that the core of storage and read-write capability is phase-change material (based on chalcogenide compound), phase change memory
The common typical structure of unit is mainly made of top electrode, phase change layer, lower electrode, insulating layer and substrate.Pass through upper/lower electrode pair
Phase-change material applies pulse, and different pulse pair phase-change materials has different Joule heat heating effects, so that phase-change material is in crystalline substance
Phase co-conversion between state and amorphous state.Phase transformation occurs mainly in the pocket in phase change layer close to lower electrode, referred to as phase transformation
Region.Phase-change material is most of using Ge2Sb2Te5, abbreviation GST at present based on chalcogenide compound alloy.Electrode material
Material is general to select high-melting-point, low-resistance material, such as TiW.
Phase-change memory cell is mainly operated by the way of applying pulse signal, specific mode of operation has three
Kind: RESET operation (writing process), SET operation (erase process) and READ operation (reading process).Carrying out RESET operation is
So that phase-change memory cell is reached high-impedance state, cope with it and apply a pulsewidth compared with the higher voltage of small magnitude or current pulse signal,
The temperature of phase-change memory cell phase change region is set to rapidly rise to fusion temperature or more, the state of phase-change material long-range order first
It is destroyed, then so that phase change region is cooled fast to crystallization temperature hereinafter, phase-change material has little time crystallization, formation amorphous state presents high
Resistance state；Carrying out SET operation is that phase-change memory cell is made to reach low resistance state, copes with it and applies a lower electricity of pulsewidth higher magnitude
Pressure or current pulse signal, when such pulse pair phase change region heats, phase-change material rests on fusion temperature and knot for a long time
Between brilliant temperature, phase-change material has time enough to be crystallized, abundant crystallization, forms crystalline state and low resistance state is presented；Carry out READ
Operation is to cope with it in order to read the high low resistive state of phase-change memory cell to read data " 0 " or " 1 " of storage and apply width
It is worth the pulse signal of very little, the Joule heat of generation is insufficient to interfere with the phase of phase-change material, therefore while being read out will not change
The data of phase-change memory cell storage.
The phase change memory array structure of mainstream is upper/lower electrode crossed array at present, and upper/lower electrode intersection is one and deposits
Storage unit, electrode, which applies pulse signal etc., to be written and read the unit.In phase change memory array, each is deposited
Storage unit only includes a memory resistor, i.e. phase-change memory cell, the both ends of the storage unit be connected respectively to a wordline and
One bit line.When a bit line is set high level/low level by column decoder.And other bit lines it is hanging when, indicate the bit line
Effectively；When a wordline is set low level/high level by line decoder, and other wordline are hanging, indicate that the wordline is effective.
Often choose a bit line and a wordline that a storage unit is just chosen to be operated.It can also directly be directly selected by acupuncture treatment
One top electrode and a lower electrode are tested to determine that a storage unit accesses test macro.
It can be carried out as needed after the upper/lower electrode of phase-change memory cell is correctly connected to characteristic of semiconductor analyzer
The test of relevant.The test of phase change memory array carries out on this basis, it is important to the selection of efficiently and accurately
Any to-be-measured cell.According to laboratory existing device, carrying out test addressing to array mainly has following two sets of plan:
(1) have an acupuncture treatment addressing method: using probe station micron probe prick on the Pad that electrode is drawn, two probes respectively with
Two ports of characteristic of semiconductor analyzer are connected, and one of probe is pricked on the Pad that array element top electrode is drawn, another
A probe is pricked on the Pad that electrode is drawn under array element, and bundle, which takes different upper/lower electrodes i.e., every time can determine in array not
Test macro is connected into unit；
(2) it designs site selection system: using after wire bonding wiring, electrode being led into each pin, designs peripheral circuit
It with addressing test board selects different pins and determines the unit in array to select different upper/lower electrodes and tested.
The first scheme, the equipment of use mainly have Cascade S300 microwave probe platform, characteristic of semiconductor analyzer, height
Frequency oscillograph etc..On microwave probe platform, with the upper/lower electrode of two probe selected cells, the signal exit of probe respectively with
Characteristic of semiconductor parameter tester, ondograph, sample resistance connection.The source measuring unit of characteristic of semiconductor analyzer can be with
DC I-V scanning is carried out, phase change cells I-V characteristic curve, and read threshold voltages and threshold current from curve are obtained.Partly lead
The impulse generator of bulk properties analyzer can produce high-speed pulse, carry out the erasable operation of pulse.Oscillograph is used to observe waveform,
The failing edge of distortion is avoided to influence the phase transition process of unit.It tests to obtain transformation curve by I-V, determines phase-change memory cell
High low resistance state；By gradually adjusting the amplitude and width of pulse signal, phase-change memory cell SET pulse parameter, RESET arteries and veins are determined
Rush parameter.
Test of this scheme for a phase-change memory cell in phase change memory array, can be convenient efficiently to selected
Unit is tested, but this method is higher to environmental requirement, and the depth difference having an acupuncture treatment can obtain different contact electricity
Resistance, this also will affect test result.More major problem is that, unit is manually found under the microscope using needs when this scheme,
Testing efficiency is very low.Therefore a kind of array test is needed since the unit to be surveyed is more for large-capacity phase change storage array
System is carried out engagement unit addressing and is tested.Pin is drawn after wire bonding wiring using second scheme, using setting
The site selection system of meter will be rapid and simple and accurately selectes unit, completes to test the correlated performance of selected unit.
Generally speaking, the key of two kinds of test phase change memory array schemes is all that can accurately search out to-be-measured cell.It is former
There is scheme using probe station pricking, is only assured that the unit with the Pad for pricking upper to-be-measured cell upper/lower electrode extraction, but have an acupuncture treatment
Operation is time-consuming relatively complicated.
Summary of the invention
In view of the drawbacks of the prior art, the purpose of the present invention is to provide a kind of site selection system of the naked array of phase change memory,
Aim to solve the problem that tradition acupuncture treatment site selecting method testing efficiency is low, test result is easier to the technology influenced by acupuncture treatment degree problem
Problem.
The present invention provides a kind of site selection systems of the naked array of phase change memory, for carrying out performance to phase change memory array
Addressing control is provided when test；Including row selection circuit, line control circuit, column select circuit and column control circuit；The row control
One end of circuit processed is connect with the row selection circuit, and the other end of the line control circuit is used to connect with phase change memory array
It connects；One end of the column control circuit is connect with the column select circuit, and the other end of the column control circuit is used for and phase transformation
Storage array connection；When work, the row selection circuit and the column select circuit are connect with characteristic of semiconductor analyzer, and half
Test signal and pumping signal needed for conductor characteristics analyzer is used to provide phase change memory array test；Pass through row selection circuit
The gating that multiplexing High Speed Analog channel is realized with column select circuit selects the phase change memory battle array by binary address code
The row address and column address of column.
Further, the row selection circuit is identical with the structure of the column select circuit, including the n grade connected step by step
High-speed switch array；The first order includes a switch unit, and switch unit includes 2mRoad multiplex channel analog switch, 2mRoad multiplexing
One end of channel analogy switch is connected and receives input signal as common end；The second level includes 2mA switch unit, each
Switch unit includes 2mRoad multiplex channel analog switch, 2 in first switch unitmOne end of road multiplex channel analog switch is equal
It is connected and is connect with the other end of first via multiplex channel analog switch in the first order；2 in second switch unitmRoad multiplexing is logical
One end of road analog switch is connected and connect with the other end of the second road multiplex channel analog switch in the first order；... the 2ndm
2 in a switch unitmOne end of road multiplex channel analog switch is connected and with the in the first order the 2mRoad multiplex channel analog switch
The other end connection；... n-th grade includes 2m×(n-1)A switch unit, each switch unit include 2mMultiplex channel simulation in road is opened
It closes, 2 in first switch unitmOne end of road multiplex channel analog switch be connected and with first via multiplex channel in previous stage
The other end of analog switch connects；2 in second switch unitmOne end of road multiplex channel analog switch be connected and with it is previous
The other end connection of second road multiplex channel analog switch in grade；... the 2ndm×(n-1)2 in a switch unitmRoad multiplex channel mould
One end of quasi- switch is connected and with the in previous stage the 2mThe other end of road multiplex channel analog switch connects；Wherein, m, n are
Positive integer more than or equal to 1.
Further, the line control circuit is identical with column controling circuit structure, including the road m*n control unit, each
Road control unit includes the resistance and switch being sequentially connected in series, the non-series connection termination power of resistance, the non-series connection of switch
Connecting pin ground connection.
The invention has the advantages that being carried out after phase change memory array to be measured is accessed test macro to different units in array
When test, it is only necessary to determine the ranks number where the unit, and ranks number is converted into binary address code, it is controlled by changing
Circuit inputs corresponding rank addresses binary address code to the closed state of inductive switch, and circuit will gate corresponding ranks electricity
Pole forms test loop and completes test.It is more fast and simple than traditional PAD STITCH, substantially increase testing efficiency, and will not be because of
Acupuncture treatment is horizontal to influence test result.And each unit of gating phase change memory array may be implemented in the present invention, meets test
It is required that.
Detailed description of the invention
Fig. 1 is the site selection system and phase change memory array and semiconductor of the naked array of phase change memory provided in an embodiment of the present invention
Structural schematic diagram between specificity analysis instrument；
Fig. 2 is column select circuit and row selection electricity in the site selection system of the naked array of phase change memory provided in an embodiment of the present invention
The structural schematic diagram on road；
Fig. 3 is line control circuit and column control electricity in the site selection system of the naked array of phase change memory provided in an embodiment of the present invention
The structural schematic diagram on road.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
In order to meet the testing requirement of phase change memory array, phase change memory array test macro of the invention be can be convenient fastly
Speed accurately selects one of more wordline bit line and is accessed characteristic of semiconductor analyzer to be tested.Present invention design
The test macro of the large-capacity phase change memory array provided is used for the large-scale phase transition storage without gating transistor
Array is tested.Test macro can be used toggle switch and carry out binary system addressing, by high-speed, multi-path analog channel to big
Unit in type phase change memory array is gated, and carries out property to phase-changing memory unit with characteristic of semiconductor analyzer
Performance test.
Characteristic of semiconductor analyzer is used to generate test, pumping signal, and measures work.
It is the site selection system substitution acupuncture treatment addressing with design in the principle of the invention, addressing test board is only to be measured with control input
To-be-measured cell can be accessed the survey that test circuit carries out relevant by the binary code of unit ranks (wordline bit line) address
Examination.Entire test loop the general frame is as shown in Figure 1.
Such as figure, row selection circuit and column select circuit and relevant control circuit constitute site selection system, phase change memory array
The test that entire test loop completes phase change memory array is connected and composed by site selection system and characteristic of semiconductor analyzer.
Since the phase change memory array of test mainly uses upper/lower electrode cross array structure, row selection circuit and column selection
Circuit is the key component of site selection system, the main choosing that multiplexing High Speed Analog channel is realized using multistage high-speed switch array
It is logical, array row address and column address (top electrode and lower electrode) can be selected by binary address code.Control circuit control input
To the binary address code of row selection circuit and column select circuit, the methods of single-chip microcontroller or switch control low and high level can be passed through
To realize.Selection circuit and control circuit are all designed on PCB development board, hot-wire array is mounted on pcb board and semiconductor
Specificity analysis instrument is connected.Characteristic of semiconductor analyzer (this laboratory use have Keithley 4200-SCS, Keysight-
B1500) it is used to test and pumping signal needed for phase-change memory cell and array test are provided.It contains exciting test unit
(SMU), front-end amplifier, the modules such as impulse generator are far set, the configuration parameter of these modules can satisfy phase-change memory cell
Resistance test, DC I-V sweep test, the test of pulse I-V sweep and the requirement of Reset and Set pulse test.When test,
Row selection circuit and column select circuit select test cell and access test loop, generate test signal by characteristic of semiconductor analyzer
Or pumping signal.
With the method, when changing test cell, does not have to transformation acupuncture treatment, only determine that its is right with by the ranks number of to-be-measured cell
The ranks binary address code answered changes control circuit and corresponds to switch closed condition, controls the input of binary address code
Selected to-be-measured cell access test circuit, substantially increases testing efficiency.Multiplexing analog channel is design row selection circuit
With the key of column select circuit, multiplexes analog channel and connected and composed step by step by multistage high-speed switch array.
Fig. 2 gates schematic diagram by the multiplexer channel that n grades of switch arrays form.As shown in Fig. 2, the switch of every level-one
It is 2mRoad multiplex channel analog switch, the first order are switched with one, public termination signal input part, and 2mA multiplex channel end point
The 2 of the second level are not connectmThe common end of a switch, thus two-stage switch arrays can gate 2 altogetherm×2m=2m×2Paths, thus
Analogize, each multiplex channel of every level-one switch is connected with the common end of next stage switch, then n grades of switch arrays in total may be used
To realize gating 2m×(n-1)Paths.Need m × n binary-coded address control gating channels.For example, simply such as one
Secondary switch array, each switch selects 4 road multiplex channels, can gate the road 4 × 4=16 in total.It is with binary system
It is gating 24Road, so needing 4 binary-coded address control gating channels.2 control level-one switches before 4 bit address, latter 2
Secondary switch is controlled, determines that 4 binary codes can determine the channel on one of 16 tunnels of gating.Such as input address code is
" 0111 ", front two " 01 " it is confirmed that level-one switch the 2nd road gating, access the common end of second secondary switch, latter 2
" 11 " are it is confirmed that the 4th tunnel of this secondary switch gates, therefore what is finally selected is the 8th paths in 16 paths.Thus
Analogize, according to three step switch array, the road 4 × 4 × 4=64 gating can be carried out, while needing 6 binary address codes.Root
Principle can design row selection circuit and column select circuit, ranks selection circuit according to the size of phase change memory array to be measured accordingly
It is all to be made of multiple-pole switch, the series that switch arrays divide is determined by the port number of selected multiplexer channel analog switch
It is fixed.
Each 2mRoad multiplex channel analog switch has an input channel and 2mRoad output channel, in addition there are also m ground
Location code input terminal.This m bit address code input terminal is then connected with control circuit, determines the simulation by the binary address code of input
Switch the channel be connected when work.The binary address code of control circuit input determines rank addresses.It is connected using toggle switch
Resistance controls the low and high level of resistance lower end by the way that whether control switch is connected.
The selection of multiplexer channel analog switch needs to consider carefully.Firstly, the choosing that will be made of multistage high-speed switch
When location circuit access test circuit, due to having high speed signal when test, the not selected channel of open circuit is kept at this time
It will be equivalent to a series-parallel capacitor, these equivalent capacitive loads will will affect test signal.By selecting stable switch core
Piece can control load effect in tolerance interval；In addition, shadow of the bandwidth of multiplexing analog channel to signal integrity
It is also noticeable for ringing.
Output channel of the every row electrode of phase change memory array all with row selection circuit switch arrays is respectively connected with, each column electricity
Output channel of the pole all with column select circuit switch arrays is respectively connected with, when test, the ranks transformation of variables of to-be-measured cell at two
Ary codes are input to ranks selection circuit by row column control circuit to determine channel respectively.The common end of ranks selection circuit
It is connected respectively with the both ends of characteristic of semiconductor analyzer, then entire test macro forms signal circuit.
Line control circuit is identical with column controling circuit structure, as shown in figure 3, include the road m*n control unit, it is every to control all the way
Unit processed includes the resistance and switch being sequentially connected in series, the non-series connection termination power of resistance, the non-series connection of switch
End ground connection.
For a kind of further description site selection system of the naked array of phase change memory provided in an embodiment of the present invention；Now with
For the realization of 256Kb phase change memory array addressing test board, details are as follows: quick when in order to realize phase change memory array test
The function of addressing, addressing circuit design is integrated on circuit printing plate (PCB) by we.Altium Designer is a excellent
Elegant PCB design software, has the function of powerful circuit design, this software can draw principle diagram design, circuit simulation, PCB
It makes editor, topological logic self routing, signal integrity analysis and designs the fusion of the technological perfectionisms such as output.It is to pass through benefit herein
Go out schematic diagram into after crossing simulation optimization with Altium Designer Software on Drawing and produce pcb board again, then component is welded to
Method on pcb board designs the phase change memory array test addressing test board of a 256Kb.
When designing phase change memory array addressing test board, due to needing to use high-speed pulse signal etc. when test, design
The problems such as signal integrity, Power Integrity, electromagnetic interference will be faced in the process.Therefore soft using Altium Designer
Part carries out that the processes such as PCB layout, components' placement and PCB layering should be thought better of when PCB design and wiring.
By it is previously described it is recognised that entire test macro be the row selection circuit controlled by multiplexing analog channel and
Phase change memory array is connected by column select circuit with two ports of characteristic of semiconductor analyzer, the row electricity of row selection circuit selection
The column electrode infall of pole and column select circuit selection constitutes storage unit to be measured, accesses entire test circuit forming circuit.
By taking a 256Kb phase change memory array test site selection system in the present invention as an example, which is by 512 × 512
Phase-change memory cell is constituted, i.e., the array is made of 512 row electrodes and 512 column electrode intersections.512=16 × 16 × 2, because
This, row selection circuit and column select circuit may be designed to three step switch array, and the first order is 2 road multiplexed analog channels, the
The second level third level is 16 road multiplexed analog channels.The switch arrays of row selection circuit and column select circuit are by 9 two-stage system codes
Address control, provides 512 road multiplexed analog channels for phase change memory array.
Wherein, an input terminal connects the end SMU1 of characteristic of semiconductor analyzer Keysight-B1500 by BNC connector,
For input test signal and pumping signal, 512 road multiplexed analog channels connect 512 lines respectively, according to the binary system of input
Address code selects one of channel output, to choose the row electrode of phase change memory array to-be-measured cell.512=29Road output
It needs 9 bit address to be selected in total, therefore has prepared 9 bit address input terminal A0~A8.The wherein input side of address A0~A8
Formula devises two methods simultaneously, and one is use Labview control program structure computer interfaces to provide man-machine interactive interface,
Rank addresses are inputted on interface, are sent address code on single-chip microcontroller by computer disposal, and single-chip microcontroller is according to experiment needs
It oneself programmes and address code is input on addressing test board in the form of low and high level；Another method is that direct utilize is dialled
Code switch connects resistance, controls one section of resistance of low and high level by the way that whether control switch is connected, and then determine multichannels at different levels
The gating in multiplexed analog channel.
Since row electrode is interspersed in phase change memory array the right and left, first order switch divides the channel into 2 256
Road, 256 tunnels are to be all odd column, another 256 tunnel is all even column.First order gating is TI's using chip
TS5A63157 chip.This chip is high-speed analog switch, and a common end COM connects BNC input, and an input terminal IN passes through lock
Storage is grounded location A0, and two output ends NC and NO connect the odd number end ordered series of numbers COM and the end even column COM respectively, as IN=A0=0,
The odd column of array gates, and as IN=A0=1, the even column of array is gated.The second level and third level gating circuit use
The CD74HC4067 of TI, this chip are No. 16 multiplexers, and operating voltage 2V~6V provides 16 tunnel analog channels, and bandwidth reaches
To 89MHZ, test request can satisfy.Chip has 4 control terminal S0~S3, for controlling the output on 16 tunnels.Second level choosing
Circuit passband uses two CD74HC4067, and odd column is one corresponding, and COM terminates the end NC of the first order；Even column is one corresponding,
Its end COM corresponds to the end NO of the first order, and four control terminal S0~S3 of two chips respectively correspond 8 in addition to A0 in the line of address
Gao Siwei, that is, A1 of bit address A1~A8~A4, the 16 tunnels output of two chips connect the end COM of 16 CD74HC4067 again respectively, this
2 × 16=32 CD74HC4067 forms third level gating circuit.Four control terminal S0 of chip in third level gating circuit~
S3 is grounded low four i.e. A5~A8 of location A1~A8 respectively.It gates to obtain 2 × 16 × 16 controllable simulations by three-level
Channel is divided into two groups of 16 × 16=256 paths and is connected respectively with 256 road odd columns of array interface with 256 road even columns.It is comprehensive
Upper described, designed three step switch array can be realized by this 9 bit address code of A0~A8 to 512 all analog channels
In any gating function all the way.
Column select circuit uses three-level gating circuit identical with row selection circuit, 2 × 16 × 16 analog channel difference
512 column electrodes of array are connect, and its output end connects characteristic of semiconductor analyzer (Keysight-B1500) by BNC connector
The port other end SMU2.The method that column select circuit inputs 9 binary address codes is also identical as row selection circuit.In this way, logical
The collective effect of space selection circuit and column select circuit, can be in 512 × 512 phase change memory array quickly when test
Unit required for accurately selecting carries out various electrical characteristics tests.
In order to guarantee to test the integrality of signal, the interference of noise in high speed circuit is reduced, is designed according to principles above
It after phase change memory array addressing test board schematic diagram, needs to consider several factors during generating pcb board, specific wiring is all
The methodological principle that will be proposed in many documents of reference.Due to array center's wiring congestion, pcb board uses four-sheet structure, and four layers
It is routed row selection circuit respectively, column select circuit, bus plane, ground plane, the orthogonal trend of signal wire between adjacent layer reduces layer
Between electromagnetic interference.
In embodiments of the present invention, the site selection system of 256Kb phase change memory array is using steps are as follows:
(1) test board power interface is connected into DC power supply, power supply output is 4V, guarantees that each chip normally selects on test board
It is logical.
(2) test board Pin BNC connector is connect into B1500 characteristic of semiconductor analyzer SMU1 delivery outlet, by test board Pout
BNC connector connects B1500 characteristic of semiconductor analyzer SMU2 delivery outlet.Circuit communication is entirely tested at this time.
(3) test switching plate S0~S8 controls 9 binary systems, can gate any a line in 512 rows.Switch S9~S17 control
9 binary systems are made, any one column in 512 column can be gated.
As it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, not to
The limitation present invention, any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should all include
Within protection scope of the present invention.
Claims (2)
1. a kind of site selection system of the naked array of phase change memory, for providing addressing when being tested for the property to phase change memory array
Control；It is characterised in that it includes row selection circuit, line control circuit, column select circuit and column control circuit；
One end of the line control circuit is connect with the row selection circuit, and the other end of the line control circuit is used for and phase transformation
Storage array connection；
One end of the column control circuit is connect with the column select circuit, and the other end of the column control circuit is used for and phase transformation
Storage array connection；
When work, the row selection circuit and the column select circuit are connect with characteristic of semiconductor analyzer, characteristic of semiconductor
Test signal and pumping signal needed for analyzer is used to provide phase change memory array test；Pass through row selection circuit and column selection
Circuit realizes the gating in multiplexing High Speed Analog channel, and the row ground of the phase change memory array is selected by binary address code
Location and column address；
The row selection circuit is identical with the structure of the column select circuit, including the n grade high-speed switch array connected step by step；
The first order includes a switch unit, and switch unit includes 2mRoad multiplex channel analog switch, 2mMultiplex channel simulation in road is opened
One end of pass is connected and receives input signal as common end；
The second level includes 2mA switch unit, each switch unit include 2mRoad multiplex channel analog switch, first switch unit
In 2mOne end of road multiplex channel analog switch is connected and the other end with first via multiplex channel analog switch in the first order
Connection；2 in second switch unitmOne end of road multiplex channel analog switch is connected and leads to the second tunnel multiplexing in the first order
The other end of road analog switch connects；... the 2ndm2 in a switch unitmOne end of road multiplex channel analog switch is connected simultaneously
With the in the first order the 2ndmThe other end of road multiplex channel analog switch connects；
……
N-th grade includes 2m×(n-1)A switch unit, each switch unit include 2mRoad multiplex channel analog switch, first switch
2 in unitmOne end of road multiplex channel analog switch be connected and in previous stage first via multiplex channel analog switch it is another
One end connection；2 in second switch unitmOne end of road multiplex channel analog switch is connected and answers with the second tunnel in previous stage
The other end connection switched with channel analogy；... the 2ndm×(n-1)2 in a switch unitmOne end of road multiplex channel analog switch
It is connected and with the in previous stage the 2ndmThe other end of road multiplex channel analog switch connects；
Wherein, m, n are the positive integer more than or equal to 1.
2. site selection system as described in claim 1, which is characterized in that the line control circuit and column controling circuit structure phase
It together, including the road m*n control unit, include the resistance and switch being sequentially connected in series, the non-series connection of resistance per control unit all the way
Connect termination power, the non-series connection end ground connection of switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610470708.2A CN106158045B (en) | 2016-06-23 | 2016-06-23 | A kind of site selection system of the naked array of phase change memory |
Applications Claiming Priority (1)
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| CN1897156A (en) * | 2005-07-13 | 2007-01-17 | 三星电子株式会社 | Phase change random access memory (pram) device having variable drive voltages |
| CN1959847A (en) * | 2005-09-08 | 2007-05-09 | 三星电子株式会社 | Phase change random access memory device having variable drive voltage circuit |
| CN102354537A (en) * | 2011-07-06 | 2012-02-15 | 华中科技大学 | Method and system for testing chip of phase change memory |
| CN104347111A (en) * | 2013-07-25 | 2015-02-11 | 瑞萨电子株式会社 | Semiconductor integrated circuit device |
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| US9697896B2 (en) * | 2014-02-26 | 2017-07-04 | Stmicroelectronics S.R.L. | High throughput programming system and method for a phase change non-volatile memory device |
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| CN1897156A (en) * | 2005-07-13 | 2007-01-17 | 三星电子株式会社 | Phase change random access memory (pram) device having variable drive voltages |
| CN1959847A (en) * | 2005-09-08 | 2007-05-09 | 三星电子株式会社 | Phase change random access memory device having variable drive voltage circuit |
| CN102354537A (en) * | 2011-07-06 | 2012-02-15 | 华中科技大学 | Method and system for testing chip of phase change memory |
| CN104347111A (en) * | 2013-07-25 | 2015-02-11 | 瑞萨电子株式会社 | Semiconductor integrated circuit device |
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