CN106096177A - A kind of multi-chip joint simulation method based on traditional EDA instrument - Google Patents
A kind of multi-chip joint simulation method based on traditional EDA instrument Download PDFInfo
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- CN106096177A CN106096177A CN201610462881.8A CN201610462881A CN106096177A CN 106096177 A CN106096177 A CN 106096177A CN 201610462881 A CN201610462881 A CN 201610462881A CN 106096177 A CN106096177 A CN 106096177A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2113/00—Details relating to the application field
- G06F2113/18—Chip packaging
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
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Abstract
The present invention relates to a kind of multi-chip joint simulation method based on traditional EDA instrument, including: whole SiP circuit is divided into Digital Logic electronic circuit and analog submodule circuit by circuit function, wherein Digital Logic electronic circuit uses Verilog emulator, analog submodule circuit or the circuit employing HSIM emulator should not being described with Verilog language；Having only to during emulation whole SiP circuit is applied unified test vector, Verilog emulator and HSIM emulator automatically can interact in whole simulation process, transmitted mutually by required emulation intermediate data；After having emulated, the simulation result of all electronic circuits can be checked by view tool.Port and the matching of sequential when the present invention is for verifying each sub-chip collaborative work in SiP circuit, prevent from, because circuit parameter design is unreasonable or port connection error and the circuit operation irregularity problem that causes, providing reference for final SiP design.
Description
Technical field
The present invention relates to a kind of chip emulation method, a kind of multi-chip associative simulation based on traditional EDA instrument
Method.
Background technology
The developing rapidly of electronic information technology has promoted electronic product to develop towards miniaturization, this little to integrated circuit
The aspects such as type, multi-functional, high bandwidth and low-power consumption constantly claim, and the system integration becomes more and more important.In order to meet
The chip integration improved constantly, mainly has two ways to solve: one is SOC(system on a chip) (SoC) technology, and another kind is
System in package (SiP) technology.SoC technology can be integrated in high performance digital circuit and analog circuit in chip piece, but
This technology has cost height, the shortcoming of complex process.SiP technology by multiple chips and passive device integration in a packaging body
In, form a functional device, perform the function of some standard components and parts, thus realize complete machine function.SoC and SiP is
The system integration mode that two kinds are complementary to one another, but owing to SiP is to use ripe micro-group dress and interconnection technique, various integrated electricity
Road such as CMOS, GaAs, SiGe circuit or opto-electronic device, MEMS and all kinds of passive element are integrated into a packaging body
In, in terms of construction cycle, cost and motility, relatively SoC has obvious advantage.It can by all kinds of devices, integrated chip,
Wiring and dielectric layer are all encapsulated in a system, and three layers of original encapsulating structure are integrated into one layer of encapsulating structure.It has
Flexible design, encapsulation volume are little, packaging efficiency high, substantially reduce line distance, drastically increase packaging efficiency
And packaging density.System-in-Package technology be mainly used in application processor, system flash encapsulation it can also be used to mobile phone, number
The electronic products such as camera, also can expand to more areas in the future.
Although system in package the aspect such as integrated level, reliability advantage clearly, but the most also give the imitative of chip simultaneously
True checking brings certain difficulty.Along with circuit integrated in shell gets more and more, the interconnecting relation of chip chamber becomes increasingly complex,
The matching of chip chamber port and sequential become SiP pay close attention to emphasis, its be related to whole SiP circuit can normally work and
The reliability and stability of work.
In order to verify matching and the correctness of interconnecting relation of SiP circuit chip port, IC Front-end Design Shi Tongchang is adopted
Carry out simulating, verifying with the following method: write function and the sequential of a sub-chip in test vector emulation SiP circuit, obtain defeated
New test and excitation is generated, as the test vector of second sub-chip after going out result.Although it is permissible with upper type
Substantially verify the function of SiP chip, but there is a lot of defect: 1, be only used for verifying the SiP circuit comprising less electronic circuit, right
Emulation is cannot be carried out in that circuit that sub-chip is many and annexation is complicated；2, test is generated by the output of a sub-chip
Vector, owing to it contains only sequential and function information, for verifying the matching aspect of two or more sub-chip chamber ports
Cannot be carried out the most real simulation；3, using the mode that above-mentioned level is verified, workload is big, and simulation efficiency is the lowest, it is impossible to suitable
For complicated circuit.
Summary of the invention
The technical problem to be solved in the present invention is to overcome existing defect, on the basis of existing integrated circuit simulating instrument
On, it is provided that a kind of method being applicable to multi-chip collaborative simulation, port when being used for verifying each sub-chip collaborative work in SiP circuit
And the matching of sequential, prevent because circuit parameter design is unreasonable or port connection error and the circuit operation irregularity that causes
Problem, provides reference for final SiP design.
In order to solve above-mentioned technical problem, the invention provides following technical scheme:
A kind of multi-chip joint simulation method based on traditional EDA instrument of the present invention, comprises the following steps:
(1) by circuit function, whole SiP circuit being divided into Digital Logic electronic circuit and analog submodule circuit, wherein numeral is patrolled
Volume electronic circuit (such as protocol processor etc.) uses Verilog emulator, analog submodule circuit (such as memorizer, PLL etc.) or unsuitable
The circuit being described with Verilog language uses HSIM emulator；
(2) whole SiP circuit need to be applied unified test vector, Verilog emulator and HSIM emulator during emulation
Can automatically interact in whole simulation process, required emulation intermediate data is transmitted mutually；
(3), after having emulated, view tool is used to check the simulation result of all electronic circuits.
Further, step (1) needs first to arrange simulated environment before emulation, and emulator is made Initialize installation.
Further, the analog submodule circuit that step (1) describes for using Spice netlist, top need to be taken out from netlist
Layer port list and port direction, add combined simulation system function, shows that this analog submodule circuit uses HSIM emulator；For
The Digital Logic electronic circuit using Verilog netlist to describe, need to quote the library file in PDK.
Further, step (2) needs when emulation whole SiP circuit is applied unified test vector, adds load combined
The VPI shared library of emulation, starts emulation.
Beneficial effects of the present invention:
1, only test vector need to be applied at circuit top layer, it is not necessary to manually generate the test vector of each electronic circuit, imitative in guarantee
On the premise of true precision, drastically increase simulation efficiency.
2, owing to whole simulation flow is without manual intervention, it is to avoid the artificial incorrect operation being likely to occur.
3, the method is equally applicable to the SiP circuit that two or more electronic circuit is constituted, and has good reusability.
Accompanying drawing explanation
Fig. 1 is the composition structure chart of the SiP circuit of the present invention；
Fig. 2 is the simulated environment setting procedure figure that the present invention needs to use；
Fig. 3 is the multi-chip associative simulation flow chart of the present invention.
Detailed description of the invention
Embodiment cited by the present invention, is only intended to help and understands the present invention, should not be construed as the present invention is protected model
The restriction enclosed, for those skilled in the art, without departing from the inventive concept of the premise, it is also possible to right
The present invention makes improvements and modifications, and these improve and modification also falls in the range of the claims in the present invention protection.
By protocol processor DIGITAL (Digital Logic electronic circuit) and SRAM memory, (analog submodule is electric with one for the present invention
Road) the SiP circuit that forms is introduced.The composition structure of SiP circuit is as shown in Figure 1.The emulation tool that the present invention needs
Verilog emulator NC-Verilog and the Spice emulator HSIM of Synopsys company for Cadence company.Carry out
During associative simulation, system will call Verilog routine interface (VPI) or language interface able to programme (PLI) and HSIM and NC-
Verilog emulator interacts.NC-Verilog triggers HSIM emulator as main emulator by calling associative simulation storehouse
Work, and it is mutual to call the information that VPI power function completes between two emulators.
Before starting associative simulation, need to arrange simulated environment, emulator is made Initialize installation.The setting of simulated environment
As shown in Figure 2, setting steps is as follows for flow chart:
1, the operating path of NC-Verilog emulator is set, such as:
Set path=($ path/usr/local/vendors/cadence/ldv40/tools/bin)；
2, VPI shared library libvpihsim.so is added to LD_LIBRARY_PATH environmental variable；
3, TCL shared library path is set, such as:
setenv TCL_LIBRARY/usr/local/vendors/cadence/ldv40/tools/txe/lib/
tcl8.3。
Generally in a SiP circuit, Digital Logic electronic circuit occupies leading, and therefore we are with top layer for Verilog net
As a example by the Digital Logic electronic circuit that table describes, associating simulation flow is described, as shown in Figure 3.
The first step, generates corresponding Verilog netlist according to SRAM memory Spice netlist, only needs to comprise in this netlist
The port list of SRAM top layer, port direction and top-level module name, function describes part and uses initial $ nsda_module () generation
Replace, and by the named SRAM.cs of this Verilog netlist.$ nsda_module () is the system function for associative simulation, shows
This electronic circuit uses HSIM emulator；
Second step, sets up emulation netlist SRAM.sp of SRAM, specifies the Spice netlist path of SRAM, connection in this document
Technology library used and the simulated conditions of SRAM when closing emulation, such as voltage, temperature etc., wherein must comprise following information:
SRAM and the definition of all electronic circuits thereof；
Quoting of all process modelings that emulation need to use；
Need the signal name exported in wave file；
HSIM simulation accuracy and simulation velocity；
3rd step, prepares the Verilog netlist of protocol processor DIGITAL (Digital Logic electronic circuit), if semidefinite
Circuit processed, also needs to include Veriolg library file in corresponding PDK；
4th step, loads the configuration file cosim.cfg of associative simulation, for telling the Spice emulation of emulator HSIM
Parameter and output file title；
5th step, loads VPI shared library libvpihsim.so of associative simulation；
6th step, starts emulation, obtains the output of FSDB simulation waveform file, starts order for ncverilog+loadvpi
=libvpihsim.so:nsda_vpi_startup+nsda+ " xosim.cfg "+access+rwc ffile.f.
Claims (4)
1. a multi-chip joint simulation method based on traditional EDA instrument, it is characterised in that comprise the following steps:
(1) whole SiP circuit is divided into Digital Logic electronic circuit and analog submodule circuit, wherein Digital Logic by circuit function
Circuit uses Verilog emulator, analog submodule circuit or the circuit should not being described with Verilog language to use HSIM to imitate
True device；
(2) whole SiP circuit need to apply during emulation unified test vector, Verilog emulator and HSIM emulator can be
Whole simulation process automatically interacts, required emulation intermediate data is transmitted mutually；
(3), after having emulated, view tool is used to check the simulation result of all electronic circuits.
Multi-chip joint simulation method based on traditional EDA instrument the most according to claim 1, it is characterised in that described
Step (1) needs first to arrange simulated environment before emulation, and emulator is made Initialize installation.
Multi-chip joint simulation method based on traditional EDA instrument the most according to claim 1, it is characterised in that described
The analog submodule circuit that step (1) describes for using Spice netlist, need to take out top level ports list and port side from netlist
To, add combined simulation system function, show that this analog submodule circuit uses HSIM emulator；For using Verilog netlist to retouch
The Digital Logic electronic circuit stated, need to quote the library file in PDK.
Multi-chip joint simulation method based on traditional EDA instrument the most according to claim 1, it is characterised in that described
Step (2) needs when emulation whole SiP circuit is applied unified test vector, loads the VPI shared library of associative simulation, opens
Dynamic emulation.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111931444A (en) * | 2019-05-09 | 2020-11-13 | 长江存储科技有限责任公司 | Simulation method for function peer detection |
| CN112800709A (en) * | 2021-04-09 | 2021-05-14 | 中国电子科技集团公司信息科学研究院 | Digital-to-analog converter modeling method and system and digital-to-analog converter |
| CN115062569A (en) * | 2022-08-17 | 2022-09-16 | 深圳市华杰智通科技有限公司 | Parallel acceleration system and method for millimeter wave chip design simulation EDA (electronic design automation) |
| CN115248998A (en) * | 2022-09-22 | 2022-10-28 | 济南新语软件科技有限公司 | SoC chip distributed simulation verification platform and method |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111931444A (en) * | 2019-05-09 | 2020-11-13 | 长江存储科技有限责任公司 | Simulation method for function peer detection |
| CN112800709A (en) * | 2021-04-09 | 2021-05-14 | 中国电子科技集团公司信息科学研究院 | Digital-to-analog converter modeling method and system and digital-to-analog converter |
| CN112800709B (en) * | 2021-04-09 | 2021-07-02 | 中国电子科技集团公司信息科学研究院 | Digital-to-analog converter modeling method and system and digital-to-analog converter |
| CN115062569A (en) * | 2022-08-17 | 2022-09-16 | 深圳市华杰智通科技有限公司 | Parallel acceleration system and method for millimeter wave chip design simulation EDA (electronic design automation) |
| CN115248998A (en) * | 2022-09-22 | 2022-10-28 | 济南新语软件科技有限公司 | SoC chip distributed simulation verification platform and method |
| CN115248998B (en) * | 2022-09-22 | 2023-01-03 | 济南新语软件科技有限公司 | SoC chip distributed simulation verification platform and method |
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Application publication date: 20161109 |