CN106059528A

CN106059528A - Length-variable single-rate FIR digital filter design method

Info

Publication number: CN106059528A
Application number: CN201610408897.0A
Authority: CN
Inventors: 徐伟
Original assignee: Xian Electronic Engineering Research Institute
Current assignee: Xian Electronic Engineering Research Institute
Priority date: 2016-06-12
Filing date: 2016-06-12
Publication date: 2016-10-26
Anticipated expiration: 2036-06-12
Also published as: CN106059528B

Abstract

The invention relates to a length-variable single-rate FIR digital filter design method. By means of the length-variable single-rate FIR digital filter design method, the order number of a digital filter can be rapidly changed; therefore, the method is particularly applied to an occasion, in which the working frequency of the digital filter is obviously greater than the input data sampling rate and the filter coefficient length needs to be rapid; in signal processing, pulse matching compression processing of multiple signals having different time widths can be effectively completed; and thus, the length-variable single-rate FIR digital filter design method has the characteristics of being high in expansibility and universality, convenient to debug and the like.

Description

A kind of adjustable length single-rate Finite Impulse Response filter method for designing

Technical field

The invention belongs to signal processing technology field, relate to a kind of adjustable length single-rate Finite Impulse Response filter.This Bright in existing radar digital signal processing, during multi-signal form Rapid Variable Design, pulse compression digital filter design is asked The solution that topic proposes, has the advantages that autgmentability is strong, highly versatile, efficiency are high, can be widely applied to signal processor and produces Product field.

Background technology

Finite Impulse Response filter is widely used in signal processor, such as the occasion such as low-pass filtering, pulse compression.Make Realizing process of pulse-compression by FIR filter, current FIR filter is fixed due to length, if divided with same wave filter Time bandwidth signals and hour bandwidth signals when processing big, simple use the method changing coefficient, it will cause hour bandwidth signals to process and prolong Increase late.If bandwidth signals and hour bandwidth signals, then can increase hardware resource when using two filter parallel to process big.For This, it is proposed that a kind of adjustable length single-rate Finite Impulse Response filter design.This design is put down based on FPGA hardware Platform, can be used for digital signal pulses compression and processes.This adjustable length feature of digital filtering utensil, is particularly well-suited to radar signal The application of bandwidth signals when datatron needs to process multiple.

Summary of the invention

Solve the technical problem that

Present invention mainly solves technical problem is that: FIR filter is fixed due to length, uses dumb.At needs In occasion wide during reason multi-signal, there is process and postpone the big or situation of the wasting of resources.

Technical scheme

A kind of adjustable length single-rate Finite Impulse Response filter method for designing, it is characterised in that comprise the steps:

Step 1: produce and store the coefficient for FIR filter, step is as follows:

Step 1a: use the method for both sides symmetry zero padding to expand filter coefficient, make filter coefficient length be equal to 2mn, Wherein m, n are integer, and require that expanding postfilter coefficient has even symmetry, and the working clock frequency of digital filter is defeated Enter m times of signal sampling frequency；

Step 1b: the first half data of filter coefficient be stored in the Rom of n, stores m coefficient in each Rom；

Step 2: producing the Data-Link for FIR filter, step is as follows:

Step 2a: by selector U, postpone to save R1 and postpone joint Rm to form the feedback loop Sm that the degree of depth is m；Wherein postpone joint Rm Being unified into by m group register stage, its list entries x (k) and output sequence y (k) relation are y (k)=x (k-m), and wherein k is integer； Selector U exports branch road, the otherwise lower branch road of output when control signal e is effective；

Step 2b: formed the feedback loop Tm that the degree of depth is m by the Re1 of selector U, delay joint Rm-1, R1 and band Enable Pin；Control Signal e processed connects selector U and the Re1 of band Enable Pin respectively；

Step 2c: Sm and n feedback loop Tm of n feedback loop is formed Data-Link: under wherein the output of feedback loop Sm connects The input of one feedback loop Sm, the output of last feedback loop Sm connects the input of first feedback loop Tm；

Step 3: producing control signal, step is as follows:

Step 3a: producing the cycle with the work clock of digital filter is control signal e of 1 for m width；

Step 3b: signal e is postponed 3 clocks and produces signal e1；

Step 3c: signal e1 is postponed 1 clock and produces signal e2；

Step 3d: signal e2 is postponed n clock and produces signal e3；

Step 4: coefficient and data are carried out arithmetical operation, and step is as follows:

Step 4a: be added corresponding for Sm with n the feedback loop Tm output of n feedback loop；

Step 4b: be added the coefficient being multiplied by again in step 1 in corresponding Rom；

Step 4c: the output carrying out each multiplier under signal e1 controls respectively adds up；

Step 4d: multichannel accumulation result is Serial output in order under lock-out pulse e1 controls；

Step 4e: under lock-out pulse e2 controls, serial data is added up；

Step 4f: latch accumulator output under lock-out pulse e3 controls, obtain result y.

When filter length is become 2mr from 2mn, wherein r is integer and less than n, only need to defeated by the r feedback loop Tm Enter signal and changed into the output of the r feedback loop Sm by the output of the r+1 feedback loop Tm, signal e2 to signal e3 is postponed simultaneously R is changed into by n.

Beneficial effect

The one adjustable length single-rate Finite Impulse Response filter method for designing that the present invention proposes, compared with prior art Relatively, have a characteristic that

1. filter process variable-length, uses motility higher.

2. being applicable to coefficient even symmetric filter, computational efficiency is high.

Accompanying drawing explanation

Fig. 1 is feedback loop Sm structure

Fig. 2 is feedback loop Tm structure

Fig. 3 is timing letter production method

Fig. 4 is filter function structure

Detailed description of the invention

In conjunction with embodiment, accompanying drawing, the invention will be further described:

See Fig. 1, use m level register stage joint group to become the delay joint Rm of a length of m, its list entries x (k) and output sequence Row y (k) relation is y (k)=x (k-m).The feedback loop Sm that the degree of depth is m is formed by selector U and delay joint R1, Rm.Wherein x is Data-in port, e is that selector controls input port, and y is data-out port, and selector U is defeated when control signal is effective Go out upper branch road, the otherwise lower branch road of output.

See Fig. 2, by selector U and delay joint Rm-1, R1, and the R1 of band Enable Pin, the composition degree of depth is the feedback loop of m Tm.Wherein x is data-in port, and e is that selector controls input port, and y is data-out port, and ye is state output end Mouthful, Re1 represents the delay joint R1 of band Enable Pin.

See Fig. 3, it is assumed that digital filter input data synchronizing signal be the cycle be m width be the pulse signal e of 1, right Signal e postpones 3 clocks and produces signal e1, signal e1 is postponed 1 clock and produces signal e2, signal e2 is postponed n clock Produce signal e3.

Seeing Fig. 4, Sm and n feedback loop Tm of n feedback loop is formed Data-Link, as n=3, structure is as shown in Figure 4. It is added, by corresponding for Sm with n the feedback loop Tm output of n feedback loop, the coefficient being multiplied by again in corresponding Rom, controls at lock-out pulse e1 The lower output carrying out each multiplier respectively adds up, multichannel accumulation result Serial output in order under lock-out pulse e1 controls, Under lock-out pulse e2 controls, serial data is added up, under lock-out pulse e3 controls, latch accumulator output, obtain result y.

Can realize by adjusting 2 parameters when dynamically changing filter length, one is working clock frequency and adopt The ratio of sample frequency, another is to postpone assistant warden connection number.

The wave filter of design in the present invention, when filter length is become 2mr from 2mn (r is integer and is less than n), only needs The input signal of the r feedback loop Tm is changed the output of the r feedback loop Sm into, simultaneously by the output of the r+1 feedback loop Tm Postpone to be changed into r by n to signal e2 to signal e3.

Claims

1. an adjustable length single-rate Finite Impulse Response filter method for designing, it is characterised in that comprise the steps:

Step 1: produce and store the coefficient for FIR filter, step is as follows:

Step 1a: use the method for both sides symmetry zero padding to expand filter coefficient, makes filter coefficient length be equal to 2mn, wherein M, n are integer, and require that expanding postfilter coefficient has even symmetry, and the working clock frequency of digital filter is input letter M times of number sample frequency；

Step 2: producing the Data-Link for FIR filter, step is as follows:

Step 2a: by selector U, postpone to save R1 and postpone joint Rm to form the feedback loop Sm that the degree of depth is m；Wherein postpone joint Rm by m Group register stage is unified into, and its list entries x (k) and output sequence y (k) relation are y (k)=x (k-m), and wherein k is integer；Choosing Select device U and export branch road, the otherwise lower branch road of output when control signal e is effective；

Step 2b: formed the feedback loop Tm that the degree of depth is m by the Re1 of selector U, delay joint Rm-1, R1 and band Enable Pin；Control letter Number e connects selector U and the Re1 of band Enable Pin respectively；

Step 2c: Sm and n feedback loop Tm of n feedback loop is formed Data-Link: wherein the output of feedback loop Sm connects the next one The input of feedback loop Sm, the output of last feedback loop Sm connects the input of first feedback loop Tm；

Step 3: producing control signal, step is as follows:

Step 3b: signal e is postponed 3 clocks and produces signal e1；

Step 3c: signal e1 is postponed 1 clock and produces signal e2；

Step 3d: signal e2 is postponed n clock and produces signal e3.

Step 4b: be added the coefficient being multiplied by again in step 1 in corresponding Rom,

Step 4c: the output carrying out each multiplier under signal e1 controls respectively adds up,

Step 4d: multichannel accumulation result is Serial output in order under lock-out pulse e1 controls,

Step 4e: under lock-out pulse e2 controls, serial data is added up,

A kind of adjustable length single-rate Finite Impulse Response filter method for designing, it is characterised in that: When filter length is become 2mr from 2mn, wherein r is integer and less than n, only need to by the input signal of the r feedback loop Tm by The output of the r+1 feedback loop Tm changes the output of the r feedback loop Sm into, postpones to be changed into by n to signal e2 to signal e3 simultaneously r。