CN105990332A - Thin film transistor substrate and display panel thereof - Google Patents
Thin film transistor substrate and display panel thereof Download PDFInfo
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- CN105990332A CN105990332A CN201510085288.1A CN201510085288A CN105990332A CN 105990332 A CN105990332 A CN 105990332A CN 201510085288 A CN201510085288 A CN 201510085288A CN 105990332 A CN105990332 A CN 105990332A
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Abstract
The invention discloses a thin film transistor substrate and a display panel thereof. The display panel includes the following components of: a substrate; a first metal layer which is arranged on the substrate and includes a gate and a gate line connected with the gate; a first insulation layer which is arranged on the first metal layer; a planarization layer which is arranged on the first insulation layer; an opening which is defined by the side wall of the planarization layer and the surface of the first insulation layer and is overlapped with the gate line; an active layer which is arranged on the opening and the planarization layer; and a second metal layer which is located on the active layer and includes a source contacting with the active layer and a data line connected with the source; and the planarization layer and the first insulation layer are located between the data line and the gate line.
Description
Technical field
The present invention relates to thin film transistor (TFT), and particularly relate to thin film transistor base plate and display.
Background technology
In current thin film transistor base plate processing technology, after forming grid and gate line, i.e. definition has
Active layer correspondence grid, using as channel layer.Being subsequently formed another metal level, it includes on active layer both sides
Source electrode and drain electrode, and be connected to the data wire of source electrode.Above-mentioned data wire and data wire overlapping only every
There is gate dielectric.In order to reduce the driving electric current of thin film transistor (TFT), the thickness of gate dielectric need to be reduced.
But gate dielectric is the thinnest, the electric capacity between data wire and gate line is the biggest and increases both confluces
Burden.In other words, said structure cannot reduce driving electric current and the reduction data wire of thin film transistor (TFT) simultaneously
And the electric capacity between gate line.
In sum, need new thin film transistor base plate at present badly, to reducing driving of thin film transistor (TFT)
During streaming current, it is possible to reduce the electric capacity between data wire and gate line.
Summary of the invention
The display floater that one embodiment of the invention provides, including: substrate；The first metal layer, is positioned at substrate
On, including grid, and connect the gate line of grid；First insulating barrier, is positioned on the first metal layer；
Planarization layer, is positioned on the first insulating barrier；Opening, by sidewall and the table of the first insulating barrier of planarization layer
Face is defined, opening and gate overlap；Active layer, is positioned on planarization layer and covers opening；And the
Two metal levels, are positioned on active layer, including the source electrode of contact active layer, and connect the data wire of source electrode；
Wherein planarization layer and the first insulating barrier are between data wire and gate line.
The thin film transistor base plate that one embodiment of the invention provides, including: substrate；The first metal layer, position
On substrate, including grid, and connect the gate line of grid；First insulating barrier, is positioned at the first metal
On layer；Planarization layer, is positioned on the first insulating barrier；Opening, by sidewall and first insulation of planarization layer
The surface of layer is defined, opening and gate overlap；Active layer, is positioned on planarization layer and covers opening；
And second metal level, it is positioned on active layer, including the source electrode of contact active layer, and connects source electrode
Data wire；Wherein planarization layer and the first insulating barrier are between data wire and gate line.
Accompanying drawing explanation
Figure 1A to Fig. 1 D is the processing technology sectional view of thin film transistor base plate in one embodiment of the invention；
Fig. 2 A to Fig. 2 D is the top view of corresponding Figure 1A to Fig. 1 D；
Fig. 3 A to Fig. 3 C is the processing technology section view of the thin film transistor base plate in one embodiment of the invention
Figure；
Fig. 4 A to Fig. 4 C is the top view of corresponding diagram 3A to Fig. 3 C；
Fig. 5 A and Fig. 5 B is the sectional view of thin film transistor base plate in the embodiment of the present invention；
Fig. 6 A to Fig. 6 B is the processing technology sectional view of thin film transistor base plate in one embodiment of the invention；
Fig. 7 A to Fig. 7 B is the top view of corresponding diagram 6A to Fig. 6 B；
Fig. 8 A to Fig. 8 C is the processing technology section view of the thin film transistor base plate in one embodiment of the invention
Figure；
Fig. 9 A to Fig. 9 C is the top view of corresponding diagram 8A to Fig. 8 C；
Figure 10 A to Figure 10 D is the processing technology section view of thin film transistor base plate in one embodiment of the invention
Figure；
Figure 11 A to Figure 11 D is the top view of corresponding diagram 10A to Figure 10 D；
Figure 12 A to Figure 12 D is the processing technology section view of thin film transistor base plate in one embodiment of the invention
Figure；
Figure 13 A to Figure 13 D is the top view of corresponding diagram 12A to Figure 12 D；
Figure 14 is the schematic diagram of display in one embodiment of the invention.
Symbol description
10 substrates
11 gate lines
11A grid
13,51 insulating barrier
15,15 ' planarization layer
17 openings
19 active layers
19 ' conductor metal oxide layers
21 data wires
21A source electrode
21B drains
31 etching stopping layers
33,103 contact hole
101 protective layers
1401 thin film transistor base plates
1403 display mediums
1405 opposite substrates
Detailed description of the invention
Figure 1A to Fig. 1 D is in one embodiment of the invention, the processing technology section view of thin film transistor base plate
Figure.Figure 1A to Fig. 1 D is respectively the sectional view at the dotted line of the top views such as Fig. 2 A to Fig. 2 D.It is worth
It is noted that the processing technology of thin film transistor base plate also can be completed by other modes, however it is not limited to following
Step.Additionally, being formed before thin film transistor base plate, among or can be carried out other afterwards additionally walk
Suddenly, to define other nonwoven fabric from filaments among or on thin film transistor base plate.First, formed metal level in
On substrate 10, then patterned metal layer is to define gate line 11 and coupled grid 11A.At this
Inventing in an embodiment, substrate 10 can be glass, plastic cement or other common baseplate materials.At this
Inventing in an embodiment, metal level can be metal or the conjunction of the single or multiple lift combinations such as molybdenum, aluminum, copper, titanium
Gold, its forming method can be physical vaporous deposition (PVD), sputtering method, or the like.Patterning
The method of metal level can be lithographic fabrication process and etching process.Lithographic fabrication process comprises following step
Rapid: painting photoresist such as spin-coating method, soft baking, alignment of photomask, exposure, postexposure bake,
Development, rinsing, drying such as hard baking, other suitable fabrication technique or combinations of the above.Additionally, light
The step of exposure carving processing technology can use additive method instead, the most unglazed mask lithography, electron-beam direct writing,
Or ion beam direct write.After lithographic fabrication process, can be etched processing technology such as dry ecthing, wet etching,
Or combinations of the above is with patterned metal layer.Removable photoresist pattern after etching process,
Its method can be ashing, divest or combinations of the above.
Then insulating barrier 13 and planarization layer 15 are sequentially formed on gate line 11 with grid 11A.Absolutely
Edge layer 13 can be organo-siloxane compound, or inorganic such as silicon nitride, silicon oxide, silicon oxynitride,
Carborundum, aluminium oxide, hafnium oxide or the multiple structure of above-mentioned material, its forming method can be chemistry gas
Phase sedimentation (CVD) such as plasma enhancing formula CVD (PECVD), low pressure chemical vapor deposition (LPCVD), secondary
Atmospheric pressure cvd (SACVD), physical vapour deposition (PVD) (PVD) or similar techniques.Implement in the present invention one
In example, the thickness of insulating barrier 13 betweenBetween.If the thickness of insulating barrier 13 is the thinnest,
Though then transistor charging ability is high but gate insulator electric leakage is too high.If the thickness of insulating barrier 13 is blocked up,
Then transistor charging ability is too low.In an embodiment of the present invention, planarization layer 15 can be organic insulation
Layer material or inorganic insulating layer material, its forming method can be physical property deposition or chemical gaseous phase deposition.
In an embodiment of the present invention, the composition of planarization layer 15 is different from insulating barrier 13.Real in the present invention one
Execute in example, the thickness of planarization layer 15 betweenBetween.If the thickness of planarization layer 15
Spend thin, then the distance between the data wire and the gate line 11 that are subsequently formed is too short, and cannot effectively drop
Electric capacity between low data wire and gate line 11.If the thickness of planarization layer 15 is blocked up, then affect its figure
Case difficulty.Must it should be noted that at this, the top view of Fig. 2 A eliminates insulating barrier 13 and planarization
Layer 15 is to simplify accompanying drawing.
Then, as shown in Figure 1B Yu Fig. 2 B, patterning planarization layer 15 is to form opening 17, to expose
The upper surface of the insulating barrier 13 of corresponding grid 11A.The method of above-mentioned formation opening 17 can be photoetching making
Technique with etching process it has been observed that be not repeated herein.
Then, as shown in Fig. 1 C and Fig. 2 C, it is formed with active layer after said structure, is patterned with active layer
To define active layer 19 in the sidewall of opening 17 and bottom.As shown in Figure 1 C, active layer 19 can be bigger
In opening 17, i.e. extend on the surface of part planarization layer 15.In an embodiment of the present invention, have
Active layer 19 can be polysilicon or metal-oxide semiconductor (MOS) such as indium gallium zinc oxide (IGZO).Active layer
Forming method can be CVD such as PECVD, LPCVD or SACVD, physics and vapour deposition (PVD),
Solution synthesis mode deposition, or the like.It should be noted that when active layer 19 is burning
During thing quasiconductor, planarization layer 15 can not be silicon nitride or the insulant rich in hydrogen, to avoid in system
The active layer 19 of the sidewall and bottom making to will be located in opening 17 in technique is converted to conductor.Pattern active
Layer method can be lithographic fabrication process with etching process it has been observed that be not repeated herein.
Then, as shown in Fig. 1 D and Fig. 2 D, formation metal level is on said structure, then pattern metal
Layer is to define data wire 21, source electrode 21A and drain electrode 21B.In an embodiment of the present invention, above-mentioned gold
Belonging to the metal or alloy that layer can be the single or multiple lift combinations such as molybdenum, aluminum, copper, titanium, its forming method can be
Physical vapour deposition (PVD) (PVD) or sputter.The method of patterned metal layer can be lithographic fabrication process and etching
Processing technology is it has been observed that be not repeated herein.Above-mentioned data wire 21 is separated with smooth with gate line 11 overlapping
Change layer 15 and insulating barrier 13.Above-mentioned source electrode 21A is connected to data wire 21.Source electrode 21A and drain electrode 21B
Lay respectively on the active layer 19 in the opposite side walls of opening 17 and be not attached to each other.It should be noted that
Do not extend on the part active layer 19 on planarization layer 15 if source electrode 21A is only positioned at drain electrode 21B
On active layer 19 to the sidewall of opening 17, then the passage length (channel length) of active layer 19
By long and be difficult to drive.
Fig. 3 A to Fig. 3 C is in one embodiment of the invention, the processing technology section view of thin film transistor base plate
Figure.Fig. 3 A to Fig. 3 C is respectively the sectional view at the dotted line of the top views such as Fig. 4 A to Fig. 4 C.Complete
After becoming the structure of Fig. 1 C and Fig. 2 C, form etching stopping layer 31 thereon to form Fig. 3 A and Fig. 4 A
Shown structure.In an embodiment of the present invention, etching stopping layer 31 can be silicon oxide, aluminium oxide,
The inorganic insulation layers such as titanium oxide, its forming method can be chemical gaseous phase deposition, ald, physics sink
The method such as long-pending.In an embodiment of the present invention, the thickness of etching stopping layer 31 between
Between.If the thickness of etching stopping layer 31 is the thinnest, then inadequate for active layer protective capability.If etching
The thickness of stop-layer 31 is blocked up, then affect the processing technology time and patterning difficulty increases.Required at this
Illustrating, the top view of Fig. 3 A eliminates insulating barrier 13, planarization layer 15 and etching stopping layer
31 to simplify accompanying drawing.
Then as shown in Fig. 3 B and Fig. 4 B, patterned etch stop 31 to form contact hole 33, with
Expose the active layer 19 on the sidewall of opening 17 and the part active layer 19 on the bottom of opening 17.On
Stating and form the method for contact hole 33 can be lithographic fabrication process and etching process it has been observed that at this not
Repeat.
Then, as shown in Fig. 3 C and Fig. 4 C, formation metal level is on said structure, then pattern metal
Layer is to define data wire 21, source electrode 21A and drain electrode 21B.The composition of above-mentioned metal level and forming method
With aforementioned, and the method for patterned metal layer can be lithographic fabrication process with etching process it has been observed that
It is not repeated herein.Above-mentioned data wire 21 and gate line 11 overlapping are separated with etching stopping layer 31, planarization
Layer 15 and insulating barrier 13.Above-mentioned source electrode 21A is connected to data wire 21.Source electrode 21A and drain electrode 21B
Via contact hole 33, contact is positioned in the opposite side walls of opening 17 respectively active layer 19 and the most not phase
Even.The nonwoven fabric from filaments being separated by between data wire 21 and the gate line 11 of this embodiment is more, therefore can enter one
Step reduces electric capacity between the two.On the other hand, the source electrode 21A bottom opening 17 with drain electrode 21B it
Between be separated with etching stopping layer 31, can avoid further because processing technology error causes both to be electrical connected.
Fig. 5 A is in one embodiment of the invention, the sectional view of thin film transistor base plate.Knot in Fig. 5 A
Structure is similar with the structure of Fig. 1 D, difference formed after opening 17 be formed with active layer 19 before, be initially formed
Another insulating barrier 51.There is between insulating barrier 51 and active layer 19 preferably interfacial property.In the present invention
In one embodiment, insulating barrier 51 can be silicon oxide, aluminium oxide or titanium oxide, and its forming method can be
The methods such as chemical gaseous phase deposition, ald or physical property deposition.In an embodiment of the present invention,
The thickness of insulating barrier 51 betweenBetween.If the thickness of insulating barrier 51 is the thinnest, then insulate
Layer electric leakage is too high.If the thickness of insulating barrier 51 is blocked up, then affect transistor charging ability.
Fig. 5 B is in one embodiment of the invention, the sectional view of thin film transistor base plate.Knot in Fig. 5 B
Structure is similar with the structure of Fig. 3 C, difference formed after opening 17 be formed with active layer 19 before, be initially formed
Another insulating barrier 51.There is between insulating barrier 51 and active layer 19 preferably interfacial property.As for insulation
The composition of layer 51, forming method, are not repeated herein with aforementioned with thickness.
Fig. 6 A to Fig. 6 B is in one embodiment of the invention, the processing technology section view of thin film transistor base plate
Figure.Fig. 6 A to Fig. 6 B is respectively the sectional view at the dotted line of the top views such as Fig. 7 A to Fig. 7 B.Fig. 6 A
Structure similar with the structure of Fig. 1 C, difference is metal-oxide semiconductor (MOS) at the active layer 19 of Fig. 6 A
Such as IGZO, it includes the Part I on the bottom being positioned at opening 17, and is positioned at planarization layer
Part II on 15, and the planarization layer 15 of Fig. 1 C changes into being changed by metal-oxide semiconductor (MOS)
Planarization layer 15 ' for conductor.In an embodiment of the present invention, planarization layer 15 ' be silicon nitride or rich in
The insulating barrier of hydrogen, its hydrogen content need to be more than 10 atom %.Consequently, it is possible to be formed on planarization layer 15 '
The Part II of active layer 19 be converted into conductor metal oxide layer 19 '.Must it should be noted that at this,
The top view of Fig. 7 A eliminates insulating barrier 13 with planarization layer 15 ' to simplify accompanying drawing.
Then, as shown in Fig. 6 B and Fig. 7 B, formation metal level is on said structure, then pattern metal
Layer is to define data wire 21, source electrode 21A and drain electrode 21B.The composition of above-mentioned metal level and forming method
With aforementioned, and the method for patterned metal layer can be lithographic fabrication process with etching process it has been observed that
It is not repeated herein.Above-mentioned data wire 21 is separated with planarization layer 15 ' and insulating barrier with gate line 11 overlapping
13.Above-mentioned source electrode 21A is connected to data wire 21.Source electrode 21A lays respectively at active layer with drain electrode 21B
The conductor metal oxide layer 19 ' of 19 both sides is upper and is not attached to each other.Due to having on planarization layer 15 '
Active layer 19 has been converted into conductor metal oxide layer 19 ', and source electrode 21A only needs to contact with drain electrode 21B
Conductor metal oxide layer 19 ' on planarization layer 15 ', without extending in opening 17, can enter one
Step reduces the size of opening 17 and avoids because processing technology error causes both to be electrical connected.
Fig. 8 A to Fig. 8 C is in one embodiment of the invention, the processing technology section view of thin film transistor base plate
Figure.Fig. 8 A to Fig. 8 C is respectively the sectional view at the dotted line of the top views such as Fig. 9 A to Fig. 9 C.Complete
After becoming the structure of Fig. 6 A and Fig. 7 A, form etching stopping layer 31 thereon to form Fig. 8 A and Fig. 9 A
Shown structure.The composition of etching stopping layer 31, forming method and thickness, with aforementioned, are not gone to live in the household of one's in-laws on getting married at this
State.Should be noted that at this, the top view of Fig. 9 A eliminate insulating barrier 13, planarization layer 15 ',
With etching stopping layer 31 to simplify accompanying drawing.
Then as shown in Fig. 8 B and Fig. 9 B, patterned etch stop 31 to form contact hole 81, with
Expose the conductor metal oxide layer 19 ' on planarization layer 15 '.The method of above-mentioned formation contact hole 81 can
For lithographic fabrication process with etching process it has been observed that be not repeated herein.
Then, as shown in Fig. 8 C and Fig. 9 C, formation metal level is on said structure, then pattern metal
Layer is to define data wire 21, source electrode 21A and drain electrode 21B.The composition of above-mentioned metal level and forming method
With aforementioned, and the method for patterned metal layer can be lithographic fabrication process with etching process it has been observed that
It is not repeated herein.Above-mentioned data wire 21 and gate line 11 overlapping are separated with etching stopping layer 31, planarization
Layer 15 ' and insulating barrier 13.Above-mentioned source electrode 21A is connected to data wire 21.Source electrode 21A and drain electrode 21B
Via contact hole 81, contact is positioned at the gold on the planarization layer 15 ' on the two opposite sides of opening 17 respectively
Belong to oxide conductor layer 19 ' and be not attached to each other.Between data wire 21 and the gate line 11 of this embodiment
The nonwoven fabric from filaments being separated by is more, therefore can reduce electric capacity between the two further.On the other hand, source electrode 21A
It is not required to extend in opening 17 with drain electrode 21B, the size of opening 17 can be reduced further and avoid because of system
Both are caused to be electrical connected as fabrication error.
Figure 10 A to Figure 10 D is in one embodiment of the invention, and the processing technology of thin film transistor base plate is cutd open
View.Figure 10 A to Figure 10 D is respectively the sectional view at the dotted line of the top views such as Figure 11 A to Figure 11 D.
Patterned etch stop 31 after the structure completing Fig. 3 A, at least retains etching stopping layer 31 in opening
On the active layer 19 of the bottom of mouth 17 as shown in Figure 10 A.Must it should be noted that at this, Figure 11 A's
Top view eliminates insulating barrier 13 with planarization layer 15 to simplify accompanying drawing.
The most as shown in Figure 10 B, deposition protective layer 101 is on said structure.In this embodiment, have
Active layer 19 is metal-oxide semiconductor (MOS).Above-mentioned etching stopping layer 31 can not be for nitridation with insulating barrier 13
Silicon or the insulating barrier rich in hydrogen, to avoid the active layer 19 bottom by opening 17 to be converted to conductor.Above-mentioned
Protective layer 101 is silicon nitride or the insulating barrier rich in hydrogen, and its forming method can be chemical gaseous phase deposition or thing
The methods such as rationality deposition.Above-mentioned protective layer 101 can make other active layers 19 turns beyond bottom opening 17
It is changed to conductor metal oxide layer 19 '.
Then, as shown in Figure 10 C and Figure 11 C, form contact hole 103 and pass protective layer 101, to expose
Conductor metal oxide layer 19 ' on planarization layer 15.The method of above-mentioned formation contact hole 103 can be light
Carve processing technology with etching process it has been observed that be not repeated herein.
Then, as shown in Figure 10 D and Figure 11 D, formation metal level is on said structure, then patterned gold
Belong to layer to define data wire 21, source electrode 21A and drain electrode 21B.The composition of above-mentioned metal level and formation side
Method is with aforementioned, and the method for patterned metal layer can be that lithographic fabrication process is the most front with etching process
State, be not repeated herein.Above-mentioned data wire 21 and gate line 11 overlapping are separated with protective layer 101, smooth
Change layer 15 and insulating barrier 13.Above-mentioned source electrode 21A is connected to data wire 21.Source electrode 21A and drain electrode
The conductor metal oxide layer 19 ' that 21B contacts both sides respectively via contact hole 103 above and is not attached to each other.
Between bottom protective layer 101 and opening 17, there is etching stopping layer 31, can avoid opening 17
The active layer 19 of bottom is converted to conductor.
Figure 12 A to Figure 12 D is in one embodiment of the invention, and the processing technology of thin film transistor base plate is cutd open
View.Figure 12 A to Figure 12 D is respectively the sectional view at the dotted line of the top views such as Figure 13 A to Figure 13 D.
Patterned etch stop 31 after the structure completing Fig. 3 A, to retain etching stopping layer 31 in opening
On the active layer 19 of the bottom of 17, and on other regions beyond active layer 19, as Figure 12 A with
Shown in Figure 13 A.Must it should be noted that at this, the top view of Figure 13 A eliminates insulating barrier 13 with smooth
Change layer 15 to simplify accompanying drawing.
The most as shown in Figure 12 B, deposition protective layer 101 is on said structure.In this embodiment, have
Active layer 19 is metal-oxide semiconductor (MOS).Above-mentioned etching stopping layer 31 can not be for nitridation with insulating barrier 13
Silicon or the insulating barrier rich in hydrogen, to avoid the active layer 19 bottom by opening 17 to be converted to conductor.Above-mentioned
Protective layer 101 is silicon nitride or the insulating barrier rich in hydrogen, and its forming method can be chemical gaseous phase deposition or thing
The methods such as rationality deposition.Above-mentioned protective layer 101 can make other active layers 19 turns beyond bottom opening 17
It is changed to conductor metal oxide layer 19 '.
Then as shown in Figure 12 C and Figure 13 C, patterning protective layer 101 to form contact hole 103, with
Expose the conductor metal oxide layer 19 ' on planarization layer 15.The method of above-mentioned formation contact hole 103 can
For lithographic fabrication process with etching process it has been observed that be not repeated herein.
Then, as shown in Figure 12 D and Figure 13 D, formation metal level is on said structure, then patterned gold
Belong to layer to define data wire 21, source electrode 21A and drain electrode 21B.The composition of above-mentioned metal level and formation side
Method is with aforementioned, and the method for patterned metal layer can be that lithographic fabrication process is the most front with etching process
State, be not repeated herein.Above-mentioned data wire 21 and gate line 11 overlapping are separated with protective layer 101, etching
Stop-layer 31, planarization layer 15 and insulating barrier 13.Above-mentioned source electrode 21A is connected to data wire 21.Source
Pole 21A and drain electrode 21B contacts the conductor metal oxide layer 19 ' of both sides respectively via contact hole 103
And be not attached to each other.The nonwoven fabric from filaments being separated by between data wire 21 and the gate line 11 of this embodiment is more,
Therefore electric capacity between the two can be reduced further.
Above-mentioned Fig. 1 D, Fig. 3 C, Fig. 5 A, Fig. 5 B, Fig. 6 B, Fig. 8 C, Figure 10 D and Figure 12 D
The drain electrode 21B of shown thin film transistor base plate can be connected with pixel electrode further, to control pixel region
Light and shade.Pixel region can further include common electrode.Pixel electrodes is normal with the design of common electrode
See thin film transistor base plate, be not repeated herein.
Figure 14 is the sectional view of the display of one embodiment of the invention.In fig. 14, display includes thin
Film transistor substrate 1401, opposite substrate 1405 and be sandwiched in thin film transistor base plate 1401 with to base
Display medium 1403 between plate 1405.Thin film transistor base plate 1401 can be Fig. 1 D, Fig. 3 C, figure
Thin film transistor base plate shown in 5A, Fig. 5 B, Fig. 6 B, Fig. 8 C, Figure 10 D or Figure 12 D, aobvious
Show that medium 1030 can be liquid crystal layer or organic luminous layer.Opposite substrate 1020 can be colored optical filtering substrates or
It it is transparency carrier.
Claims (13)
1. a display floater, including:
Substrate；
The first metal layer, is positioned on this substrate, including grid, and connects the gate line of this grid；
First insulating barrier, is positioned on this first metal layer；
Planarization layer, is positioned on this first insulating barrier；
Opening, is defined by the surface of the sidewall of this planarization layer with this first insulating barrier, this opening with should
Gate overlap；
Active layer, is positioned on this planarization layer and covers this opening；And
Second metal level, is positioned on this active layer, and including contacting the source electrode of this active layer, and connect should
The data wire of source electrode；
Wherein this planarization layer and this first insulating barrier are between this data wire and this gate line.
2. display floater as claimed in claim 1, wherein, this second metal level contacts on this opening
This active layer.
3. display floater as claimed in claim 2, also includes the second insulating barrier, is positioned at this planarization layer
On, and this active layer is positioned on this second insulating barrier, and this second insulating barrier, this planarization layer and should
First insulating barrier is between this data wire and this gate line.
4. display floater as claimed in claim 2, also includes etching stopping layer, be positioned at this active layer with
On this planarization layer, and this etching stopping layer has multiple contact hole and exposes the part on this opening this is active
Layer, wherein this source electrode is via this active layer of contact of those contact holes,
Wherein this etching stopping layer, this planarization layer and this first insulating barrier are positioned at this data wire and these grid
Between polar curve.
5. display floater as claimed in claim 4, also includes the second insulating barrier, is positioned at this planarization layer
On, and this active layer is positioned on this second insulating barrier, and this etching stopping layer, this second insulating barrier, should
Planarization layer and this first insulating barrier are between this data wire and this gate line.
6. display floater as claimed in claim 1, wherein, this active layer comprises and is positioned at this first insulation
Part I on the surface of layer, and it is positioned at the Part II on this planarization layer, wherein, this is second years old
Metal level contacts the Part II of this active layer.
7. display floater as claimed in claim 6, wherein this planarization layer is by silicon nitride or rich in hydrogen
Insulant formed.
8. display floater as claimed in claim 6, also includes etching stopping layer, be positioned at this active layer with
On this planarization layer, and this etching stopping layer has second of this active layer of multiple contact hole exposed portion
Point, wherein this source electrode is via the Part II of this active layer of contact of those contact holes,
Wherein this etching stopping layer, this planarization layer and this first insulating barrier are positioned at this data wire and these grid
Between polar curve.
9. display floater as claimed in claim 6, also includes:
Etching stopping layer, is positioned on this active layer；And
Protective layer, is positioned on this etching stopping layer, the Part II of this active layer and this planarization layer,
And this protective layer has the Part II of this active layer of multiple contact hole exposed portion, this source electrode is via those
The Part II of one this active layer of contact of contact hole；
Wherein this protective layer, this planarization layer and this first insulating barrier are positioned at this data wire and this gate line
Between.
10. display floater as claimed in claim 9, wherein this protective layer is by silicon nitride or rich in hydrogen
Insulant formed.
11. display floaters as claimed in claim 9, wherein this etching stopping layer is also located at this planarization
On layer, and this protective layer, this etching stopping layer, this planarization layer and this first insulating barrier are positioned at this number
According between line and this gate line.
12. display floaters as claimed in claim 1, also include:
Opposite substrate；And
Display medium, between this substrate and this opposite substrate.
13. 1 kinds of thin film transistor base plates, including:
Substrate；
The first metal layer, is positioned on this substrate, including grid, and connects the gate line of this grid；
First insulating barrier, is positioned on this first metal layer；
Planarization layer, is positioned on this first insulating barrier；
Opening, is defined by the surface of the sidewall of this planarization layer with this first insulating barrier, this opening with should
Gate overlap；
Active layer, is positioned on this planarization layer and covers this opening；And
Second metal level, is positioned on this active layer, and including contacting the source electrode of this active layer, and connect should
The data wire of source electrode；
Wherein this planarization layer and this first insulating barrier are between this data wire and this gate line.
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| CN201510085288.1A CN105990332B (en) | 2015-02-17 | 2015-02-17 | Thin film transistor base plate and its display panel |
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| CN201510085288.1A CN105990332B (en) | 2015-02-17 | 2015-02-17 | Thin film transistor base plate and its display panel |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108022935A (en) * | 2016-11-01 | 2018-05-11 | 群创光电股份有限公司 | Display device |
| CN108155201A (en) * | 2016-12-02 | 2018-06-12 | 群创光电股份有限公司 | Display device |
| CN109493726A (en) * | 2018-12-04 | 2019-03-19 | 武汉华星光电半导体显示技术有限公司 | Display panel |
| US10726758B2 (en) | 2018-12-04 | 2020-07-28 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel |
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| CN108022935A (en) * | 2016-11-01 | 2018-05-11 | 群创光电股份有限公司 | Display device |
| US10732475B2 (en) | 2016-11-01 | 2020-08-04 | Innolux Corporation | Thin film transistor substrate and display device using the same |
| CN108022935B (en) * | 2016-11-01 | 2021-05-07 | 群创光电股份有限公司 | Display device |
| CN108155201A (en) * | 2016-12-02 | 2018-06-12 | 群创光电股份有限公司 | Display device |
| CN108155201B (en) * | 2016-12-02 | 2020-09-22 | 群创光电股份有限公司 | Display device |
| CN109493726A (en) * | 2018-12-04 | 2019-03-19 | 武汉华星光电半导体显示技术有限公司 | Display panel |
| US10726758B2 (en) | 2018-12-04 | 2020-07-28 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel |
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| CN105990332B (en) | 2019-11-05 |
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