CN105977264A - Double-gate array substrate and manufacturing method thereof, display panel and display device - Google Patents
Double-gate array substrate and manufacturing method thereof, display panel and display device Download PDFInfo
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- CN105977264A CN105977264A CN201610512345.4A CN201610512345A CN105977264A CN 105977264 A CN105977264 A CN 105977264A CN 201610512345 A CN201610512345 A CN 201610512345A CN 105977264 A CN105977264 A CN 105977264A
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- 239000000758 substrate Substances 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000011800 void material Substances 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 14
- 230000005540 biological transmission Effects 0.000 claims description 9
- 238000009826 distribution Methods 0.000 claims description 7
- 238000013499 data model Methods 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 5
- 238000002788 crimping Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention provides a double-gate array substrate and a manufacturing method thereof, a display panel and a display device. In the array substrate, gate lines can receive gate driving signals transmitted by a gate driving circuit via a plurality of guide lines which are on the same layer and in the same direction as data wires, and when the array substrate is applied to the display device, only a fan-out area of the guide lines is set on the side of the array substrate in the row direction, so that the space occupied by two sides of the display device is effectively reduced, and then a borderless design of the display device can be realized.
Description
Technical field
The present invention relates to Display Technique field, especially relate to a kind of double grid array base palte and system thereof
Make method, display floater, display device.
Background technology
The display device of main flow typically uses the mode of turntable driving, i.e. raster data model electricity at present
Road applies signal on the grid line that each row sub-pixel is connected successively makes each row sub-pixel lead successively
Logical, and use data drive circuit to apply data on the data wire that each row sub-pixel is connected
Voltage thus data voltage corresponding for each sub-pixel is written in each sub-pixel, complete
Corresponding light emitting control.
Owing to the cost of data drive circuit is more high than gate driver circuit, prior art
In propose a kind of double grid display device, as it is shown in figure 1, include some column data lines and
Several rows grid line.Wherein, every two row grid lines control the unlatching of a line sub-pixel unit, each
Column data line writes data voltage in the sub-pixel unit of the unlatching of its adjacent both sides.This
The number of desired data line just can be reduced half by sample.Additionally, each grid line passes through grid line
Flexibly connect circuit 1 ' and connect gate driver circuit, so that gate driver circuit provides for grid line
Drive signal.Each data wire flexibly connects circuit 2 ' by data wire and connects data-driven electricity
Road, so that data drive circuit provides data voltage signal for data wire.
But as it is shown in figure 1, in double grid display device, owing to grid line is in display device
Fan-out at side frame, thus be accordingly used in the grid line crimping grid line and just flexibly connects circuit 1 '
Need to be arranged in the side frame of display device, in thus causing the side frame of display device
A part of space flexibly connected circuit 1 ' by grid line and take, thus be unfavorable for display device
Rimless designs.
Summary of the invention
It is an object of the invention to, solve in existing double grid display device grid line at side frame
Fan-out, correspondingly makes grid line flexibly connect circuit and is arranged in the side frame of display device, lead
Cause a part of space in side frame to be flexibly connected circuit by grid line and take, be unfavorable for display device
The problem of Rimless design.
For solving the problems referred to above, the invention provides a kind of double grid array base palte and making side thereof
Method, display floater, display device.
First aspect, the invention provides a kind of double grid array base palte, including the son of array distribution
Pixel cell, some data line and some grid lines,
Wherein, two grid lines, adjacent two data it are provided with between adjacent rows sub-pixel unit
Comprising two row sub-pixel unit between line, each data line is in the sub-pixel unit position of every a line
The place of putting connects two both sides being positioned at this data wire and all adjacent with this data wire sub-pixel list
Unit；
Described array base palte also includes some the guide wires arranged with data wire with layer, each
Guide wire is correspondingly arranged at first void area, and described first void area is adjacent two
Void area between two row sub-pixel unit between data line, each guide wire all passes through
Transfer hole is corresponding connected with a grid line, for corresponding grid line transmission signal.
Alternatively,
Described array base palte also includes some public electrode wires, each public electrode wire correspondence
It is arranged in first void area；And first void area at public electrode wire place with lead
First void area at lead-in wire place is different；
Public electrode, described public electrode and described common electrical it is also formed with on described array base palte
Polar curve is connected by via.
Alternatively, each bar guide wire and pieces of data line are in the same area fan-out.
Alternatively, the fan-out area of each bar guide wire and the fan-out area of pieces of data line are many
Individual, and the fan-out area of each bar guide wire is alternately arranged with the fan-out area of pieces of data line.
Second aspect, the invention provides the manufacture method of a kind of double grid array base palte, including:
Array base palte is formed the sub-pixel unit of array distribution, if some data line and
Dry bar grid line；Wherein, between adjacent rows sub-pixel unit, it is provided with two grid lines, adjacent two
Comprising two row sub-pixel unit between data line, each data line is at the sub-pixel of every a line
Two both sides being positioned at this data wire and all adjacent with this data wire is connected at cell position
Pixel cell；
Described array base palte is also formed with some the guide wires arranged with layer with data wire,
Each guide wire is correspondingly arranged at first void area, and described first void area is
Void area between two row sub-pixel unit between adjacent two data line, each guide wire
All corresponding connected with a grid line by transfer hole, for corresponding grid line transmission grid letter
Number.
Alternatively, described array base palte is also formed with some public electrode wires, each
Public electrode wire is correspondingly formed in first void area；And the of public electrode wire place
One void area is different from first void area at guide wire place；
Described array base palte is also formed with public electrode, described public electrode and described public
Electrode wires is connected by via.
The third aspect, the invention provides a kind of display floater, including double grid battle array described above
Row substrate.
Fourth aspect, a kind of display device, including display floater described above.
Alternatively, described double grid array base palte is each bar guide wire with pieces of data line in same district
The array base palte of territory fan-out；Described display device also includes gate driver circuit, data-driven electricity
Road and flexibly connect circuit；Described gate driver circuit and described data drive circuit are by identical
The circuit that flexibly connects be connected with each bar guide wire on array base palte or pieces of data line respectively.
Alternatively, described double grid array base palte is fan-out area and the pieces of data of each bar guide wire
The fan-out area of line is multiple, and the fan of the fan-out area of each bar guide wire and pieces of data line
Go out the array base palte that region is alternately arranged；Described display device also includes gate driver circuit, number
According to drive circuit and flexibly connect circuit；Described gate driver circuit and described data drive circuit
By different flexibly connect circuit respectively with each bar guide wire on array base palte or each bar number
It is connected according to line；Wherein, what gate driver circuit connected flexibly connects circuit and data drive circuit
Connect to flexibly connect circuit alternately arranged.
In the array base palte that the embodiment of the present invention provides, grid line can pass through some and data wire
The raster data model of gate driver circuit transmission is received with layer and guide wire equidirectional with data wire
Signal so that when this array base palte is applied to display device, only need to be on array base palte line direction
Side edge the fan-out area of guide wire is set, effectively reduce what display device both sides took
Space, thus it is advantageously implemented the Rimless design of display device.
Accompanying drawing explanation
By inventive feature information and advantage, accompanying drawing can be more clearly understood from reference to accompanying drawing
It is schematic and should not be construed as the present invention is carried out any restriction, in the accompanying drawings:
Fig. 1 is the display device structure schematic diagram comprising double grid array base palte in prior art；
The array base-plate structure schematic diagram that Fig. 2 provides for embodiment of the present invention；
The structural representation of a kind of display device that Fig. 3 provides for embodiment of the present invention；
The structural representation of the another kind of display device that Fig. 4 provides for embodiment of the present invention.
Detailed description of the invention
In order to be more clearly understood that the above-mentioned purpose of the present invention, feature and advantage, knot below
Close the drawings and specific embodiments the present invention is further described in detail.Need explanation
It is that, in the case of not conflicting, the feature in embodiments herein and embodiment can be mutual
Combination.
Elaborate a lot of detail in the following description so that fully understanding the present invention, but
It is that the present invention can implement to use other to be different from other modes described here, therefore,
Protection scope of the present invention is not limited by following public specific embodiment.
First aspect, embodiment of the present invention provides a kind of double grid array base palte, including array
The sub-pixel unit of distribution, some data line and some grid lines.
Wherein, two grid lines, adjacent two data it are provided with between adjacent rows sub-pixel unit
Comprising two row sub-pixel unit between line, each data line is in the sub-pixel unit position of every a line
The place of putting connects two both sides being positioned at this data wire and all adjacent with this data wire sub-pixel list
Unit.
This double grid array base palte also includes some the guide wires arranged with data wire with layer, each
Bar guide wire is correspondingly arranged at first void area.Wherein, the first interstice coverage here
Territory is the void area between adjacent two data line between two row sub-pixel unit.Additionally, it is every
Article one, guide wire is all corresponding connected with a grid line by transfer hole, for passing to corresponding grid line
Defeated signal.
In the array base palte that the embodiment of the present invention provides, grid line can pass through some and data wire
The raster data model of gate driver circuit transmission is received with layer and guide wire equidirectional with data wire
Signal so that when this array base palte is applied to display device, only need to be on array base palte line direction
Side edge the fan-out area of guide wire is set, effectively reduce what display device both sides took
Space, thus it is advantageously implemented the Rimless design of display device.
In actual applications, sub-pixel unit here can be red sub-pixel unit or green
Sub-pixel unit or blue subpixels unit.
In the specific implementation, the structure of above-mentioned double grid array base palte may show as multiple difference
Form.Below in conjunction with the accompanying drawings some of which embodiment is specifically described.
See Fig. 2, if the array base palte shown in Fig. 2 include array distribution sub-pixel unit P and
Dry bar grid line G.Wherein, two grid line G it are provided with between adjacent rows sub-pixel unit P.Right
For every a line sub-pixel unit P, a wherein grid line adjacent with this row sub-pixel unit P
Connecting the even column pixels unit in this row sub-pixel unit P, another grid line connects this row
Odd column pixel unit in pixel cell P, so that this row sub-pixel unit P is at these two
The moment should opened in each frame under the co-controlling of grid line opens.Such as, in Fig. 2
The first row sub-pixel unit P by grid line G1 and G2 co-controlling, the second row sub-pixel unit P by
Grid line G3 and G4 co-controlling.Meanwhile, the array base palte shown in Fig. 2 also includes some data
Line D.Wherein, two row sub-pixel unit P, each number are comprised between adjacent two data line D
Two sub-pixel unit P being adjacent are connected, for opening with sub-pixel unit P according to line D
Shi Xiangqi inputs data voltage.
Additionally, this double grid array base palte also includes some the guide wires arranged with data wire with layer
L.Wherein, two row that each guide wire L is correspondingly arranged between adjacent two data line D
At void area between pixel cell P.Each guide wire L is all by transfer hole O and one
Grid line G correspondence is connected, and such as guide wire L1 is connected with grid line G1 by transfer hole O1, thus
Make guide wire L to the grid line G of each correspondence under the control of its gate driver circuit connected
Transmission signal.
It is understood that when above-mentioned array base palte is applied in display device, due to grid line
It is connected with gate driver circuit by guide wire, therefore has only to the fan-out line of guide wire
It is connected with gate driver circuit and can realize gate driver circuit and transmit signal to grid line.And guide
Arranging in line direction same with data wire again, therefore guide wire can be fanned in the side of data wire fan-out
Go out, thus make the side edge of display device without arranging the fan-out area of grid line again, thus
Be conducive to the Rimless design of display device.
In the specific implementation, the array base palte that the embodiment of the present invention provides can also include some
Public electrode wire.See Fig. 2, in the array base palte that the embodiment of the present invention provides, each public affairs
Common-battery polar curve COM is correspondingly arranged in first void area, namely two column data line D it
Between two row sub-pixel unit P between region in, and the region at public electrode wire COM place
Different from the region at guide wire L place.It is to say, between every two row sub-pixel unit P only
An one public electrode wire COM or guide wire L can be set.Correspondingly, on array base palte also
It is formed with public electrode (not shown in Fig. 2).Wherein, public electrode and public electrode wire COM
Can be connected by via, thus transmit common electrode signal to public electrode.
It is understood that the grid line in the array base palte of present invention offer and public electrode wire
Quantity can be designed according to the ranks number of the sub-pixel unit in array base palte.Concrete next
Say, if battle array substrate includes M row N row sub-pixel unit, owing to it uses dual-gated design, because of
This has only to arrange N/2 data line and 2M bar grid line.And then, need at array base palte
Arrange 2M bar and data wire in arbitrarily 2M the first void area with layer and unidirectional to lead
Lead-in wire, so that the guide wire that 2M bar grid line all has correspondence is attached thereto.Understandable
It is, after being provided with 2M bar guide wire, array base palte to there remains N/2-2M and do not set
Put the first void area of guide wire.Now, in these first void area, public affairs just can be set
Common-battery polar curve.Therefore, the quantity of the public electrode wire this array base palte comprised can be
N/2-2M, so that the structure of the array base palte of present invention offer disclosure satisfy that and comprises this battle array
The basic display requirement of row substrate.
In the specific implementation, each bar guide wire in above-mentioned array base palte and pieces of data line are in battle array
Fan-out mode at row substrate line direction upper side edge can have multiple implementation.Below in conjunction with attached
Fig. 3 and accompanying drawing 4 fan-out optional to two of which mode illustrate.
Fig. 3 shows the fan-out mode of a kind of guide wire and data wire, due in array base palte
Guide wire L is consistent with the arragement direction of data wire D, therefore each guide wire and each data wire
The lower section fan-out of array base palte can be all shown at Fig. 3.Wherein, each bar guide wire L and each bar number
It is multiple according to the fan-out area of line D, and the fan-out area of each bar guide wire L and pieces of data
The fan-out area of line D is alternately arranged.When this is applied in display device at array base palte, hand over
For fan-out guide wire L and data wire D can by different flexibly connect circuit respectively with
Corresponding drive circuit connects.Such as, guide wire L can be by flexibly connecting circuit 1 and grid
Drive circuit connects, and data wire D can be by flexibly connecting circuit 1 with data drive circuit even
Connect, thus grid line G can receive, by guide wire L, the driving signal that gate driver circuit provides,
And according to the unlatching driving signal to control corresponding row sub-pixel unit P, data wire D receives data
Drive circuit provide data voltage and when sub-pixel unit P is opened by data voltage write.
Fig. 4 shows the fan-out mode of another guide wire and data wire, unlike Fig. 3,
In array base palte shown in Fig. 4, each bar guide wire L and pieces of data line D can be at the same area
Fan-out.When this array base palte is applied in display device, at the guide wire of the same area fan-out
L and data wire D can flexibly connect circuit 3 and gate driver circuit or data by identical
Drive circuit connects.Advantage of this is that, it is simple to guide wire and the crimping of data wire,
Thus reduce the manufacture difficulty at crimping.
Certainly, in the array base palte that the embodiment of the present invention provides, guide wire and data wire are all right
Otherwise fan-out, this is not especially limited by the present invention.
Understandable, illustration in above-described embodiment is only to facilitate more preferably geographical
Solve the array base palte that the embodiment of the present invention provides, the concrete restriction to the present invention can not be constituted.
And will not influence each other between each above-mentioned preferred implementation, each preferred implementation it
Between combination in any obtained by scheme all should fall into protection scope of the present invention.
Second aspect, embodiment of the present invention additionally provides the making side of a kind of double grid array base palte
Method, including:
S101, on array base palte, form the sub-pixel unit of array distribution, some data line
And some grid lines；
Wherein, two grid lines, adjacent two data it are provided with between adjacent rows sub-pixel unit
Comprising two row sub-pixel unit between line, each data line is in the sub-pixel unit position of every a line
The place of putting connects two both sides being positioned at this data wire and all adjacent with this data wire sub-pixel list
Unit；
S102, on array base palte, it is also formed with some guidings arranging with data wire with layer
Line, each guide wire is correspondingly arranged at first void area, and the first void area is
Void area between two row sub-pixel unit between adjacent two data line, each guide wire
All corresponding connected with a grid line by transfer hole, for corresponding grid line transmission grid letter
Number.
The array base palte being fabricated to by above-mentioned manufacture method, grid line can be by some and number
Receive the grid of gate driver circuit transmission with layer and guide wire equidirectional with data wire according to line
Drive signal so that when this array base palte is applied to display device, only need to be in array base palte row side
Side edge upwards arranges the fan-out area of guide wire, effectively reduces display device both sides and accounts for
Space, thus be advantageously implemented display device Rimless design.
In the specific implementation, so that the array base palte made by above-mentioned manufacture method can
Controlling luminous intensity in each sub-pixel unit, the manufacture method that embodiment of the present invention provides is also
Including:
S201, on array base palte, it is also formed with some public electrode wires, each common electrical
Polar curve is correspondingly formed in first void area；And first space at public electrode wire place
Region is different from first void area at guide wire place；
S202, on array base palte, it is also formed with public electrode, public electrode and public electrode wire
It is connected by via.
The manufacture method provided due to embodiment of the present invention is the double grid provided according to the present invention
The structure of array base palte and make, so those skilled in the art can be according to foregoing description
The structure of double grid array base palte learns the method making this substrate, the most no longer to this
The manufacture method of the double grid array base palte of bright offer repeats.
The third aspect, embodiment of the present invention additionally provides a kind of display floater, including above-mentioned
Double grid array base palte.Due in this double grid array base palte, data wire and connect the guiding of grid line
Line side fan-out the most in the row direction, therefore without arranging the fanout area of grid line again on side
Territory so that apply the display device of this display floater to be capable of the purpose of Rimless design.
Fourth aspect, embodiment of the present invention additionally provides a kind of display device, this display device
Including above-mentioned display floater.
Wherein, the double grid array base palte that display floater here includes is for as described in relation to the first aspect
Double grid array base palte.Additionally, display device here can also include gate driver circuit,
Data drive circuit and flexibly connect circuit.It is understood that gate driver circuit and number
Be arranged on the pcb board outside display floater according to drive circuit, therefore, gate driver circuit with
And data drive circuit need by flexibly connect circuit could be with corresponding guide wire and data
Line connects.
It is understood that gate driver circuit and data drive circuit need by flexibility even
The mode that connection circuit is connected with guide wire and data wire has a variety of.Such as, as it is shown on figure 3,
Gate driver circuit and data drive circuit can by different flexibly connect circuit respectively with
Each bar guide wire or pieces of data line on array base palte are connected.And gate driver circuit connection
Flexibly connect that circuit is connected with data drive circuit to flexibly connect circuit alternately arranged.Concrete next
Saying, the gate driver circuit being arranged on pcb board is by flexibly connecting circuit 1 and guide wire L
It is connected, thus transmits gate drive signal to grid line G corresponding for guide wire L.And it is arranged on PCB
Data drive circuit on plate is connected with data wire D by flexibly connecting circuit 2, thus to number
Data voltage signal is transmitted according to line D.Each flexibly connects circuit 1 and flexibly connects circuit 2 with each
It is alternately arranged, so that display device disclosure satisfy that basic display requirement.
For another example, as shown in Figure 4, gate driver circuit can pass through phase with data drive circuit
With flexibly connect circuit respectively with each bar guide wire on array base palte or pieces of data line phase
Even.Specifically, the gate driver circuit being arranged on pcb board is permissible with data drive circuit
All it is connected with the guide wire L on array base palte or data wire D respectively by flexibly connecting circuit 3.
Advantage of this is that, it is simple to guide wire and the crimping of data wire, thus the system at crimping
Make difficulty, simplify the processing technology of whole display device.
In the specific implementation, here flexibly connect circuit can be COF (Chip On Flex,
Or Chip On Film, frequently referred to chip on film), or can be FPC (Flexible Printed
Circuit board, flexible PCB).This is not especially limited by the present invention.
Additionally, display device here can be: Electronic Paper, mobile phone, panel computer, TV
Machine, display, notebook computer, DPF, navigator etc. are any has display function
Product or parts.
Last it is noted that above example is only in order to illustrate technical scheme, and
Non-to its restriction；Although the present invention being described in detail with reference to previous embodiment, ability
The those of ordinary skill in territory is it is understood that it still can be to the skill described in foregoing embodiments
Art scheme is modified, or wherein portion of techniques feature is carried out equivalent；And these are repaiied
Change or replace, not making the essence of appropriate technical solution depart from various embodiments of the present invention technical side
The spirit and scope of case.
Claims (10)
1. a double grid array base palte, it is characterised in that: include the sub-pixel list of array distribution
Unit, some data line and some grid lines,
Wherein, two grid lines, adjacent two data it are provided with between adjacent rows sub-pixel unit
Comprising two row sub-pixel unit between line, each data line is in the sub-pixel unit position of every a line
The place of putting connects two both sides being positioned at this data wire and all adjacent with this data wire sub-pixel list
Unit；
Described array base palte also includes some the guide wires arranged with data wire with layer, each
Guide wire is correspondingly arranged at first void area, and described first void area is adjacent two
Void area between two row sub-pixel unit between data line, each guide wire all passes through
Transfer hole is corresponding connected with a grid line, for corresponding grid line transmission signal.
Array base palte the most according to claim 1, it is characterised in that
Described array base palte also includes some public electrode wires, each public electrode wire correspondence
It is arranged in first void area；And first void area at public electrode wire place with lead
First void area at lead-in wire place is different；
Public electrode, described public electrode and described common electrical it is also formed with on described array base palte
Polar curve is connected by via.
3. according to the arbitrary described array base palte of claim 1-2, it is characterised in that each bar is led
Lead-in wire and pieces of data line are in the same area fan-out.
4. according to the arbitrary described array base palte of claim 1-2, it is characterised in that each bar is led
The fan-out area of lead-in wire is multiple with the fan-out area of pieces of data line, and each bar guide wire
Fan-out area is alternately arranged with the fan-out area of pieces of data line.
5. the manufacture method of a double grid array base palte, it is characterised in that including:
Array base palte is formed the sub-pixel unit of array distribution, if some data line and
Dry bar grid line；Wherein, between adjacent rows sub-pixel unit, it is provided with two grid lines, adjacent two
Comprising two row sub-pixel unit between data line, each data line is at the sub-pixel of every a line
Two both sides being positioned at this data wire and all adjacent with this data wire is connected at cell position
Pixel cell；
Described array base palte is also formed with some the guide wires arranged with layer with data wire,
Each guide wire is correspondingly arranged at first void area, and described first void area is
Void area between two row sub-pixel unit between adjacent two data line, each guide wire
All corresponding connected with a grid line by transfer hole, for corresponding grid line transmission grid letter
Number.
Method the most according to claim 5, it is characterised in that including:
Described array base palte is also formed with some public electrode wires, each public electrode
Line is correspondingly formed in first void area；And first interstice coverage at public electrode wire place
Territory is different from first void area at guide wire place；
Described array base palte is also formed with public electrode, described public electrode and described public
Electrode wires is connected by via.
7. a display floater, it is characterised in that include as described in claim 1-4 is arbitrary
Double grid array base palte.
8. a display device, it is characterised in that include display surface as claimed in claim 7
Plate.
9. display device as claimed in claim 8, it is characterised in that described double grid array base
Plate is array base palte as claimed in claim 4；Described display device also includes raster data model electricity
Road, data drive circuit and flexibly connect circuit；Described gate driver circuit drives with described data
Galvanic electricity road by identical flexibly connect circuit respectively with each bar guide wire on array base palte or
Pieces of data line is connected.
10. display device as claimed in claim 8, it is characterised in that described double grid array
Substrate is array base palte as claimed in claim 5；Described display device also includes raster data model
Circuit, data drive circuit and flexibly connect circuit；Described gate driver circuit and described data
Drive circuit by different flexibly connect circuit respectively with each bar guide wire on array base palte
Or pieces of data line is connected；Wherein, what gate driver circuit connected flexibly connects circuit and data
It is alternately arranged that what drive circuit connected flexibly connects circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610512345.4A CN105977264A (en) | 2016-06-30 | 2016-06-30 | Double-gate array substrate and manufacturing method thereof, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106847097A (en) * | 2017-04-21 | 2017-06-13 | 京东方科技集团股份有限公司 | A kind of flexible display substrates and display device |
| CN107942592A (en) * | 2017-11-03 | 2018-04-20 | 惠科股份有限公司 | Display panel and display device |
| CN108847415A (en) * | 2018-06-29 | 2018-11-20 | 厦门天马微电子有限公司 | A kind of array substrate, gate driving circuit and display panel |
| CN110109301A (en) * | 2019-04-23 | 2019-08-09 | 深圳市华星光电半导体显示技术有限公司 | A kind of array substrate, display device |
| US10692898B2 (en) | 2017-01-09 | 2020-06-23 | HKC Corporation Limited | Display panel and display device |
| CN111341209A (en) * | 2020-04-08 | 2020-06-26 | Tcl华星光电技术有限公司 | Display panel |
| US11404449B2 (en) | 2020-04-08 | 2022-08-02 | Tcl China Star Optoelectronics Technology Co., Ltd. | Display panel |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101582422A (en) * | 2009-06-01 | 2009-11-18 | 友达光电股份有限公司 | Display device |
| US20100164917A1 (en) * | 2005-09-26 | 2010-07-01 | Au Optronics Corp. | Display panels |
| CN102629053A (en) * | 2011-08-29 | 2012-08-08 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN104795043A (en) * | 2015-05-11 | 2015-07-22 | 京东方科技集团股份有限公司 | Array substrate, liquid crystal display panel and display device |
| CN104914640A (en) * | 2015-06-26 | 2015-09-16 | 合肥鑫晟光电科技有限公司 | Array substrate, manufacturing method thereof, display panel and display device |
-
2016
- 2016-06-30 CN CN201610512345.4A patent/CN105977264A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100164917A1 (en) * | 2005-09-26 | 2010-07-01 | Au Optronics Corp. | Display panels |
| CN101582422A (en) * | 2009-06-01 | 2009-11-18 | 友达光电股份有限公司 | Display device |
| CN102629053A (en) * | 2011-08-29 | 2012-08-08 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN104795043A (en) * | 2015-05-11 | 2015-07-22 | 京东方科技集团股份有限公司 | Array substrate, liquid crystal display panel and display device |
| CN104914640A (en) * | 2015-06-26 | 2015-09-16 | 合肥鑫晟光电科技有限公司 | Array substrate, manufacturing method thereof, display panel and display device |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10692898B2 (en) | 2017-01-09 | 2020-06-23 | HKC Corporation Limited | Display panel and display device |
| CN106847097A (en) * | 2017-04-21 | 2017-06-13 | 京东方科技集团股份有限公司 | A kind of flexible display substrates and display device |
| CN106847097B (en) * | 2017-04-21 | 2019-03-19 | 京东方科技集团股份有限公司 | A kind of flexible display substrates and display device |
| US10453870B2 (en) | 2017-04-21 | 2019-10-22 | Boe Technology Group Co., Ltd. | Flexible display substrate and display device |
| CN107942592A (en) * | 2017-11-03 | 2018-04-20 | 惠科股份有限公司 | Display panel and display device |
| WO2019084979A1 (en) * | 2017-11-03 | 2019-05-09 | 惠科股份有限公司 | Display panel and display device |
| CN108847415A (en) * | 2018-06-29 | 2018-11-20 | 厦门天马微电子有限公司 | A kind of array substrate, gate driving circuit and display panel |
| CN108847415B (en) * | 2018-06-29 | 2020-08-11 | 厦门天马微电子有限公司 | Array substrate, grid drive circuit and display panel |
| CN110109301A (en) * | 2019-04-23 | 2019-08-09 | 深圳市华星光电半导体显示技术有限公司 | A kind of array substrate, display device |
| CN111341209A (en) * | 2020-04-08 | 2020-06-26 | Tcl华星光电技术有限公司 | Display panel |
| US11404449B2 (en) | 2020-04-08 | 2022-08-02 | Tcl China Star Optoelectronics Technology Co., Ltd. | Display panel |
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