CN105957806B - Method for reducing data remanence in nonvolatile memory - Google Patents
Method for reducing data remanence in nonvolatile memory Download PDFInfo
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- CN105957806B CN105957806B CN201610409795.0A CN201610409795A CN105957806B CN 105957806 B CN105957806 B CN 105957806B CN 201610409795 A CN201610409795 A CN 201610409795A CN 105957806 B CN105957806 B CN 105957806B
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- erasing operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Abstract
The invention discloses a kind of method for reducing data remanence in nonvolatile memory, including：Structural modeling is carried out to non-volatile memory cells using Silvaco TCAD and electrology characteristic models；The corresponding model parameter of factor that data remanence has an impact in being determined in structural model and electrology characteristic model to nonvolatile memory；Using control variate method, according to 0.18 μm of standard CMOS process, influence of any of the above-described influence factor to data remanence in nonvolatile memory is determined, and the floating boom electron number corresponding to floating gate charge amount is calculated；By reducing tunnel oxide thickness, or the source voltage in increase erasing operation, or increase the erasing operation time to reduce floating boom electron number, the model parameter value for choosing floating boom electron number minimum is applied in the industrial manufacturing process and the course of work of device, and then attacker is more difficult to guess storage data according to floating boom electron number, that is, is effectively reduced the probability for recovering data.
Description
Technical field
The present invention relates to the secure storage of nonvolatile memory, and in particular in nonvolatile memory with FGS floating gate structure
Related data remanence problem, belongs to field of information security technology.
Background technology
With the fast development of information storage technology, solid state storage technologies are used widely.Solid-state memory can divide
For volatile memory and nonvolatile memory.Compared with power-off loses the volatile memory of data, non-volatile memories
Device is maintained to data therein when power supply temporarily interrupts or the long period is in off-position[1].At present, with non-easy
The property lost memory is widely used in the sides such as computer, automobile, mobile equipment, communication and medical treatment for the solid state storage technologies of core
Face.
But any type memory is not perfectly safe.The application of nonvolatile memory is based on a kind of false
If that is, by erasing operation, the information in memory is irrecoverable.But it is actually really not so, in nonvolatile memory
Still suffer from data remanence problem.Nonvolatile memory is to store information in the form of a charge, and in write operation, electric charge is deposited
Storage is in floating boom, in erasing operation, allows electric charge to flow out floating boom[2].But performing erasing operation will can not flow in write operation
The electronics for entering floating boom is wiped clean completely, still has Partial charge to remain on floating boom, and is characterized in the device parameters such as threshold voltage
On[3].Even if the data in non-volatile are all logical one, attacker can still pass through the specific mould of measurement device parameter
Analog quantity, through operational analysis, the information in recovering, makes individual privacy or enterprise's secret etc. be on the hazard.
Early in 1996, Peter Gutmann had found there are problems that data remanence in semiconductor memory by studying[4],
And the data remanence phenomenon in the storage unit of nonvolatile memory EEPROM is made further research in 2001, send out
Existing programming time and unit condition etc. can influence the threshold voltage of memory device[5].Data remanence in nonvolatile memory with
Several factors are related, such as write operation time, erasing operation time, bias voltage, technological parameter etc..But do not have article
Or patent proposes how to carry out simulating, verifying to these influence factors.Therefore, after the erasing operation of the invention from reduction on floating boom
The angle of remaining electron number, by varying some influence factors of device, makes after write/erase operation, floating gate type is non-
Electronics residual in volatile memory is less, so as to reduce the data remanence in nonvolatile memory.
[bibliography]
1. Zeng Ying, Wu Dong, Sun Lei etc.；Sophisticated semiconductor memory --- structure, design are with applying [M], Beijing：Electronics work
Industry publishing house, 2005,236-242.
2. Liu Yin, Su Yu, Zhu Jun；FLASH memory cell structures and functional study [J], Tsinghua University's journal (natural science
Version), 1999,39 (S1)：91-94.
3.Skorobogatov S.Data remanence in flash memory devices[M]
.Cryptographic Hardware and Embedded Systems–CHES 2005.Springer Berlin
Heidelberg,2005:339-353。
4.Gutmann P.Secure deletion of data from magnetic and solid-state
memory[C].Proceedings of the Sixth USENIX Security SympoSium,San Jose,
CA.1996,14。
5.Gutmann P.Data remanence in semiconductor devices[C].Proceedings of
the 10th conference on USENIX Security SympoSium-Volume 10.USENIX
Association,2001:4-4。
The content of the invention
, can residual fraction electronics on floating boom after non-volatile memory crosses erasing operation.The present invention proposes that one kind is used for
The method for reducing data remanence in nonvolatile memory, based on software emulation, by varying device some influence factors with
Remaining number of electrons on floating boom after reduction erasing operation, and then attacker is more difficult to guess storage data according to floating boom electron number,
It is effectively reduced the probability for recovering data.
In order to solve the above-mentioned technical problem, the present invention proposes a kind of for reducing data remanence in nonvolatile memory
Method, comprises the following steps：
Step 1：Non-volatile memory cells are modeled using Silvaco TCAD, including structural model and electricity spy
Property model, wherein, structural model include at least using dry oxygen thermal oxide formed tunnel oxidation layer；Electrology characteristic model includes at least
Source voltage and the setting of erasing operation time in erasing operation；
Step 2：Data remanence produces shadow in being determined in structural model and electrology characteristic model to nonvolatile memory
The corresponding model parameter of loud factor；Wherein, the model parameter corresponding to tunnel oxide thickness is spread in dry oxygen thermal oxide
Total time, the model parameter corresponding to the voltage of source is the source voltage in erasing operation, the model corresponding to the erasing operation time
Parameter is Transient total time in erasing operation；
Step 3：Using control variate method, according to 0.18 μm of standard CMOS process, tunnel oxide thickness, erasing behaviour are determined
Source voltage and influence of any influence factor to data remanence in nonvolatile memory in the erasing operation time in work, including：
(1) influence that tunnel oxide thickness produces data remanence in nonvolatile memory, the source in erasing operation
Voltage is 12 volts, and the erasing operation time is 10 microseconds, and the value range for the total time spread in dry oxygen thermal oxide is 8.5~9.5,
Unit is minute, sets step-length as ＜ 0.5 minute, value is respectively 8.5,8.75,9.095,9.1,9.25,9.4,9.45,
9.5；
(2) influence of the source voltage to data remanence in nonvolatile memory in erasing operation, tunnel oxide thickness
For 10.0003 nanometers, the erasing operation time is 10 microseconds, and the value range of source voltage is 7~13, and unit is volt, and value is divided
Wei 7,8,9,10,11,12,13；
(3) influence of the erasing operation time to data remanence in nonvolatile memory, tunnel oxide thickness are
10.003 nanometers, the source voltage in erasing operation is 12 volts, and the value range of erasing operation time is 0.00001~19.85,
Unit is microsecond, value is respectively 0.00001,0.0001,0.001,0.01,0.1,1,10,15,17.5,18.5,19.5,
19.75、19.8、19.85；
(4) proceeded as follows respectively according to the definite Data duplication in above-mentioned (1), (2), (3)：First, carry out once straight
Stream emulation, obtains not into the size of initial threshold voltage during row write erasing operation；Then, the transient state of first time write operation is carried out
Emulation；Finally, transient state and the direct current emulation of erasing operation are carried out, obtains the floating gate charge amount size after the completion of erasing operation, with
And threshold voltage and the difference of initial threshold voltage after the completion of erasing operation；Floating gate charge amount institute is calculated by following formula
Corresponding floating boom electron number；
N=q/-1.602 × 10-19
In formula, N is floating boom electron number, and unit is；Q is floating gate charge amount, and unit is coulomb；
Step 4：By reducing the source voltage in tunnel oxide thickness, or increase erasing operation, or increase erasing operation
Time to reduce floating boom electron number, choose floating boom electron number minimum model parameter value be applied to the industrial manufacturing process of device with
In the course of work.
Compared with prior art, the beneficial effects of the invention are as follows：
Data remanence in nonvolatile memory is the major hidden danger for being potentially damaging to information security.At present only with overriding
The data remanence problem that can not be fully solved etc. technological means in nonvolatile memory, therefore, the present invention is from reduction through wiping
The angle of the remaining electronics of floating boom after division operation, can not only efficiently reduce the data remanence in nonvolatile memory, and
And the unlimited technique of the method, unlimited influence factor, also unlimited emulation tool, applied widely.
Brief description of the drawings
Fig. 1 is the basic structure floating gate cell schematic diagram that data are stored in nonvolatile memory；
Fig. 2 is the flow chart that the present invention is used to reduce the method for data remanence in nonvolatile memory；
Fig. 3 is the structural modeling of non-volatile memory cells；
Fig. 4 is that floating boom residual electron number is influenced analogous diagram by tunnel oxide thickness；
Fig. 5 is shadow of the difference by tunnel oxide thickness of the threshold voltage and initial threshold voltage after the completion of erasing operation
Ring analogous diagram；
Fig. 6 is that source voltage of the floating boom residual electron number in by erasing operation is influenced analogous diagram；
Fig. 7 is source voltage of the difference of the threshold voltage and initial threshold voltage after the completion of erasing operation in by erasing operation
Influence analogous diagram；
Fig. 8 is that floating boom residual electron number is influenced analogous diagram by the erasing operation time；
Fig. 9 is that the difference of the threshold voltage and initial threshold voltage after the completion of erasing operation is influenced by the erasing operation time
Analogous diagram.
Embodiment
The basic structure that data are stored in nonvolatile memory is floating gate cell, as shown in Figure 1.Non-volatile memories list
Store electric charge in meta structure is floating boom.Floating boom is surrounded between control gate and substrate by insulating layer, the broad stopband of insulating layer
A potential barrier is formd, prevents electronics to flow in or out floating boom.The logical zero and logical one shape of non-volatile memory cells
State can be distinguish between according to the number of negative electrical charge on floating boom, and the number of negative electrical charge is determined by programming operation on floating boom.Programming behaviour
Work is divided into write operation and erasing operation.Write operation utilizes channel hot electron injection effect, electronics is flowed into floating boom, on floating boom
Negative electrical charge increase, the threshold voltage V of transistorthRise, added gate source voltage V during higher than read operationGS, transistor cutoff, number
According to saving as logical zero；Erasing operation utilizes F-N tunneling effects, electronics is flowed out floating boom, the melanoma cells on floating boom, crystal
The threshold voltage V of pipethReduce, added gate source voltage V during less than read operationGS, transistor turns, data save as logical one.
If Fig. 2 is the flow chart that the present invention is used to reduce the method for data remanence in nonvolatile memory.With reference to
The drawings and specific embodiments are described in further detail technical solution of the present invention, and described specific embodiment is only to the present invention
It is explained, is not intended to limit the invention.
Step 1：Using 0.18 μm of standard CMOS process, non-volatile memory cells are built using Silvaco TCAD
Mould, including structural modeling and electrology characteristic modeling.
Structural model is included at least forms tunnel oxidation layer using dry oxygen thermal oxide.In Deckbuild windows, start work
Skill editing machine Athena, first carries out the division and substrate initialization of grid, in the key area net such as interface, oxide layer and raceway groove
Lattice division is thinner, improves simulation accuracy.Processing step in the structural modeling of non-volatile memory cells, mainly including dry oxygen
Thermal oxide forms tunnel oxidation layer, and depositing polysilicon is situated between as floating boom, deposited oxide-nitride oxide layer as between grid
Matter, then one layer of polysilicon is deposited as control gate, the material of above deposit is then etched away, the injection of active area is carried out and moves back
Fire.In the structural modeling of non-volatile memory cells, it is also necessary to define electrode, can be preserved in device simulation afterwards on electrode
Characteristic in terms of electricity, and electrology characteristic on electrode can be carried out by Tonyplot and is checked.Carrying out non-volatile memories list
Before the programming operation of member, it is also necessary to starter editing machine DevEdit to the cellular construction that is formed in process establishment device into
Row grid is readjusted, and saves as structured file.Structural modeling result such as Fig. 3.
Electrology characteristic model includes at least the setting of source voltage and erasing operation time in erasing operation.In Deckbuild
In window, starter emulator Atlas, carries out a direct current emulation, obtains not into initial threshold during row write erasing operation first
The size of threshold voltage.By adding 12 volts of voltages to control gate, source adds 0 volt of voltage, and drain terminal adds 6 volts of voltages, write for the first time
Enter the Transient of operation, the floating gate charge amount size being written after the completion of operation, is then based on first time write operation, leads to
Cross and add 0 volt of voltage to control gate, source adds 12 volts of voltages, and drain terminal is hanging, carries out the emulation of erasing operation, erasing operation it is initial
The quantity of electric charge is exactly the floating gate charge amount size after the completion of write operation.By inclined to control gate, source, drain terminal and substrate making alive
Put, Transient is carried out to first time erasing operation, floating gate charge amount can be obtained and changed with the change in erasing time, and profit
Extraction floating gate charge amount size is stated with Extract.Then direct current emulation is carried out to non-volatile memory cells, obtained for the first time
The difference of threshold voltage and initial threshold voltage after erasing operation after the completion of the size and erasing operation of threshold voltage.
Step 2：Model parameter corresponding with influence factor is found in the model that step 1 is established.The present invention chooses non-easy
The influence factor of data remanence includes tunnel oxide thickness, the source voltage swing in erasing operation and wiping in the property lost memory
The division operation time.Wherein, the model parameter corresponding to tunnel oxide thickness is the total time spread in dry oxygen thermal oxide, and source is electric
The corresponding model parameter of pressure is the source voltage in erasing operation, and the model parameter corresponding to the erasing operation time is erasing operation
Middle Transient total time.
Step 3：Using control variate method, shadow of the single influence factor to data remanence in nonvolatile memory is studied
Ring.Including：
According to 0.18 μm of standard CMOS process, research tunnel oxide thickness is to data remanence in nonvolatile memory
During influence, source voltage in erasing operation is 12 volts, and the erasing operation time is 10 microseconds, the total time spread in dry oxygen thermal oxide
Value range be 8.5~20, unit is minute, and it is the multiple of 0.5 minute or 0.5 minute first to set step-length, and value is respectively
8.5、9、9.5、10、10.5、11、12、13、15、20.Model is reduced according to the requirement to tunnel oxide thickness and simulation result
The scope of parameter value, value range are changed into 8.5~9.5, and unit is minute, set step-length to be ＜ 0.5 minute, and value is respectively
8.75、9.095、9.1、9.25、9.4、9.45。
Source voltage is studied in erasing operation in nonvolatile memory during the influence of data remanence, tunnel oxide thickness
For 10.003 nanometers, the erasing operation time is 10 microseconds, and the value range of source voltage is 7~13, and unit is volt, and value is distinguished
For 7,8,9,10,11,12,13.The erasing operation time is studied in nonvolatile memory during the influence of data remanence, tunnel oxygen
It is 10.003 nanometers to change layer thickness, and the source voltage in erasing operation is 12 volts, and the value range of erasing operation time is
0.00001~19.85, unit is microsecond, value is respectively 0.00001,0.00005,0.0001,0.001,0.01,0.1,
0.5、1、5、10、15、17.5、18.5、19.5、19.75、19.8、19.85。
Study any influence factor and imitate during the influence of data remanence, carrying out a direct current in nonvolatile memory first
Very, obtain then carrying out the Transient of first time write operation not into the size of initial threshold voltage during row write erasing operation,
Transient state and the direct current emulation of erasing operation are finally carried out, obtains the floating gate charge amount size after the completion of erasing operation, and erasing
The difference of threshold voltage and initial threshold voltage after the completion of operation.As corresponding to being calculated floating gate charge amount in following formula
Floating boom electron number.
N=q/-1.602 × 10-19
In formula, N is floating boom electron number, and unit is；Q is floating gate charge amount, and unit is coulomb.
Tunnel oxide thickness is studied in nonvolatile memory during the influence of data remanence, by writing erasing operation
Afterwards, floating boom electron number is with simulation result such as Fig. 4 of the situation of change of tunnel oxide thickness, threshold voltage and initial threshold voltage
Difference with the situation of change of tunnel oxide thickness simulation result such as Fig. 5.It can be seen from the figure that with tunnel oxidation layer
The reduction of thickness, remaining electron number is reduced on floating boom, and the difference of threshold voltage and initial threshold voltage after erasing operation is got over
Small, i.e., the data remanence in nonvolatile memory is fewer.Source voltage is to number in nonvolatile memory in research erasing operation
During according to remaining influence, after writing erasing operation, floating boom electron number with the situation of change of source voltage in erasing operation emulation
As a result such as Fig. 6, the difference of threshold voltage and initial threshold voltage with the situation of change of source voltage in erasing operation simulation result
Such as Fig. 7.It can be seen from the figure that with the increase of source voltage in erasing operation, remaining electron number is reduced on floating boom, erasing behaviour
The difference of threshold voltage and initial threshold voltage after work is smaller, i.e., the data remanence in nonvolatile memory is fewer.Research
The erasing operation time in nonvolatile memory during the influence of data remanence, after writing erasing operation, floating boom electron number with
The difference of the simulation result of the situation of change of erasing operation time such as Fig. 8, threshold voltage and initial threshold voltage is with erasing operation
The simulation result of the situation of change of time such as Fig. 9.It can be seen from the figure that with the increase of erasing operation time, it is residual on floating boom
The electron number stayed is reduced, and the difference of threshold voltage and initial threshold voltage after erasing operation is smaller, i.e. nonvolatile memory
In data remanence it is fewer.
Step 4：Choose floating boom electron number and remain minimum model parameter value.Drawn according to simulation result, reduce tunnel oxygen
Change the source voltage swing in layer thickness, or increase erasing operation, or increase erasing operation time, floating boom after erasing operation can be made
Upper remaining electron number is less, and threshold voltage and initial threshold voltage gap are smaller, recovers the difficulty of storage information and can add
Greatly.Selection Model parameter value not only needs to reduce floating boom electron number residual, it is also necessary to meets the performance of nonvolatile memory
It is required that.By taking the erasing operation time as an example, come out if the electronics on floating boom removed completely, i.e. threshold voltage after erasing operation
Initial threshold voltage is equal to, it is necessary to long time, and this time restriction erasing performance of nonvolatile memory,
Therefore the performance requirement of consideration system is needed, to determine the length of erasing operation time.
To sum up, the present invention modeled by simulation software, using control variate method one by one On Affecting Factors In The Study to non-volatile
The influence of data remanence in memory, it is residual to reduce data in nonvolatile memory using some influence factors for changing device
Stay.But the unlimited technique of the present invention, unlimited influence factor, also unlimited emulation tool.
Claims (1)
- A kind of 1. method for reducing data remanence in nonvolatile memory, it is characterised in that comprise the following steps：Step 1：Non-volatile memory cells are modeled using Silvaco TCAD, including structural model and electrology characteristic mould Type, wherein, structural model is included at least forms tunnel oxidation layer using dry oxygen thermal oxide；Electrology characteristic model includes at least erasing Source voltage and the setting of erasing operation time in operation；Step 2：Data remanence has an impact in being determined in structural model and electrology characteristic model to nonvolatile memory The corresponding model parameter of factor；Wherein, the model parameter corresponding to tunnel oxide thickness be spread in dry oxygen thermal oxide it is total Time, the model parameter corresponding to the voltage of source are the source voltage in erasing operation, the model parameter corresponding to the erasing operation time It is Transient total time in erasing operation；Step 3：Using control variate method, according to 0.18 μm of standard CMOS process, determine in tunnel oxide thickness, erasing operation Source voltage and influence of any influence factor to data remanence in nonvolatile memory in the erasing operation time, including：(1) influence that tunnel oxide thickness produces data remanence in nonvolatile memory, the source voltage in erasing operation For 12 volts, the erasing operation time is 10 microseconds, and the value range for the total time spread in dry oxygen thermal oxide is 8.5~9.5, unit It is minute, sets step-length to be ＜ 0.5 minute, value is respectively 8.5,8.75,9.095,9.1,9.25,9.4,9.45,9.5；(2) influence of the source voltage to data remanence in nonvolatile memory in erasing operation, tunnel oxide thickness are 10.0003 nanometers, the erasing operation time is 10 microseconds, and the value range of source voltage is 7~13, and unit is volt, and value is distinguished For 7,8,9,10,11,12,13；(3) influence of the erasing operation time to data remanence in nonvolatile memory, tunnel oxide thickness are received for 10.003 Meter, the source voltage in erasing operation is 12 volts, and the value range of erasing operation time is 0.00001~19.85, and unit is micro- Second, value is respectively 0.00001,0.0001,0.001,0.01,0.1,1,10,15,17.5,18.5,19.5,19.75,19.8, 19.85；(4) proceeded as follows respectively according to the definite Data duplication in above-mentioned (1), (2), (3)：First, a direct current emulation is carried out, is obtained not into the size of initial threshold voltage during row write erasing operation；Then, the Transient of first time write operation is carried out；Finally, transient state and the direct current emulation of erasing operation are carried out, obtains the floating gate charge amount size after the completion of erasing operation, and The difference of threshold voltage and initial threshold voltage after the completion of erasing operation；As the floating boom electron number corresponding to floating gate charge amount is calculated in following formula；N=q/-1.602 × 10-19In formula, N is floating boom electron number, and unit is；Q is floating gate charge amount, and unit is coulomb；Step 4：By reducing the source voltage in tunnel oxide thickness, or increase erasing operation, or increase erasing operation time To reduce floating boom electron number, the model parameter value for choosing floating boom electron number minimum is applied to industrial manufacturing process and the work of device During.
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| EP0774788A1 (en) * | 1995-11-14 | 1997-05-21 | Programmable Microelectronics Corporation | A PMOS flash memory cell capable of multi-level threshold voltage storage |
| CN1440038A (en) * | 2002-02-18 | 2003-09-03 | 三菱电机株式会社 | Nonvolatile memory for catching charges in isolative films |
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| JP2534660B2 (en) * | 1986-03-06 | 1996-09-18 | 日本電気株式会社 | Method of manufacturing nonvolatile semiconductor memory device |
| KR102272228B1 (en) * | 2014-05-13 | 2021-07-06 | 삼성전자주식회사 | Nonvolatile memory device, storage device having the same, and operation method therof |
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|---|---|---|---|---|
| EP0501941B1 (en) * | 1991-01-31 | 1996-10-23 | Interuniversitair Microelektronica Centrum Vzw | Transistor structure for use in erasable and programmable semiconductor memory devices |
| EP0774788A1 (en) * | 1995-11-14 | 1997-05-21 | Programmable Microelectronics Corporation | A PMOS flash memory cell capable of multi-level threshold voltage storage |
| CN1440038A (en) * | 2002-02-18 | 2003-09-03 | 三菱电机株式会社 | Nonvolatile memory for catching charges in isolative films |
| CN1866399A (en) * | 2005-05-16 | 2006-11-22 | 松下电器产业株式会社 | Storage controller, involatile storage,involatile storage system and data inputting method |
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