CN105932050B - A kind of planar gate IGBT and preparation method thereof - Google Patents
A kind of planar gate IGBT and preparation method thereof Download PDFInfo
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- 238000009825 accumulation Methods 0.000 description 5
- 230000009467 reduction Effects 0.000 description 5
- 230000009514 concussion Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000005670 electromagnetic radiation Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 206010019133 Hangover Diseases 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
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- 239000004744 fabric Substances 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
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- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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Abstract
A kind of planar gate IGBT and preparation method thereof, belongs to power semiconductor device technology field.The present invention is on the basis of conventional planar grid IGBT device structure, floating p-type area is introduced in the subregion on the areas device JFET surface, the floating p-type area is spaced apart with gate electrode perpendicular to the formation of MOS orientations, in the areas JFET by being spread from grid toward the lateral carrier in floating p-type area direction in MOS orientations when device forward conduction, structure of the invention is not under conditions of influencing device forward conduction characteristic, reduce the grid capacitance of device, especially grid collector capacitance, improve the switching speed of device, reduce the switching loss of device, the blocking characteristics of device will not be made to deteriorate simultaneously.
Description
Technical field
The invention belongs to power semiconductor device technology fields, are related to insulated gate bipolar transistor (IGBT), specifically relate to
And planar gate insulated gate bipolar transistor.
Background technology
Insulated gate bipolar transistor (IGBT) is a kind of MOS field-effects and the compound novel electric power electricity of bipolar transistor
Sub- device.Its existing MOSFET is easy to drive, and controls simple advantage, and has power transistor turns pressure drop low, on state current
Greatly, small advantage is lost, it has also become one of core electron component in modern power electronic circuit is widely used in such as
The every field of the national economy such as communication, the energy, traffic, industry, medicine, household electrical appliance and aerospace.The application pair of IGBT
The promotion of power electronic system performance plays particularly important effect.
Since IGBT inventions, people have been devoted to improve the performance of IGBT.By development in twenties years, carry in succession
Go out mostly for IGBT device structure, device performance is made to have obtained steady promotion.Trench gate IGBT structure eliminates planar gate
The areas the JFET resistance of IGBT structure, and higher MOS gully densities are can get, it is significantly carried so as to make the characteristic of device obtain
It is high.However, compared with planar gate IGBT structure, the high electric field of trench gate structure bottom be influence its reliability major factor it
One, thus high pressure IGBT still mainly uses planar gate structure at present.For high voltage planar grid IGBT, in order to reduce device p-type base
The areas JFET resistance between area and the electron accumulation layer raising in device forward conduction by being formed under the areas JFET gate electrode
The carrier of device injects enhancement effect, and the areas JFET between device p-type base area are very wide.The gate structure band on the wide areas JFET top
Carry out device capacitor greatly, especially grid-collector capacitance, reduced the switching speed of device, increases the switch of device
Loss, while improving the requirement to device gate drive circuit ability.In addition, the grid capacitance on the areas device JFET top, in device
Negative differential capacity effect can be formed in part low current opening process, device is made to generate concussion and thus band incoming call in opening process
The problem of magnetic radiation.
Invention content
For the blocking electricity of the carrier concentration profile of device and conduction voltage drop and device when not influencing forward conduction
In the case of pressure, reduce the grid capacitance of device, especially grid-collector capacitance, improve the switching speed of device, reduction is opened
Loss is closed, further improves the compromise of forward conduction voltage drop and switching loss, while reducing to device gate drive circuit ability
It is required that and overcome the problems, such as the concussion in opening process that negative differential capacity effect is brought, in conventional high-tension planar gate IGBT device
On the basis of structure (as shown in Figure 1), the present invention provides a kind of high voltage planar grid IGBT (half cellular and section such as figure along AB lines
Shown in 2 and 3) and preparation method thereof.The present invention is less than p-type by introducing a layer thickness in the subregion on the areas device JFET surface
The thin floating p-type area of base area makes the floating p-type area form interval point perpendicular to MOS orientations with gate electrode
Cloth, and make the floating p-type area in expansion of the length perpendicular to MOS orientations less than the areas device JFET bipolar carrier
It dissipates length, and is more than it in the length perpendicular to MOS orientations in the length for being parallel to MOS orientations,
The length being usually arranged is than being at least 4 times or more.In device forward conduction, the present invention by the areas JFET perpendicular to MOS ditches
Spread from grid toward the lateral carrier in floating p-type area direction on road length direction, make areas JFET under floating p-type area have with
The identical carrier concentration profile in the areas JFET under grid, under conditions of not influencing device forward conduction, reduce device
The grid capacitance of part, especially grid-collector capacitance, improve the switching speed of device, reduce the switching loss of device,
The blocking characteristics of device will not be made to deteriorate simultaneously.In addition, the reduction of the areas device JFET upper gate capacitance, reduces device small
Negative differential capacity effect under electric current open state avoids the electromagnetism spoke that shakes and thus bring of the device in opening process
Problem is penetrated, the Performance And Reliability of device is improved.Production method provided by the invention need not increase complicated processing step,
It is compatible with conventional planar grid IGBT production methods.
Technical solution of the present invention is as follows：
A kind of planar gate IGBT, half structure cell and as shown in Figures 2 and 3 along the section of AB lines, including：From bottom to up
Back collector electrode metal 10, p-type collecting zone 9, N-type field stop layer 8 and the drift regions N- 7 being cascading；The N- drifts
There is 7 upper layer both sides of area p-type base area 4,4 upper layer of p-type base area to have mutually independent N+ emitter region 3 and P+ emitter region 2；Institute
Stating N+ emitter region 3 and 2 upper surface of P+ emitter region has emitter metal 1；It is characterized in that, the emitter metal 1 positioned at both sides
Between semiconductor surface have compound gate structure, between compound gate structure and emitter metal 1 have spacing；It is described multiple
It includes dielectric layer 5 and the gate electrode 6 on dielectric layer 5 to close gate structure；The lower surface of the dielectric layer 5 and part N+
Emitter region 3, p-type base area 4 are connected with the upper surface of the drift regions N- 7；Along device longitudinal direction, gate electrode 6 has in the side of device
There are opening, the underface of the opening that there is floating p type island region 11；The floating p type island region 11 is located at 7 upper layer of the drift regions N-, and edge
Device horizontal direction has spacing, along device longitudinal direction, floating p type island region between the both sides and p-type base area 4 of floating p type island region 11
11 portion of upper surface is contacted with dielectric layer 5；The floating p-type area 11 is less than in the length perpendicular to MOS orientations
The bipolar carrier diffusion length in the areas device JFET, the floating p-type area 11 and the gate electrode 6 are being parallel to MOS ditch Taoist priests
The length for spending direction is more than it in the length perpendicular to MOS orientations, and the floating p-type area 11 is being parallel to
The length of MOS orientations is it perpendicular to 4 times or more of MOS orientation length；Half structure cell
It is symmetrical in the center line along device horizontal direction.
Further, a kind of planar gate IGBT, half structure cell and section such as Fig. 4, Fig. 5 and Fig. 6 along AB and CD lines
Shown, along device longitudinal direction, in the side of device tool there are two opening, the underface of two openings has the gate electrode 6
There is floating p type island region 11, between device horizontal direction, floating p type island region 11, between the both sides of floating p type island region 11 and p-type base area 4
With spacing, and the opening of both sides and floating p type island region 11 are symmetrical along the center line of device.
Further, a kind of planar gate IGBT, half structure cell and section such as Fig. 7, Fig. 8 and Fig. 9 along AB and CD lines
Shown, the areas the JFET surface between the floating p type island region 11, between the both sides of floating p type island region 11 and p-type base area 4 also has
One layer of N-type layer 12, the doping concentration of the N-type layer 12 is more than the concentration of the drift regions N- 7, and its junction depth is not more than floating p-type
The junction depth in area 11；
Further, there can also be one layer of N-type hole blocking layer between the p-type base area 4 and the drift regions N- 7；
Further, can identical also may be used with material in MOS channel regions and the thickness of the dielectric layer 5 on the areas JFET top
With difference；
Further, the drift region structure is NPT structures or FS structures；The IGBT device uses semi-conducting material
Si, SiC, GaAs or GaN make.
Further, the device architecture is applicable not only to IGBT device, and the p-type collecting zone 9 at the device back side is changed to N+
Layer, the structure is equally applicable to MOSFET element, as MOSFET element in application, the current potential of the floating p type island region 11 can
It also can be with emitter equipotential with floating.
A kind of production method of planar gate IGBT, includes the following steps：
The first step：That chooses certain thickness and concentration is lightly doped FZ silicon chips to form the drift regions N- 7 of device；
Second step：Pass through the N-type field stop layer 8 of ion implanting N-type impurity and making devices of annealing in silicon chip back side；
Third walks：Silicon chip is overturn and is thinned, in the terminal structure of front side of silicon wafer making devices；
4th step：Active area is etched, dielectric layer 5 is formed on 7 surface of the drift regions N-；
5th step：The depositing polysilicon layer on dielectric layer 5, and photoetching, etching form gate electrode 6；
6th step：It using photoetching process, by ion implanting p type impurity and anneals, is formed in 7 upper layer both sides of the drift regions N-
P-type base area 4；
7th step：Using photoetching process, by ion implanting p type impurity, the 7 upper layer shape of the drift regions N- between p-type base area 4
At the floating p-type area 11 thinner than p-type base area 4；
8th step：Using photoetching process, by ion implanting N-type impurity, N+ emitter region 3 is formed on 4 upper layer of p-type base area；
9th step：Using photoetching process, by ion implanting p type impurity, in 4 upper layer shape P+ emitter region 2, P+ of p-type base area
Emitter region 2 and N+ emitter region 3 are mutual indepedent；
Tenth step：Metal, and photoetching, etching are deposited, the device surface in gate electrode both sides forms metal collector 1；
11st step：Silicon chip is overturn, silicon wafer thickness is thinned, in silicon chip back side implanting p-type impurity and anneals, is hindered in N-type field
Only 8 lower surface of layer forms p-type collecting zone 9；
12nd step：The back side deposits metal, and metal collector 10 is formed in 9 lower surface of p-type collecting zone.It is prepared into this hair
Bright planar gate IGBT.
It should be noted that simplify the description, above-mentioned device architecture and preparation method are by taking n-channel IGBT device as an example
Illustrate, but the present disclosure applies equally to the preparation of p-channel IGBT device.And the processing step in above-mentioned device preparation method and
Process conditions can carry out additions and deletions and adjustment according to actual needs.
In said program, the corresponding X-direction in coordinate system shown in Fig. 2 of the device horizontal direction, device
The corresponding Z-direction in coordinate system shown in Fig. 2 of part longitudinal direction.
The operation principle of the present invention：
The switching process of IGBT is exactly the process rushed, discharged to grid capacitance, and grid capacitance gets over favourable opposition, discharge time
It is longer.Thus, in the switching process of IGBT, grid capacitance, especially grid-collector capacitance have the switching loss of device
There is important influence.For high voltage planar grid IGBT device, in order to reduce the areas the JFET resistance between device p-type base area and in device
The carrier that device is improved by the electron accumulation layer formed under the areas JFET gate electrode when part forward conduction injects enhancement effect,
Improve the concentration distribution of drift region carrier, reduce forward conduction voltage drop, improves the compromise of forward conduction voltage drop and turn-off power loss,
The areas JFET between device p-type base area are very wide.The gate structure on the wide areas JFET top brings big device capacitor, especially grid
Pole-collector capacitance reduces the switching speed of device, increases the switching loss of device, while improving and being driven to device gate
The requirement of dynamic circuit capacity.In addition, the grid capacitance on the areas device JFET top, can form negative in device low current opening process
Differential capacitance effect makes device be led to the problem of in opening process and shakes and thus bring electromagnetic radiation.By directly taking away
The gate electrode on the areas JFET top and the method for only retaining the gate electrode of p-type base area top MOS channel regions, although device can be reduced
Grid capacitance cannot be in device but in device forward conduction since the areas JFET top does not have the effect of gate electrode
The areas JFET surface forms the electron accumulation layer of high concentration, as conductance modulation type device, this also means that cannot be obtained in the areas JFET
High hole concentration is obtained, which results in the reductions of the regional Electronic and hole concentration of the entire areas JFET and the areas JFET lower part, while by
The extraction in hole is acted in p-type base area, a concentration of the 0 of the interface holoe carrier of p-type base area 9 and the drift regions N- 7, because
This so that the carrier concentration profile of the entire drift regions N- 7 is deteriorated, and eliminates the current-carrying that the gate structure on the areas JFET top is brought
Son injection enhancement effect, makes the forward conduction voltage drop of device increased dramatically, and affect the turn-off characteristic of device, is especially off
The characteristic in Carrier recombination stage after device voltage reaches busbar voltage in the process, makes the hangover in device turn off process
Time increases, and increases turn-off power loss.Structure of the invention is by introducing thin floating p in the subregion on the areas device JFET surface
Type area 11, the floating p-type area 11 are spaced apart with gate electrode 6 perpendicular to the formation of MOS orientations, and described floating
Empty p-type area 11 is less than the bipolar carrier diffusion length in the areas device JFET in the length perpendicular to MOS orientations, in device
The areas the JFET surface of the lower section of gate electrode 6 forms the electron accumulation layer of high concentration due to the effect of gate electrode when part forward conduction, by
The hole concentration of high concentration is also obtained in JFET area of the conductance modulation below gate electrode 6, the areas JFET below gate electrode is made to obtain
Obtain high electrons and holes concentration；The areas JFET below floating p-type area 11 simultaneously, although cannot be formed by the effect of electrode
The electron accumulation layer of high concentration, but due in the high electronics in the areas JFET below MOS orientation gate electrodes and
Hole concentration, by MOS orientations from gate electrode 6 toward the lateral carrier in 11 direction of floating p-type area
Diffusion makes the areas JFET of 11 lower section of floating p-type area also obtain identical with the areas JFET of 6 lower section of gate electrode high electronics and sky
Cave concentration makes the areas JFET of entire device and the areas JFET lower part obtain high electrons and holes concentration, has and conventional planar
The identical carrier concentration profile of grid IGBT structure and identical forward conduction characteristic.By making the floating p-type area 11 and institute
It states gate electrode 6 and is more than it in the length perpendicular to MOS orientations in the length for being parallel to MOS orientations, and
And the floating p-type area 11 is made in the length for being parallel to MOS orientations to be it long perpendicular to MOS orientations
4 times or more of degree, the present invention reduces device as far as possible in the case where not influencing device forward conduction characteristic and breakdown characteristics
The grid capacitance of part, especially grid-collector capacitance, improve the switching speed of device, reduce the switching loss of device.This
Outside, the reduction of the areas device JFET upper gate capacitance reduces negative differential capacity effect of the device under low current open state,
Concussion and the electromagnetic radiation thus brought of the device in opening process are avoided, the performance of device and reliable is improved
Property.
Beneficial effects of the present invention are shown：
Structure of the invention by the areas device JFET surface subregion introduce floating p-type area, the floating p-type area with
Grid is spaced apart perpendicular to the formation of MOS orientations, is passed through perpendicular to MOS raceway grooves in the areas JFET in forward conduction
It is spread from grid toward the lateral carrier in floating p-type area direction on length direction, structure of the invention is not influencing the positive guide of device
Under conditions of logical characteristic, the grid capacitance of device is reduced, especially grid-collector capacitance, improves the switch speed of device
Degree, reduces the switching loss of device, while the blocking characteristics of device will not be made to deteriorate.By making 11 He of floating p-type area
The gate electrode 6 is more than it in the length perpendicular to MOS orientations in the length for being parallel to MOS orientations,
And the floating p-type area 11 is made in the length for being parallel to MOS orientations to be it perpendicular to MOS orientations
4 times or more of length, the present invention reduces as far as possible in the case where not influencing device forward conduction characteristic and breakdown characteristics
The grid capacitance of device, especially grid-collector capacitance.In addition, the reduction of the areas device JFET upper gate capacitance, reduces
Negative differential capacity effect of the device under low current open state avoids concussion of the device in opening process and thus brings
Electromagnetic radiation, improve the Performance And Reliability of device.Production method provided by the invention need not increase complicated
Processing step, it is compatible with conventional planar grid IGBT production methods.The present invention is suitable for half from mid power to powerful high pressure
Conductor power device field.
Description of the drawings
Fig. 1 is traditional half cellular structural schematic diagram of planar gate IGBT device.
Fig. 2 is the first half cellular structural schematic diagram of planar gate IGBT device provided by the invention.
Fig. 3 is diagrammatic cross-section of the first half structure cell of planar gate IGBT device provided by the invention along AB lines.
Fig. 4 is second of planar gate IGBT device, half cellular structural schematic diagram provided by the invention.
Fig. 5 is diagrammatic cross-section of second of planar gate IGBT device, half structure cell provided by the invention along AB lines.
Fig. 6 is diagrammatic cross-section of second of planar gate IGBT device, half structure cell provided by the invention along CD lines.
Fig. 7 is the third half cellular structural schematic diagram of planar gate IGBT device provided by the invention.
Fig. 8 is diagrammatic cross-section of the third half structure cell of planar gate IGBT device provided by the invention along AB lines.
Fig. 9 is diagrammatic cross-section of the third half structure cell of planar gate IGBT device provided by the invention along CD lines.
In Fig. 1 to Fig. 9,1 is emitter metal, and 2 be P+ emitter region, and 3 be N+ emitter region, and 4 be p-type base area, and 5 be medium
Layer, 6 be gate electrode, and 7 be the drift regions N-, and 8 be N-type electric field trapping layer, and 9 be p-type collecting zone, and 10 be collector electrode metal, and 11 be floating
Empty p-type area, 12 be N-type layer.
Specific implementation mode
Below in conjunction with attached drawing, the principle of the present invention and characteristic are described further, specific embodiments of the present invention
It is illustrated by taking the IGBT of 6500V voltage class as an example, the given examples are served only to explain the present invention, is not intended to limit the present invention
Range.
Embodiment 1：
A kind of planar gate IGBT, half structure cell and as shown in Figures 2 and 3 along the section of AB lines, including：Back current collection
Pole metal 10, on back collector electrode metal 10 and coupled p-type collecting zone 9, be located at p-type collecting zone 9 on simultaneously
Coupled N-type field stop layer 8, on N-type field stop layer 8 and the coupled drift regions N- 7；Positioned at the drift regions N-
7 tops both sides and coupled p-type base area 4 are located at 4 top of p-type base area and coupled N+ emitter region 3 independent of each other
With P+ emitter region 2；Emitter metal 1 positioned at 2 upper surface of N+ emitter region 3 and P+ emitter region；Half between emitter metal 1
The compound gate structure and floating p-type area 11 of conductive surface；It is characterized in that：The compound gate structure include dielectric layer 5 with
And the gate electrode 6 on dielectric layer 5, the dielectric layer 5 and gate electrode 6 be located at N+ emitter region 3, p-type base area 4 upper zone
The upper part region of domain and the drift regions N- 7, lower surface and N+ emitter region 3, p-type base area 4 and the N- of the dielectric layer 5 drift about
The upper surface in area 7 is connected；The floating p-type area 11 is located at the upper surface part subregion of the drift regions N- 7, and is hanging down with gate electrode 6
It is directly spaced apart in the formation of MOS orientations, the floating p-type area 11 is in the length perpendicular to MOS orientations
Less than the bipolar carrier diffusion length in the areas device JFET, the floating p-type area 11 and the gate electrode 6 are being parallel to MOS ditches
The length of road length direction is more than it in the length perpendicular to MOS orientations, and the floating p-type area 11 is parallel
In the length of MOS orientations be it perpendicular to 4 times or more of MOS orientation length；The half cellular knot
Structure is symmetrical in the direction for being parallel to MOS channel lengths.Half cellular formed is being parallel to MOS orientations
Length is 80-90 micron, and the JFET sector widths between p-type base area 4 are 65-75 microns, half cellular of formation perpendicular to
The length of MOS orientations is 15-20 microns；The gate electrode of formation is in the length perpendicular to MOS orientations
5-10 microns；The floating p-type area 11 of formation is located at the center of half dollar born of the same parents in the direction for being parallel to MOS channel lengths, symmetrical,
Length is 50-70 microns, and floating p-type area 11 is 5-10 microns in the direction length perpendicular to MOS channel lengths, floating p-type area
11 junction depth is 0.2-0.5 microns.
Embodiment 2：
A kind of planar gate IGBT, half structure cell and as shown in Figure 4, Figure 5 and Figure 6 along the section of AB and CD lines, in reality
On the basis of applying example 1, the gate electrode 6 also has 1 or so pair perpendicular to the direction of MOS channel lengths at half cellular center
What is claimed is interdigital.It is described it is interdigital the length for being parallel to MOS orientations be 3-5 microns, perpendicular to MOS channel lengths
Direction length is 5-10 microns.The interdigital presence of gate electrode 6 further enhances grid toward the cross in emitter connection electrode direction
To carrier diffusion, forward conduction characteristic and carrier concentration profile are improved.
Embodiment 3：
A kind of planar gate IGBT, half structure cell and as shown in Figure 7, Figure 8 and Figure 9 along the section of AB and CD lines, in reality
On the basis of applying example 2, the areas the JFET table between the floating p type island region 11, between the both sides of floating p type island region 11 and p-type base area 4
Face also has one layer of N-type layer 12, and the doping concentration of the N-type layer 12 is more than the concentration of the drift regions N- 7, and its junction depth is less than floating
0.1-0.3 microns of the junction depth of empty p type island region 11.The introducing of n type buried layer 15 further improves the forward conduction characteristic and load of device
Sub- concentration distribution is flowed, in device breakdown, n type buried layer 15 is fully- depleted.
Claims (6)
1. a kind of planar gate IGBT, including：The back collector electrode metal (10) that is cascading from bottom to up, p-type collecting zone
(9), N-type field stop layer (8) and the drift regions N- (7)；The drift regions N- (7) the upper layer both sides have p-type base area (4), the p-type
Base area (4) upper layer has mutually independent N+ emitter region (3) and P+ emitter region (2)；The N+ emitter region (3) and P+ emitter region
(2) upper surface has emitter metal (1)；It is characterized in that, the semiconductor surface between the emitter metal (1) of both sides
With compound gate structure, there is spacing between compound gate structure and emitter metal (1)；The compound gate structure includes
Dielectric layer (5) and the gate electrode (6) on dielectric layer (5)；The lower surface of the dielectric layer (5) and part N+ emitter region
(3), p-type base area (4) are connected with the upper surface of the drift regions N- (7)；Along perpendicular to MOS orientations, gate electrode (6) is in device
There is opening, the underface of the opening to have floating p type island region (11) for the side of part；The floating p type island region (11) is located at N- drifts
Area (7) upper layer is moved, and along MOS orientations are parallel to, is had between the both sides and p-type base area (4) of floating p type island region (11)
Spacing, along perpendicular to MOS orientations, the portion of upper surface of floating p type island region (11) is contacted with dielectric layer (5)；It is described floating
Empty p type island region (11) is less than the bipolar carrier diffusion length in the areas device JFET, institute in the length perpendicular to MOS orientations
It states floating p type island region (11) and the gate electrode (6) and is more than it perpendicular to MOS in the length for being parallel to MOS orientations
The length of orientation, and the floating p type island region (11) is that it is hanging down in the length for being parallel to MOS orientations
Directly in 4 times or more of MOS orientation length.
2. a kind of planar gate IGBT according to claim 1, it is characterised in that：The gate electrode (6) has the one of opening
Side also has there are one opening, and the underface of two openings all has floating p type island region (11), and edge is parallel to MOS orientations,
Between floating p type island region (11), there is spacing between the both sides of floating p type island region (11) and p-type base area (4), and the opening of both sides and
Floating p type island region (11) is symmetrical perpendicular to the center line of MOS orientations along device.
3. a kind of planar gate IGBT according to claim 2, it is characterised in that：Between the floating p type island region (11), float
The areas JFET surface between the both sides and p-type base area (4) of empty p type island region (11) also has a floor N-type layer (12), the N-type layer
(12) doping concentration is more than the concentration of the drift regions N- (7), and its junction depth is not more than the junction depth of floating p type island region (11).
4. a kind of planar gate IGBT according to claim 1-3 any one, it is characterised in that：In MOS channel regions and
The thickness and material of the dielectric layer (5) on the areas JFET top can be the same or different.
5. a kind of planar gate IGBT according to claim 1-3 any one, it is characterised in that：The p-type base area (4) with
There can also be one layer of N-type hole blocking layer between the drift regions N- (7).
6. a kind of production method of planar gate IGBT, includes the following steps：
The first step：That chooses certain thickness and concentration is lightly doped FZ silicon chips to form the drift regions N- (7) of device；
Second step：Pass through the N-type field stop layer (8) of ion implanting N-type impurity and making devices of annealing in silicon chip back side；
Third walks：Silicon chip is overturn and is thinned, in the terminal structure of front side of silicon wafer making devices；
4th step：Active area is etched, dielectric layer (5) is formed on the drift regions N- (7) surface；
5th step：The depositing polysilicon layer on dielectric layer (5), and photoetching, etching form gate electrode (6)；
6th step：It using photoetching process, by ion implanting p type impurity and anneals, p is formed in the drift regions N- (7) upper layer both sides
Type base area (4)；
7th step：Using photoetching process, by ion implanting p type impurity, the drift regions N- (7) upper layer shape between p-type base area (4)
At the floating p type island region (11) thinner than p-type base area (4)；
8th step：Using photoetching process, by ion implanting N-type impurity, N+ emitter region (3) is formed on p-type base area (4) upper layer；
9th step：Using photoetching process, by ion implanting p type impurity, in p-type base area (4) upper layer shape P+ emitter region (2), P+
Emitter region (2) and N+ emitter region (3) are mutual indepedent；
Tenth step：Metal, and photoetching, etching are deposited, the device surface in gate electrode both sides forms metal emitting (1)；
11st step：Silicon chip is overturn, silicon wafer thickness is thinned, in silicon chip back side implanting p-type impurity and anneals, in N-type field stop layer
(8) lower surface forms p-type collecting zone (9)；
12nd step：The back side deposits metal, forms metal collector (10) in p-type collecting zone (9) lower surface, that is, is prepared into this hair
Bright planar gate IGBT.
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| GB2380604A (en) * | 2001-06-01 | 2003-04-09 | Fuji Electric Co Ltd | Bi-directional semiconductor switch |
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