CN105871895A - IEC61850 communication protocol converter with encryption and decryption functions and implementing method - Google Patents
IEC61850 communication protocol converter with encryption and decryption functions and implementing method Download PDFInfo
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- CN105871895A CN105871895A CN201610327057.1A CN201610327057A CN105871895A CN 105871895 A CN105871895 A CN 105871895A CN 201610327057 A CN201610327057 A CN 201610327057A CN 105871895 A CN105871895 A CN 105871895A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/08—Protocols for interworking; Protocol conversion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
- H04L63/0428—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0637—Modes of operation, e.g. cipher block chaining [CBC], electronic codebook [ECB] or Galois/counter mode [GCM]
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- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Communication Control (AREA)
Abstract
The invention discloses an IEC61850 communication protocol converter with encryption and decryption functions and an implementing method. The protocol converter comprises an FPGA processor, a power module, a communication interface module and a storage module. The FPGA processor is connected with the power module, the communication interface module and the storage module. A high-performance ARM microprocessor, an Ethernet controller MAC, a UART serial port communication interface, a super encryption and decryption AES module, a clock module, a reset module and a PLL phase-locked loop module are embedded in the FPGA processor. The storage module comprises an ROM, an EFLASH and an SRAM. The IEC103 protocol adopted in communication of a traditional transformer substation and the international communication standard protocol IEC61850 are converted by the converter, a solution is provided for automatic system communication of the transformer substation, and the protocol converter supports optical fiber communication, has encryption and decryption functions, increases speed of data transmission and improves safety of data transmission.
Description
Technical field
The present invention relates to the technical field of power communication, particularly to a kind of, there is encrypting and decrypting function
IEC61850 communication protocol converter and implementation method.
Background technology
Along with the development in an all-round way of China's intelligent substation, communication of power system stipulations are used uniformly across IEC61850
Standard is the pith of intelligent substation.IEC61850 standard is as International Power system automation field
Communicate unique universal standard, by a series of standardization communicating substation equipment so that it is is formed
The output of one specification, it is achieved the seamless communication of power system.
Due to the information between relay protection existing equipment and the control system of current electric substation automation system
Exchange is main or uses IEC103 standard, how to make to be unsatisfactory in electric substation automation system IEC61850
It is that transformer station realizes intelligentized key issue that the smart machine of communication standard realizes IEC61850 standard.
IEC61850 standard does not the most make corresponding specification in terms of security at present, how to realize change
After power station is used uniformly across IEC61850 communication standard, it is ensured that the confidentiality and integrity of communication data, it is ensured that
Communication of power system security is that transformer station realizes another key issue intelligentized.
Therefore for the problems referred to above, it is necessary to developing a IEC103 of realization standard handovers is IEC61850 mark
Accurate and there is the protocol converter of encrypting and decrypting function, realize unified offer for substation communication stipulations
The solution of transition, and ensure the safety and reliability of communication of power system data.
Summary of the invention
It is an object of the invention to the shortcoming overcoming prior art with not enough, it is provided that one has encrypting and decrypting merit
The IEC61850 communication protocol converter of energy and implementation method, it is achieved IEC103 standard handovers is IEC61850
The conversion of standard, and add superencipherment deciphering AES, improve the safety and reliability of communication data.
First purpose of the present invention is achieved through the following technical solutions:
A kind of IEC61850 communication protocol converter with encrypting and decrypting function, described protocol converter bag
Include FPGA processor, power module, communication interface modules, memory module, wherein, described FPGA process
Device is connected with described communication interface modules, power module, memory module respectively；
Described FPGA processor is for realizing the mutual conversion of IEC103 stipulations and IEC61850 stipulations；
Described voltage module provides operating voltage for described protocol converter；
Described communication interface modules is for realizing the data exchange of described protocol converter and external equipment；
Described memory module is used for storing data, stipulations translation-profile and boot in stipulations conversion
Loader program, FPGA control program.
Further, described FPGA processor includes high-performance ARM microprocessor, and this high-performance ARM is micro-
Processor is 32 ARM926EJ-S high-performance processors, is used for realizing IEC103 stipulations and IEC61850
The mutual conversion of stipulations；
Described 32 ARM926EJ-S high-performance processors are write under Keil4 development environment, and chip embeds
UCOS-II real-time operation program, by each module in instruction control chip, it is achieved conventions data reception,
Conversion between IEC103 stipulations and IEC61850 hough transformation, conventions data transmission, tasks carrying, work
Status monitoring function.
Further, described FPGA processor includes that superencipherment deciphers AES module, and this module uses
The block length of 128bits and the aes algorithm of 128bits key length, encryption mode uses CBC packet
Pattern, for realizing encryption and the deciphering function of communication data.
Further, described storage module includes ROM, EFLASH and SRAM memory, wherein said ROM
Memory be the 16KB ROM of Embedded for storing the control program of FPGA, described EFLASH store
Device be Embedded 10M EFLASH for storing boot loader program and stipulations translation-profile,
Described SRAM memory is Embedded 16KB SRAM storage of data in stipulations are changed.
Further, described communication interface modules includes Ethernet interface and serial interface, wherein, described with
Too network interface includes 2 RJ45 network interfaces and 2 ST optical fiber interfaces and 2 physical interface transceiver PHY,
Wherein this ST optical fiber interface selects HFBR 5803T, and this PHY chip selects DP83849IF chip；Described
Serial interface includes 2 RS485 physical interfaces and 2 RS232 physical interfaces.
Further, the power supply input of described power module is 5V voltage, uses AMS1117 power supply voltage stabilizing
Chip provides 3.3V galvanic current pressure, powers for protocol converter.
Further, described FPGA processor also includes that ethernet controller MAC, UART serial communication connects
Mouth, clock module, reseting module and PLL phase-locked loop module；Wherein,
Described clock module include RTC Controller real-time clock controller, watch dog house dog,
Timer timer and OSC32K crystal oscillator, wherein RTC Controller real-time clock controller is by 32KHz
Crystal oscillator drives, and provides real-time clock, various clock signals in synchronous converter for converter；watch dog
House dog provides monitoring in real time for converter running status, prevents program fleet occur under interference；Timer
Timer provides counting, interrupt function for translator program；
Described reseting module is connected with described high-performance ARM microprocessor, sends reset signal；With described
Watch dog house dog connects, and receives reset signal；
Described PLL phase-locked loop module is used for the frequency dividing to clock and frequency multiplication, produces multi-level clock, calibrates at different levels
Clock amplitude and phase place.
Another object of the present invention is achieved through the following technical solutions:
A kind of implementation method of the IEC61850 communication protocol converter with encrypting and decrypting function, including under
Row step:
It is as follows that S1, IEC103 Standards Code turns IEC61850 Standards Code process:
When described protocol converter receives IEC103 conventions data bag from the serial interface of communication interface modules,
IEC103 conventions data bag is stored in the SDRAM memory of memory module, micro-by high-performance ARM
Reason device reads data from SDRAM memory, and the data completing IEC103 stipulations are changed to IEC61850 stipulations；
Packet after conversion stores in the SDRAM memory of memory module, deciphers AES module through superencipherment
Complete to be stored again in SDRAM memory, through Ethernet after encryption from SDRAM memory read data packet
After controller MAC, by the Ethernet interface of communication interface modules by IEC61850 Standards Code packet
It is transferred to Ethernet；
When described protocol converter receives IEC103 conventions data from the Ethernet interface of communication interface modules
Bag, by IEC103 conventions data bag after physical interface transceiver PHY and ethernet controller MAC,
It is stored in the SDRAM memory of memory module, high-performance ARM microprocessor reads from SDRAM memory
Fetching data, the data completing IEC103 stipulations are changed to IEC61850 stipulations；Packet storage after conversion
In the SDRAM memory of memory module, read from SDRAM memory through superencipherment deciphering AES module
Packet is stored again in SDRAM memory after completing encryption, after ethernet controller MAC, passes through
IEC61850 Standards Code packet is transferred to Ethernet by the Ethernet interface of communication interface modules；
It is as follows that S2, IEC61850 Standards Code turns IEC103 Standards Code process:
When described protocol converter receives IEC61850 stipulations number from the Ethernet interface of communication interface modules
According to bag, IEC61850 conventions data bag, after ethernet controller MAC, is stored in the SDRAM of memory module
In memory, by superencipherment deciphering AES module from SDRAM memory read data packet complete deciphering after again
Secondary storage is in SDRAM memory, and high-performance ARM microprocessor reads data from SDRAM memory, complete
The data becoming IEC61850 stipulations are changed to IEC103 stipulations；Packet after conversion stores memory module
SDRAM memory in, through the serial interface of communication interface modules or Ethernet interface by IEC103 standard
Conventions data bag is transferred to Ethernet.
Further, described IEC103 Standards Code turns IEC61850 Standards Code or IEC61850 standard
Stipulations also include before turning IEC103 Standards Code:
S0, protocol converter start, and first complete FPGA processor and the reset function of each functional module, so
After read boot loader program and stipulations translation-profile from the EFLASH memory of memory module.
The present invention has such advantages as relative to prior art and effect:
1) present invention achieves electric power communication protocol IEC103 standard handovers is IEC61850 standard, for becoming
Power station automation communication protocol realizes the unified solution providing transition.
2) present invention employs superencipherment deciphering AES module, improve the safety of transformer substation communication data
Property.
3) present invention has optical fiber interface, improves speed and the reliability of data transmission.
Accompanying drawing explanation
Fig. 1 is the structured flowchart that the present invention has the IEC61850 communication protocol converter of encrypting and decrypting function；
Fig. 2 is that FPGA processor chip internal designs structured flowchart.
Detailed description of the invention
For making the purpose of the present invention, technical scheme and advantage clearer, clear and definite, develop simultaneously referring to the drawings
The present invention is described in more detail for embodiment.Should be appreciated that specific embodiment described herein is only used
To explain the present invention, it is not intended to limit the present invention.
Embodiment one
The present embodiment proposes a kind of IEC61850 communication protocol converter with encrypting and decrypting function, is one
Plant box-packed module based on FGGA, be external in power system device, change communication protocol, protocol converter
It is applied to existing protecting electrical power system equipment as external connection module.
Its structure, as it is shown in figure 1, it includes FPGA processor, power module, communication interface modules, is deposited
Storage module.FPGA processor is connected with communication interface modules, power module, memory module.Described FPGA
Processor internal design structures as in figure 2 it is shown, embedded high-performance ARM microprocessor, ethernet controller MAC,
UART serial communication interface, superencipherment deciphering AES module, clock module, reseting module and PLL are phase-locked
Ring module；Described communication interface modules includes Ethernet interface and serial interface, and Ethernet interface includes RJ45
Network interface, ST optical fiber interface and physical interface transceiver PHY, serial interface include RS485 physical interface and
RS232 physical interface；Described power module uses AMS1117 power supply voltage stabilizing chip to be that converter is powered；Institute
State memory module and include ROM, EFLASH and SRAM memory.
Embedded high-performance ARM microprocessor is ARM company 32 of described FPGA processor
ARM926EJ-S high-performance processor, for realizing the mutual conversion of IEC103 stipulations and IEC61850 stipulations.
Described 32 ARM926EJ-S high-performance processors are write under Keil4 development environment, and chip embeds
UCOS-II real-time operation program, by each module in instruction control chip, it is achieved conventions data receives,
Conversion between IEC103 stipulations and IEC61850 hough transformation, conventions data sends, tasks carrying, work
The functions such as status monitoring.
The input of described power module power supply is 5V voltage, uses AMS1117 power supply voltage stabilizing chip to provide 3.3V
Galvanic current pressure, powers for protocol converter.
Described FPGA processor embedded superencipherment deciphering AES module, aes algorithm uses dividing of 128bits
Group length and 128bits key length, encryption mode uses CBC group mode, is used for realizing communication data
Encryption and deciphering function.
Described storage module includes: ROM, EFLASH and SRAM memory, wherein the 16KB of Embedded
ROM is for storing the control program of FPGA, and Embedded 10M EFLASH is used for storing boot loader
Program and stipulations translation-profile, Embedded 16KB SRAM is the storage of data in stipulations are changed.
Embedded 4 the UART serial communication interfaces of described FPGA processor, are used for receiving transmission IEC103 rule
About data.
Described communication interface modules includes Ethernet interface and serial interface.Wherein, Ethernet interface includes 2
Individual RJ45 network interface and 2 ST optical fiber interfaces and 2 physical interface transceiver PHY, wherein optical fiber interface choosing
Be the HFBR 5803T of Agilent company, what PHY chip was selected is DP83849IF chip.
Wherein, serial interface includes 2 RS485 physical interfaces and 2 RS232 physical interfaces.
Embedded 2 the 10/100M self adaptation ethernet mac controllers of described FPGA processor, respectively with logical
2 physical interface transceiver PHY of letter interface module are connected.
The embedded clock module of described FPGA processor include RTC Controller real-time clock controller,
Watch dog house dog, Timer timer and OSC32K crystal oscillator.Wherein RTC real-time clock is by 32KHz
Crystal oscillator drives, and provides real-time clock, various clock signals in synchronous converter, watch dog for converter
House dog provides monitoring in real time for converter running status, prevents program fleet, Timer occur under interference
Timer provides the functions such as counting, interruption for translator program.
The embedded reseting module of described FPGA processor is connected with high-performance ARM microprocessor, sends and resets
Signal；It is connected with watch dog house dog, receives reset signal.
The embedded PLL phase-locked loop module of described FPGA processor is for the frequency dividing of clock and frequency multiplication, producing
Multi-level clock, calibrates clock amplitude at different levels and phase place.
Embodiment two
Present embodiment discloses the reality of a kind of IEC61850 communication protocol converter with encrypting and decrypting function
Existing method, described equipment realizes function and specifically comprises the following steps that
1., after equipment described in starts, first complete FPGA processor and the reset function of each functional module, then
Boot loader program and stipulations translation-profile is read from the EFLASH memory of memory module.
It is as follows that 2.IEC103 Standards Code turns IEC61850 Standards Code process:
(1) IEC103 conventions data is received when described protocol converter from the serial interface of communication interface modules
Bag, packet will be stored in the SDRAM memory of memory module, by ARM microprocessor from SDRAM
Memory read data, the data completing IEC103 stipulations are changed to IEC61850 stipulations.Number after conversion
According in bag storage to the SDRAM memory of memory module, through AES encryption deciphering module from SDRAM memory
Read data packet is stored again in SDRAM memory after completing encryption, after ethernet controller MAC,
By the Ethernet interface of communication interface modules, IEC61850 Standards Code packet is transferred to Ethernet.
(2) IEC103 stipulations number is received when described protocol converter from the Ethernet interface of communication interface modules
According to bag, packet, after physical interface transceiver PHY and ethernet controller MAC, is stored in storage mould
In the SDRAM memory of block, ARM microprocessor read data from SDRAM memory, complete IEC103
The data of stipulations are changed to IEC61850 stipulations.Packet after conversion stores the SDRAM of memory module
In memory, again deposit after SDRAM memory read data packet completes encryption through AES encryption deciphering module
Store up in SDRAM memory, after ethernet controller MAC, connect by the Ethernet of communication interface modules
IEC61850 Standards Code packet is transferred to Ethernet by mouth.
3.IEC61850 it is as follows that Standards Code turns IEC103 Standards Code process:
When described protocol converter receives IEC61850 stipulations number from the Ethernet interface of communication interface modules
According to bag, packet, after ethernet controller MAC, is stored in the SDRAM memory of memory module,
After SDRAM memory read data packet completes deciphering, it is stored again in SDRAM by AES encryption deciphering module
In, ARM microprocessor reads data from SDRAM memory, complete the data of IEC61850 stipulations to
IEC103 stipulations are changed.Packet after conversion stores in the SDRAM memory of memory module, through communication
IEC103 Standards Code packet is transferred to Ethernet by serial interface or the Ethernet interface of interface module.
Above-described embodiment is the present invention preferably embodiment, but embodiments of the present invention are not by above-mentioned reality
Execute the restriction of example, the change made under other any Spirit Essence without departing from the present invention and principle, modification,
Substitute, combine, simplify, all should be the substitute mode of equivalence, within being included in protection scope of the present invention.
Claims (9)
1. an IEC61850 communication protocol converter with encrypting and decrypting function, it is characterised in that institute
State protocol converter and include FPGA processor, power module, communication interface modules, memory module, wherein,
Described FPGA processor is connected with described communication interface modules, power module, memory module respectively；
Described FPGA processor is for realizing the mutual conversion of IEC103 stipulations and IEC61850 stipulations；
Described voltage module provides operating voltage for described protocol converter；
Described communication interface modules is for realizing the data exchange of described protocol converter and external equipment；
Described memory module is used for storing data, stipulations translation-profile and boot in stipulations conversion
Loader program, FPGA control program.
A kind of IEC61850 communication protocol with encrypting and decrypting function the most according to claim 1 turns
Parallel operation, it is characterised in that described FPGA processor includes high-performance ARM microprocessor, this high-performance ARM
Microprocessor is 32 ARM926EJ-S high-performance processors, is used for realizing IEC103 stipulations and IEC61850
The mutual conversion of stipulations；
Described 32 ARM926EJ-S high-performance processors are write under Keil4 development environment, and chip embeds
UCOS-II real-time operation program, by each module in instruction control chip, it is achieved conventions data reception,
Conversion between IEC103 stipulations and IEC61850 hough transformation, conventions data transmission, tasks carrying, work
Status monitoring function.
A kind of IEC61850 communication protocol with encrypting and decrypting function the most according to claim 1 turns
Parallel operation, it is characterised in that described FPGA processor includes that superencipherment deciphers AES module, and this module is adopted
With block length and the aes algorithm of 128bits key length of 128bits, encryption mode uses CBC to divide
Group pattern, for realizing encryption and the deciphering function of communication data.
A kind of IEC61850 communication protocol with encrypting and decrypting function the most according to claim 1 turns
Parallel operation, it is characterised in that described storage module includes ROM, EFLASH and SRAM memory, Qi Zhongsuo
State 16KB ROM that ROM memory is Embedded for storing the control program of FPGA, described EFLASH
Memory is that Embedded 10M EFLASH is for storing boot loader program and stipulations conversion configurations literary composition
Part, described SRAM memory is Embedded 16KB SRAM storage of data in stipulations are changed.
A kind of IEC61850 communication protocol with encrypting and decrypting function the most according to claim 1 turns
Parallel operation, it is characterised in that
Described communication interface modules includes Ethernet interface and serial interface, wherein, described Ethernet interface bag
Include 2 RJ45 network interfaces and 2 ST optical fiber interfaces and 2 physical interface transceiver PHY, wherein these ST
Optical fiber interface selects HFBR 5803T, and this PHY chip selects DP83849IF chip；Described serial interface bag
Include 2 RS485 physical interfaces and 2 RS232 physical interfaces.
A kind of IEC61850 communication protocol with encrypting and decrypting function the most according to claim 1 turns
Parallel operation, it is characterised in that
The power supply input of described power module is 5V voltage, uses AMS1117 power supply voltage stabilizing chip to provide 3.3V
Galvanic current pressure, powers for protocol converter.
A kind of IEC61850 communication protocol with encrypting and decrypting function the most according to claim 2 turns
Parallel operation, it is characterised in that described FPGA processor also includes that ethernet controller MAC, UART serial ports leads to
Letter interface, clock module, reseting module and PLL phase-locked loop module；Wherein,
Described clock module include RTC Controller real-time clock controller, watch dog house dog,
Timer timer and OSC32K crystal oscillator, wherein RTC Controller real-time clock controller is by 32KHz
Crystal oscillator drives, and provides real-time clock, various clock signals in synchronous converter for converter；watch dog
House dog provides monitoring in real time for converter running status, prevents program fleet occur under interference；Timer
Timer provides counting, interrupt function for translator program；
Described reseting module is connected with described high-performance ARM microprocessor, sends reset signal；With described
Watch dog house dog connects, and receives reset signal；
Described PLL phase-locked loop module is used for the frequency dividing to clock and frequency multiplication, produces multi-level clock, calibrates at different levels
Clock amplitude and phase place.
8. having an implementation method for the IEC61850 communication protocol converter of encrypting and decrypting function, it is special
Levy and be, comprise the following steps:
It is as follows that S1, IEC103 Standards Code turns IEC61850 Standards Code process:
When described protocol converter receives IEC103 conventions data bag from the serial interface of communication interface modules,
IEC103 conventions data bag is stored in the SDRAM memory of memory module, micro-by high-performance ARM
Reason device reads data from SDRAM memory, and the data completing IEC103 stipulations are changed to IEC61850 stipulations；
Packet after conversion stores in the SDRAM memory of memory module, deciphers AES module through superencipherment
Complete to be stored again in SDRAM memory, through Ethernet after encryption from SDRAM memory read data packet
After controller MAC, by the Ethernet interface of communication interface modules by IEC61850 Standards Code packet
It is transferred to Ethernet；
When described protocol converter receives IEC103 conventions data from the Ethernet interface of communication interface modules
Bag, by IEC103 conventions data bag after physical interface transceiver PHY and ethernet controller MAC,
It is stored in the SDRAM memory of memory module, high-performance ARM microprocessor reads from SDRAM memory
Fetching data, the data completing IEC103 stipulations are changed to IEC61850 stipulations；Packet storage after conversion
In the SDRAM memory of memory module, read from SDRAM memory through superencipherment deciphering AES module
Packet is stored again in SDRAM memory after completing encryption, after ethernet controller MAC, passes through
IEC61850 Standards Code packet is transferred to Ethernet by the Ethernet interface of communication interface modules；
It is as follows that S2, IEC61850 Standards Code turns IEC103 Standards Code process:
When described protocol converter receives IEC61850 stipulations number from the Ethernet interface of communication interface modules
According to bag, IEC61850 conventions data bag, after ethernet controller MAC, is stored in the SDRAM of memory module
In memory, by superencipherment deciphering AES module from SDRAM memory read data packet complete deciphering after again
Secondary storage is in SDRAM memory, and high-performance ARM microprocessor reads data from SDRAM memory, complete
The data becoming IEC61850 stipulations are changed to IEC103 stipulations；Packet after conversion stores memory module
SDRAM memory in, through the serial interface of communication interface modules or Ethernet interface by IEC103 standard
Conventions data bag is transferred to Ethernet.
A kind of IEC61850 communication protocol with encrypting and decrypting function the most according to claim 8 turns
The implementation method of parallel operation, it is characterised in that
Described IEC103 Standards Code turns IEC61850 Standards Code or IEC61850 Standards Code turns
Also include before IEC103 Standards Code:
S0, protocol converter start, and first complete FPGA processor and the reset function of each functional module, so
After read boot loader program and stipulations translation-profile from the EFLASH memory of memory module.
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| CN107493136A (en) * | 2017-10-16 | 2017-12-19 | 中国核动力研究设计院 | A kind of communication protocol conversion device and conversion method |
| CN108462684A (en) * | 2017-12-20 | 2018-08-28 | 山东鲁能智能技术有限公司 | A kind of IEC61850 stipulations conversion module and conversion method |
| CN108768669A (en) * | 2018-08-14 | 2018-11-06 | 杭州创谐信息技术股份有限公司 | Based on ASIC trusted remote memory switching cards and its method for interchanging data |
| CN108777690A (en) * | 2018-06-11 | 2018-11-09 | 山东超越数控电子股份有限公司 | A kind of discretionary security wireless network transmissions method |
| CN110505222A (en) * | 2019-08-14 | 2019-11-26 | 中国电力科学研究院有限公司 | A kind of protocol conversion system and method for the dedicated calibrating installation of power equipment |
| CN112953787A (en) * | 2020-12-07 | 2021-06-11 | 国网辽宁省电力有限公司锦州供电公司 | Storage and transmission method of broadband measurement data |
| CN113569525A (en) * | 2021-06-24 | 2021-10-29 | 合肥松豪电子科技有限公司 | Verification model and method for FPGA verification platform by utilizing SRAM |
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Application publication date: 20160817 |