CN105871532B - A kind of phase synchronous device and method - Google Patents
A kind of phase synchronous device and method Download PDFInfo
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- CN105871532B CN105871532B CN201610191636.8A CN201610191636A CN105871532B CN 105871532 B CN105871532 B CN 105871532B CN 201610191636 A CN201610191636 A CN 201610191636A CN 105871532 B CN105871532 B CN 105871532B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
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- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a kind of phase synchronous device and method, which includes: differential discriminator, to receive signal as input, for removing the modulation intelligence for receiving signal；Error compensator comprising first input end and the second input terminal, first input end are connected with the output end of differential discriminator；Loop filter comprising the first output end and second output terminal, input terminal are connected with the output end of error compensator；First reconstructor, input terminal are connected with the first output end of loop filter, and output end is connected with the second input terminal of error compensator, for generating loop-locking signal；And second reconstructor, input terminal is connected with the second output terminal of loop filter, for the phase locked local carrier of signal to be generated and received according to the signal of the second output terminal of loop filter.
Description
Technical field
The present invention relates to Phase synchronization technical field more particularly to a kind of phase synchronous device and methods.
Background technique
During high-speed digital communication, since environment and other influence factors lead to not be accurately received signal.Example
Such as: due in the residual frequency deviation of receiving end or the influence of remaining skew so that information is misjudged.It is then desired to be carried out to carrier phase
Tracking synchronizes.
A kind of existing phase synchronous device is referred to as section's Stas (Costas) ring, principle structure figure such as Fig. 1 institute
Show.Its advantages are the phase bit flippings that can eliminate signal in carrier modulation.
When actually realizing Costas loop, there are two types of existing ways, a kind of phase synchronous device for built in loop,
As shown in Figure 2 A.Another kind is the external phase synchronous device of loop, as shown in Figure 2 B.Relative to the Phase synchronization built in loop
For device, the external phase synchronous device of loop can allow for differential discriminator therein to introduce delay.
But the phase synchronous device that phase synchronous device or loop either built in loop is external, it is same in phase
It needs to calculate angle during step, this needs biggish calculation amount, therefore to consume more hardware resource.
Summary of the invention
The purpose of the present invention is to provide a kind of phase synchronous device and methods, existing in the prior art above-mentioned to solve
Technical problem.
An embodiment provides a kind of phase synchronous devices, comprising: differential discriminator, using receive signal as
Input, for removing the modulation intelligence for receiving signal；Error compensator comprising first input end and the second input terminal, first
Input terminal is connected with the output end of differential discriminator；Loop filter comprising the first output end and second output terminal, input terminal
It is connected with the output end of error compensator；First reconstructor, input terminal are connected with the first output end of loop filter,
Its output end is connected with the second input terminal of error compensator, for generating loop-locking signal；And second reconstructor,
Input terminal is connected with the second output terminal of loop filter, for being produced according to the signal of the second output terminal of loop filter
The raw phase locked local carrier with reception signal.
Another embodiment of the present invention provides a kind of phase synchronization methods, comprising: removal receives the modulation letter of signal
Breath；Error signal is generated according to the later amplitude of reception signal of removal modulation intelligence and the amplitude of loop-locking signal；Pass through
The amplitude of alignment error signal generates loop-locking signal and reconstruction signal；And by reconstruction signal carry out it is tired multiply produce
The raw phase locked local carrier with reception signal.
Detailed description of the invention
By reading the following detailed description of the preferred embodiment, various other advantages and benefits are common for this field
Technical staff will become clear.The drawings are only for the purpose of illustrating a preferred embodiment, and is not considered as to the present invention
Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.Wherein in the accompanying drawings, reference number
Alphabetic flag later indicates that multiple identical components will omit its last alphabetic flag when referring to these components.Attached
In figure:
Fig. 1 is the principle structure figure of Costas loop；
Fig. 2A is the structure chart of the phase synchronous device built in existing loop；
Fig. 2 B is the structure chart of the external phase synchronous device of existing loop；
Fig. 3 show the structure chart of one embodiment of phase synchronous device of the invention；
Fig. 4 is the flow chart of one embodiment of phase synchronization method of the invention.
In the accompanying drawings, same or similar element is referred to using same or similar label.
Specific embodiment
Carry out detailed description of the present invention illustrative embodiments with reference to the drawings.It should be appreciated that shown in attached drawing and
The embodiment of description is only exemplary, it is intended that is illustrated the principle and spirit of the invention, and is not limited model of the invention
It encloses.
Phase synchronous device and method in the present invention are completed by directly being handled the amplitude vector of complex signal
Phase synchronization.Therefore, the input of each module in following devices and the input of each step in method, are all signals
Amplitude vector rather than the phase of signal.Correspondingly, processed in the treatment process and each step in each module
Journey, and the amplitude vector for complex signal.
Fig. 3 show the structure chart of one embodiment of phase synchronous device 300 of the invention.As shown in figure 3, phase is same
Walking device 300 may include: differential discriminator 301, error compensator 302, loop filter 303, the first reconstructor 304 and the second weight
Structure device 305.
Differential discriminator 301 is to receive signal as input, for removing the modulation intelligence for receiving signal.Since phase modulation is
Given information, it is therefore possible to use any means remove the phase of modulated signal in differential discriminator, such as: it is multiple using two
The method that signal multiplication adds.It in one embodiment of the invention, can also include phase splicing module in differential discriminator, it can be with
Early gate technique late is used to carry out phase splicing to overcome the problems, such as phase cycle-skipping.
Error compensator 302 may include first input end and the second input terminal.First input end can be with differential discriminator
301 output end is connected.Second input terminal can be connected with the output end of the 304 of the first reconstructor.
In one embodiment of the invention, due to the amplitude vector that the input information of error compensator 302 is complex signal,
Therefore, error compensator may be constructed such that by calculating the signal from first input end and the signal from the second input terminal
Conjugate product obtain the phase difference of the two signals.
Loop filter 303 may include the first output end and second output terminal, and input terminal can be with error compensator
302 output end is connected.The signal of the first output end output of loop filter can be used for loop-locking and second exports
The signal of end output can be used for that signal is reconstructed.
Input information due to entering loop filter 303 is the amplitude vector of complex signal, at of the invention one
In embodiment, loop filter 303 may further include range value adjustment module, be configured to by adjusting loop filtering
Keep its value of real part constant while the imaginary values of the input end signal of device 303 to change its phase.It can be by adjusting letter in reply
Number imaginary values simultaneously keep value of real part constant to change its phase.Such as: if phase theta (n) to be synchronized=Δ fn+ Δ
φ can be such that the real part of signal remains unchanged then when being fitted Δ f, and imaginary part is restrained with certain step-length.And it is fitted Δ
Real part can also be made to remain unchanged when φ, and imaginary part is restrained with certain step-length.
Since the range value of the signal after range value adjustment module adjusts the angle can be also changed, in order to protect
The range value for holding signal does not occur big variation, and in one embodiment of the invention, loop filter 303 can be wrapped further
It includes range value and keeps module, be configured to adjust the range value size of module output signal according to range value to add it
It weighs to offset the variation of range value.
In one embodiment of the invention, range value keeps module can be according to following Weighted Rule to its input signal
It is weighted:
When | Sc | when > 4, y=Sc*0.0625；
When 2 < | Sc | when < 4, y=Sc*0.5；
When 0 < | Sc | when < 0.25, y=Sc*8；
When 0.25 < | Sc | when < 0.5, y=Sc*2；
When 0.5 < | Sc | when < 2, y=Sc.
Wherein, Sc indicates the output of range value adjustment module, and y indicates the signal obtained after keeping.
It is emphasized that the rule of above-mentioned point of Pyatyi weighting is an example, also it is segmented into other series and carries out
Weighting, the also adjustable change of the weighted value of every level-one.
Further, since the processing of removal modulation intelligence has been done in differential discriminator 301, so, for using MPSK tune
For the signal of system, as phase theta (n) to be synchronized=Δ fn+ Δ φ, entering parameter to be estimated entrained by the vector of ring is D
=M Δ fn+M Δ φ.Therefore, it needs to be locked with D=M Δ fn+M Δ φ when loop-locking.And signal
In parameter to be estimated be D=Δ fn+ Δ φ, so need to be compensated with D=Δ fn+ Δ φ when being compensated to signal.
The input terminal of first reconstructor 304 can be connected with the first output end of loop filter 303, the first reconstructor
304 output end can be connected with the second input terminal of error compensator 302.In this way, reconstructed through the first reconstructor 304
Signal may be used for generating loop-locking signal.
The input terminal of second reconstructor 305 can be connected with the second output terminal of loop filter 303, the second reconstructor
305 for generating and receiving the phase locked local load of signal according to the signal of the second output terminal of loop filter 303
Wave.That is: the second reconstructor 305 can be with the output signal of output phase synchronizing device 300.
Information due to entering the first reconstructor 304 and the second reconstructor 305 is all the amplitude vector of signal, this
Two reconstructors can reconstruct corresponding signal by the way of carrying out tired multiply to input signal.Work as phase synchronous device
When the signal received is modulated using MPSK, the input signal of the input signal of the first reconstructor 304 and the second reconstructor 305 it
Between meet the relationship of M:1, wherein M indicates the order of modulation of MPSK.
So far phase synchronous device according to an embodiment of the present invention is described, it is same which can reduce phase
Calculation amount during step reduces the consumption to hardware resource.
The present invention also provides a kind of phase synchronization methods.With reference to Fig. 4, Fig. 4 is phase synchronization method 400 of the invention
The flow chart of one embodiment.In one embodiment of the invention, phase synchronization method 400 may include steps of 401
To 404.
In step 401, removal receives the modulation intelligence of signal.
Since phase modulation is Given information, it is therefore possible to use any means remove modulated signal in differential discriminator
Phase, such as: utilize the mutually multiply-add method of two complex signals.It in one embodiment of the invention, can also be using early slow
Gate technique carries out phase splicing to overcome the problems, such as phase cycle-skipping.
In step 402, according to the amplitude of the amplitude of the later reception signal of removal modulation intelligence and loop-locking signal
Generate error signal.
In one embodiment of the invention, error letter can be obtained by calculating the conjugate product of the two signals
Number, the phase difference of the two signals is contained in error signal.
In step 403, loop-locking signal and reconstruction signal are generated by adjusting the amplitude of error signal.
In one embodiment of the invention, value of real part can be kept constant next simultaneously by adjusting the imaginary values of complex signal
Change its phase.Such as: if phase theta (n) to be synchronized=Δ fn+ Δ φ can make signal when being fitted Δ f
Real part remains unchanged, and imaginary part is restrained with certain step-length.And when being fitted Δ φ real part can also remain unchanged, and it is empty
It is restrained with certain step-length in portion.
Since the range value of the signal after being adjusted can be also changed, in order to keep the range value of signal not go out
Now big variation, in one embodiment of the invention, can according to the range value size of range value signal adjusted come pair
It, which is weighted, offsets the variation of range value to compensate.
In one embodiment of the invention, its input signal can be weighted according to following Weighted Rule:
When | Sc | when > 4, y=Sc*0.0625；
When 2 < | Sc | when < 4, y=Sc*0.5；
When 0 < | Sc | when < 0.25, y=Sc*8；
When 0.25 < | Sc | when < 0.5, y=Sc*2；
When 0.5 < | Sc | when < 2, y=Sc.
Wherein, Sc indicates that real part or imaginary part signal adjusted, y indicate the signal after range value is kept.
It is emphasized that the rule of above-mentioned point of Pyatyi weighting is an example, also it is segmented into other series and carries out
Weighting, the also adjustable change of the weighted value of every level-one.
Further, since the processing of removal modulation intelligence has been done in step 401, so, for being modulated using MPSK
Signal for, as phase theta (n) to be synchronized=Δ fn+ Δ φ, entering parameter to be estimated entrained by the vector of ring is D=
M·Δf·n+M·Δφ.Therefore, it needs to be locked with D=M Δ fn+M Δ φ when loop-locking, and in signal
Parameter to be estimated be D=Δ fn+ Δ φ, so need to be compensated with D=Δ fn+ Δ φ when being compensated to signal.
In step 404, by reconstruction signal carry out it is tired multiply generate and receive the phase locked of signal and local carry
Wave.
Can respectively to loop-locking signal and reconstruction signal carry out it is tired multiply, obtain for loop-locking signal and with reception
The phase locked local carrier of signal.
So far phase synchronization method according to an embodiment of the present invention is described, it is same which can reduce phase
Calculation amount during step reduces the consumption to hardware resource.
Claims (2)
1. a kind of phase synchronous device, comprising:
Differential discriminator, to receive signal as input, for removing the modulation intelligence for receiving signal；
Error compensator comprising first input end and the second input terminal, the output of the first input end and the differential discriminator
End is connected, and error compensator is configured to by calculating the signal from first input end and the signal from the second input terminal
Conjugate product obtain the phase difference of the two signals；
Loop filter comprising the first output end and second output terminal, the output end of input terminal and the error compensator
It is connected, the loop filter includes range value adjustment module and range value keeps module, and the range value adjusts module quilt
Keep its value of real part constant while being configured to by adjusting the imaginary values of the input end signal of loop filter to change its phase
Position, the range value keep module to be configured to adjust the range value size of module output signal according to range value come to range value
The output signal of adjustment module is weighted to offset the variation of range value；
First reconstructor, input terminal are connected with the first output end of loop filter, output end and error compensator
Second input terminal is connected, and locks for carrying out the tired generation loop that multiplies by the output signal of the first output end to loop filter
Determine signal；And
Second reconstructor, input terminal is connected with the second output terminal of loop filter, for by loop filter
The signal of second output terminal carries out tired multiply to generate and receive the phase locked local carrier of signal.
2. a kind of phase synchronization method, characterized in that include:
Removal receives the modulation intelligence of signal；
Mistake is generated according to the conjugate product of the amplitude of the later reception signal of removal modulation intelligence and the amplitude of loop-locking signal
Difference signal；
Keep value of real part constant while the imaginary values of alignment error signal to change its phase to obtain the mistake after phase adjustment
Difference signal；
The error signal after phase adjustment is weighted according to the range value size of the error signal after phase adjustment；
And
By to the signal after weighting carry out it is tired multiply generate and receive the phase locked local carrier of signal and loop-locking
Signal.
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