CN105867847B - Access control method, apparatus and system - Google Patents
Access control method, apparatus and system Download PDFInfo
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- CN105867847B CN105867847B CN201610184196.3A CN201610184196A CN105867847B CN 105867847 B CN105867847 B CN 105867847B CN 201610184196 A CN201610184196 A CN 201610184196A CN 105867847 B CN105867847 B CN 105867847B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
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Abstract
The embodiment of the present invention provides a kind of access control method, apparatus and system.This method includes：Processor executes memory setting instruction, and memory setting instruction includes instruction code, original memory address range and target value, and instruction code is the identification information of memory setting instruction；Processor generates memory setting information after executing the memory setting instruction, and memory setting information includes target memory address range and the target value；The processor sends the memory setting information to Memory Controller Hub, so that Memory Controller Hub sets the target value for the value of the corresponding target area of target memory address range described in memory according to memory setting information.The embodiment of the present invention executes memory setting instruction by processor, and memory setting information is sent to Memory Controller Hub, the operation of memory setting is executed by Memory Controller Hub, other operations can be performed in processor, it avoids memory setting from occupying a large amount of processing times of processor, improves the treatment effeciency of processor.
Description
Technical field
The present embodiments relate to field of communication technology more particularly to a kind of access control methods, apparatus and system.
Background technique
With the sustainable development of processor technology, memory access performance has become the principal element for influencing processor performance.All
In more memory access modes, memory setting (memset) class is more important one kind.
Commonly used in initializing one section of continuous memory headroom, the example includes but is not limited to for memory setting class memory access：It answers
With in program to the removing in the specific assignment of array continuous element element, memset library function, GPU to frame buffer zone.This kind of memory access
The characteristics of predominantly memory access range is big, memory access mode is simple.
But memory setting class memory access needs processor to execute access instruction one by one, to occupy a large amount of of processor
The time is handled, the treatment effeciency of processor is caused to be greatly reduced.
Summary of the invention
The embodiment of the present invention provides a kind of access control method, apparatus and system, to improve the treatment effeciency of processor.
The one aspect of the embodiment of the present invention is to provide a kind of access control method, including：
Processor executes memory setting instruction, memory setting instruction include instruction code, original memory address range and
The target value, described instruction code are the identification informations of the memory setting instruction；
The processor generates memory setting information after executing the memory setting instruction, and the memory setting information includes
Target memory address range and the target value；
The processor sends the memory setting information to Memory Controller Hub, so that the Memory Controller Hub is according to described in
The value of the corresponding target area of target memory address range described in memory is set the target value by memory setting information.
The other side of the embodiment of the present invention is to provide a kind of access control method, including：
Memory Controller Hub receives the memory setting information that processor is sent, and the memory setting information includes target memory
Location range and the target value, the memory setting information are that the processor executes the letter generated after the memory setting instruction
Breath, the memory setting instruction include instruction code, original memory address range and the target value, and described instruction code is in described
Deposit the identification information of setting instruction；
The Memory Controller Hub is corresponding by target memory address range described in memory according to the memory setting information
The value of target area is set as the target value.
The other side of the embodiment of the present invention is to provide a kind of memory access control device, including：
Instruction execution module, for executing memory setting instruction, the memory setting instruction includes instruction code, original memory
Address range and the target value, described instruction code are the identification informations of the memory setting instruction；
Memory setting information generating module, for generating memory setting information, the memory setting information includes in target
Deposit address range and the target value；
Sending module, for sending the memory setting information to Memory Controller Hub, so that the Memory Controller Hub foundation
The value of the corresponding target area of target memory address range described in memory is set the target by the memory setting information
Value.
The other side of the embodiment of the present invention is to provide a kind of Memory Controller Hub, including：
Memory setting information receiving module, for receiving the memory setting information of processor transmission, the memory setting letter
Breath includes target memory address range and the target value, and the memory setting information is that the processor execution memory is set
The information generated after instruction is set, the memory setting instruction includes instruction code, original memory address range and the target value, institute
State the identification information that instruction code is the memory setting instruction；
Memory setting module, for according to the memory setting information that target memory address range described in memory is corresponding
The value of target area be set as the target value.
The other side of the embodiment of the present invention is to provide a kind of memory access control system, including memory, the memory access control
Device processed and the Memory Controller Hub.
Access control method provided in an embodiment of the present invention, apparatus and system execute memory setting instruction by processor,
And memory setting information is sent to Memory Controller Hub, the operation of memory setting is executed by Memory Controller Hub, processor is executable
Other operations, avoid memory setting from occupying a large amount of processing times of processor, improve the treatment effeciency of processor.
Detailed description of the invention
Fig. 1 is access control method flow chart provided in an embodiment of the present invention；
Fig. 2 is the system construction drawing that access control method provided in an embodiment of the present invention is applicable in；
Fig. 3 be another embodiment of the present invention provides access control method flow chart；
Fig. 4 be another embodiment of the present invention provides access control method flow chart；
Fig. 5 be another embodiment of the present invention provides access control method flow chart；
Fig. 6 is the structure chart of memory access control device provided in an embodiment of the present invention；
Fig. 7 be another embodiment of the present invention provides memory access control device structure chart；
Fig. 8 is the structure chart of Memory Controller Hub provided in an embodiment of the present invention；
Fig. 9 be another embodiment of the present invention provides Memory Controller Hub structure chart；
Figure 10 is the structure chart of memory access control system provided in an embodiment of the present invention.
Specific embodiment
Fig. 1 is access control method flow chart provided in an embodiment of the present invention；Fig. 2 is memory access provided in an embodiment of the present invention
The applicable system construction drawing of control method.The embodiment of the present invention needs processor to execute memory access one by one for the memory access of memory setting class
Instruction, to occupy a large amount of processing times of processor, causes the treatment effeciency of processor to be greatly reduced, provides memory access control
Method processed, specific step is as follows for this method：
Step S101, processor executes memory setting instruction, and memory setting instruction includes instruction code, original memory
Location range and the target value, described instruction code are the identification informations of the memory setting instruction；
As shown in Fig. 2, the system that access control method provided in an embodiment of the present invention is applicable in includes processor 20, memory control
Device 21 and memory 22 processed, processor 20 be specifically as follows central processing unit (Central Processing Unit, abbreviation CPU),
Graphics processor (Graphics Processing Unit, abbreviation GPU) or the equipment of memory setting class memory access；Processor 20 is logical
It crosses Memory Controller Hub 21 and accesses memory 22, do not access memory 22 directly, processor 20 includes address conversioning unit 201 and high speed
Buffer consistency processing unit 202, Memory Controller Hub 21 include memory access unit 211.When processor 20 need to memory 22 certain
When one region carries out memory setting, processor 20 executes memory setting instruction, and it includes instruction code that the memory setting, which instructs, original
Memory address range and the target value, described instruction code are the identification informations of the memory setting instruction.
Step S102, the described processor generates memory setting information after executing the memory setting instruction, and the memory is set
Confidence breath includes target memory address range and the target value；
Processor 20 generates memory setting information after executing the memory setting instruction, and the memory setting information includes mesh
Memory address range and the target value are marked, the target memory address range is in the memory 22 that processor 20 needs to be arranged
The address range of target area, the address range are specially bound.
Step S103, the described processor sends the memory setting information to Memory Controller Hub, so that the Memory control
Device sets institute for the value of the corresponding target area of target memory address range described in memory according to the memory setting information
State target value.
After processor 20 generates memory setting information, which is sent to Memory Controller Hub 21, memory control
Memory access unit 211 in device 21 processed is according to the memory setting message reference memory 22, specifically, memory access unit 211 is by memory 22
In the value of the corresponding target area of target memory address range be set as the target value.
The embodiment of the present invention executes memory setting instruction by processor, and memory setting information is sent to Memory control
Device is executed the operation of memory setting by Memory Controller Hub, other operations can be performed in processor, and memory setting is avoided to occupy processor
A large amount of processing times, improve the treatment effeciency of processor.
Fig. 3 be another embodiment of the present invention provides access control method flow chart.Method provided in an embodiment of the present invention
Specific step is as follows：
Step S301, processor executes memory setting instruction, and memory setting instruction includes instruction code, original memory
Location range and the target value, described instruction code are the identification informations of the memory setting instruction；
In embodiments of the present invention, memory setting instruction includes instruction code, original memory address range and the target value,
Described instruction code is the identification information of the memory setting instruction.
Step S302, the address that the described original memory address range indicates is virtual address；The processor is by the void
Quasi- address conversion is that physical address obtains the target memory address range and generates memory setting information；
If the original memory address range that memory setting instruction includes indicates when the memory setting instruction that processor 20 executes
Address be virtual address, as shown in Fig. 2, then the virtual address is converted to object by the address conversioning unit 201 in processor 20
Reason address obtains the target memory address range and generates memory setting information, and the memory setting information includes target memory
Address range and the target value.
What target memory address range and original memory address range were directed toward is same region of memory, the difference is that former
Beginning memory address range indicates that target memory address range is indicated with physical address with virtual address.
Step S303, the described processor sends the memory setting information to Memory Controller Hub, so that the Memory control
Device sets institute for the value of the corresponding target area of target memory address range described in memory according to the memory setting information
State target value.
The virtual address is converted to physical address by the address conversioning unit in processor by the embodiment of the present invention, is guaranteed
Memory Controller Hub correctly identifies memory setting information.
Fig. 4 be another embodiment of the present invention provides access control method flow chart.In the corresponding embodiment of Fig. 1 or Fig. 3
On the basis of, processor can also include cache, it is preferred that the embodiment of the present invention is on the basis of Fig. 3 corresponding embodiment, place
Managing device can also include cache, and specific step is as follows for corresponding access control method：
Step S401, processor executes memory setting instruction, and memory setting instruction includes instruction code, original memory
Location range and the target value, described instruction code are the identification informations of the memory setting instruction；
The memory setting instruction includes instruction code, original memory address range and the target value, and described instruction code is
The identification information of the memory setting instruction.
Step S402, the address that the described original memory address range indicates is virtual address；The processor is by the void
Quasi- address conversion is that physical address obtains the target memory address range and generates memory setting information；
Step S403, the corresponding mesh of the target memory address range that the described processor will store in the cache
The value in mark region is write back or in vain；
In embodiments of the present invention, processor further includes cache, which may be stored in the target
The value of the corresponding target area of address range is deposited, the embodiment of the present invention is mainly used for internally depositing the setting that accesses, due to high speed
The address distribution of caching and memory is consistent, and cache is directed toward in same address and the region of memory is consistent, and is
Memory after preventing setting is different from value stored in cache, the access of Memory Controller Hub 21 be arranged memory 22 it
Before, cache coherence processing unit 202 is corresponding by the target memory address range stored in the cache
The value of target area is write back or in vain.
Step S404, the described processor sends the memory setting information to Memory Controller Hub, so that the Memory control
Device sets institute for the value of the corresponding target area of target memory address range described in memory according to the memory setting information
State target value；
Step S405, the described processor receives the mark information that the Memory Controller Hub returns, and the mark information is institute
It states Memory Controller Hub and the information for returning to the processor after memory is successfully set；
20 mark information of processor is returned to after successfully memory is arranged in Memory Controller Hub 21.
Step S406, the described processor generates interruption.
During memory 22 is arranged due to Memory Controller Hub 21, processor 20 may execute other programs, work as processing
Device 20 generates interruption after receiving the mark information that Memory Controller Hub 21 returns to stop executing other processing operations and to respond
Memory setting.
For the embodiment of the present invention before Memory Controller Hub accesses setting memory, cache coherence processing unit will high speed
The value of the corresponding target area of target memory address range stored in caching is write back or in vain, is avoided interior after being arranged
It deposits different from value stored in cache, ensure that the data consistency in memory and cache.
Fig. 5 be another embodiment of the present invention provides access control method flow chart, the embodiment of the present invention sets for memory
Setting class memory access needs processor to execute access instruction one by one, to occupy a large amount of processing times of processor, leads to processor
Treatment effeciency be greatly reduced, provide access control method, specific step is as follows for this method：
Step S501, Memory Controller Hub receives the memory setting information that processor is sent, and the memory setting information includes
Target memory address range and the target value, the memory setting information are that the processor executes the memory setting instruction
The information generated afterwards, the memory setting instruction includes instruction code, original memory address range and the target value, described instruction
Code is the identification information of the memory setting instruction；
As shown in Fig. 2, the system that access control method provided in an embodiment of the present invention is applicable in includes processor 20, memory control
Device 21 and memory 22 processed, processor 20 be specifically as follows central processing unit (Central Processing Unit, abbreviation CPU),
Graphics processor (Graphics Processing Unit, abbreviation GPU) or the equipment of memory setting class memory access；Processor 20 is logical
It crosses Memory Controller Hub 21 and accesses memory 22, do not access memory 22 directly, processor 20 includes address conversioning unit 201 and high speed
Buffer consistency processing unit 202, Memory Controller Hub 21 include memory access unit 211.When processor 20 need to memory 22 certain
When one region carries out memory setting, processor 20 executes memory setting instruction, and it includes instruction code that the memory setting, which instructs, original
Memory address range and the target value, described instruction code are the identification informations of the memory setting instruction.
Processor 20 generates memory setting information after executing the memory setting instruction, and the memory setting information includes mesh
Memory address range and the target value are marked, the target memory address range is in the memory 22 that processor 20 needs to be arranged
The address range of target area, the address range are specially bound.
After processor 20 generates memory setting information, which is sent to Memory Controller Hub 21.
Step S502, the described Memory Controller Hub is according to the memory setting information by the model of target memory address described in memory
The value for enclosing corresponding target area is set as the target value.
Memory access unit 211 in Memory Controller Hub 21 is according to the memory setting message reference memory 22, specifically, memory access list
The value of the corresponding target area of target memory address range in memory 22 is set the target value by member 211.
The embodiment of the present invention executes memory setting instruction by processor, and memory setting information is sent to Memory control
Device is executed the operation of memory setting by Memory Controller Hub, other operations can be performed in processor, and memory setting is avoided to occupy processor
A large amount of processing times, improve the treatment effeciency of processor.
On the basis of Fig. 5 corresponding embodiment, after step S502, further include：
The Memory Controller Hub is to the processor return label information, and the mark information is for indicating the memory control
Memory is successfully arranged in device processed.
Specifically, returning to 20 mark information of processor after successfully memory is arranged in Memory Controller Hub 21.Fig. 6 is the present invention
The structure chart for the memory access control device that embodiment provides.Memory access control device provided in an embodiment of the present invention can execute memory access control
The process flow that embodiment of the method processed provides, the memory access control device can either be located for the processor 21 in above-described embodiment
A module in device 21 is managed, as shown in figure 5, memory access control device 40 includes instruction execution module 41, the life of memory setting information
At module 42 and sending module 43, wherein instruction execution module 41 is for executing memory setting instruction, the memory setting instruction
Including instruction code, original memory address range and the target value, described instruction code is the mark letter of the memory setting instruction
Breath；For memory setting information generating module 42 for generating memory setting information, the memory setting information includes target memory
Location range and the target value；Sending module 43 is used to send the memory setting information to Memory Controller Hub, so that in described
Memory controller sets the value of the corresponding target area of target memory address range described in memory according to the memory setting information
It is set to the target value.
The embodiment of the present invention executes memory setting instruction by processor, and memory setting information is sent to Memory control
Device is executed the operation of memory setting by Memory Controller Hub, other operations can be performed in processor, and memory setting is avoided to occupy processor
A large amount of processing times, improve the treatment effeciency of processor.
Fig. 7 be another embodiment of the present invention provides memory access control device structure chart.On the basis of the above embodiments,
The address that the original memory address range indicates is virtual address；Memory setting information generating module 42 is specifically used for will be described
Virtual address is converted to physical address and obtains the target memory address range and generate memory setting information.
Memory access control device 40 further includes cache coherence processing unit 202, cache coherence processing unit
202 for being write back or nothing the value of the corresponding target area of the target memory address range stored in cache
Effect.
Memory access control device 40 further includes receiving module 44, and receiving module 44 is used to receive what the Memory Controller Hub returned
Mark information, the mark information are that the information that the processor is returned to after memory is successfully arranged in the Memory Controller Hub.
Memory access control device 40 further includes interrupt module 45, and interrupt module 45 receives the label for receiving module 44
Interruption is generated after information.
Memory access control device provided in an embodiment of the present invention can be specifically used for executing the implementation of method provided by above-mentioned Fig. 1
Example, details are not described herein again for concrete function.
The virtual address is converted to physical address by the address conversioning unit in processor by the embodiment of the present invention, is guaranteed
Memory Controller Hub correctly identifies memory setting information；Before Memory Controller Hub accesses setting memory, cache is consistent
The value of the corresponding target area of the memory address range stored in cache is write back or in vain, is avoided by property processing unit
Memory after setting is different from value stored in cache, ensure that memory is consistent with the data in cache
Property.
Fig. 8 is the structure chart of Memory Controller Hub provided in an embodiment of the present invention.Memory control provided in an embodiment of the present invention
Device can execute the process flow of access control method embodiment offer, as shown in figure 8, Memory Controller Hub 80 includes memory setting
Information receiving module 81 and memory setting module 82, wherein memory setting information receiving module 81 is for receiving processor transmission
Memory setting information, the memory setting information includes target memory address range and the target value, the memory setting
Information is that the processor executes the information generated after memory setting instruction, the memory setting instruction include instruction code,
Original memory address range and the target value, described instruction code are the identification informations of the memory setting instruction；Memory setting
Module 82 is used for the value of the corresponding target area of target memory address range described in memory according to the memory setting information
It is set as the target value.
The embodiment of the present invention executes memory setting instruction by processor, and memory setting information is sent to Memory control
Device is executed the operation of memory setting by Memory Controller Hub, other operations can be performed in processor, and memory setting is avoided to occupy processor
A large amount of processing times, improve the treatment effeciency of processor.
Fig. 9 be another embodiment of the present invention provides Memory Controller Hub structure chart.On the basis of Fig. 8, Memory control
Device 80 further includes mark information sending module 83, and mark information sending module 83 is used for the processor return label information,
The mark information is for indicating that memory is successfully arranged in the Memory Controller Hub.
Memory Controller Hub provided in an embodiment of the present invention can be specifically used for executing the implementation of method provided by above-mentioned Fig. 5
Example, details are not described herein again for concrete function.Figure 10 is the structure chart of memory access control system provided in an embodiment of the present invention.The memory access control
System processed can be used for executing access control method described in above-described embodiment, and as shown in Figure 10, memory access control system 100 includes visiting
Deposit control device 40, Memory Controller Hub 80 and memory 90, wherein memory access control device 40 is the corresponding embodiment institute of Fig. 6 or Fig. 7
The memory access control device 40 stated, Memory Controller Hub 80 are Memory Controller Hub 80 described in the corresponding embodiment of Fig. 8 or Fig. 9.
The memory access control system can be used for executing access control method described in above-described embodiment, detailed process and above-mentioned reality
It is consistent to apply example, details are not described herein again.
It is instructed in conclusion the embodiment of the present invention executes memory setting by processor, and memory setting information is sent
To Memory Controller Hub, the operation of memory setting is executed by Memory Controller Hub, processor can be performed other operations, avoid memory setting
The a large amount of processing times for occupying processor, improve the treatment effeciency of processor；It will by the address conversioning unit in processor
The virtual address is converted to physical address, ensure that Memory Controller Hub correctly identifies memory setting information；In Memory Controller Hub
Before access setting memory, cache coherence processing unit is corresponding by the target memory address range stored in cache
The value of target area write back or in vain, the memory after avoiding setting is different from value stored in cache,
It ensure that the data consistency in memory and cache.
In several embodiments provided by the present invention, it should be understood that disclosed device and method can pass through it
Its mode is realized.For example, the apparatus embodiments described above are merely exemplary, for example, the division of the unit, only
Only a kind of logical function partition, there may be another division manner in actual implementation, such as multiple units or components can be tied
Another system is closed or is desirably integrated into, or some features can be ignored or not executed.Another point, it is shown or discussed
Mutual coupling, direct-coupling or communication connection can be through some interfaces, the INDIRECT COUPLING or logical of device or unit
Letter connection can be electrical property, mechanical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
In network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme
's.
It, can also be in addition, the functional units in various embodiments of the present invention may be integrated into one processing unit
It is that each unit physically exists alone, can also be integrated in one unit with two or more units.Above-mentioned integrated list
Member both can take the form of hardware realization, can also realize in the form of hardware adds SFU software functional unit.
The above-mentioned integrated unit being realized in the form of SFU software functional unit can store and computer-readable deposit at one
In storage media.Above-mentioned SFU software functional unit is stored in a storage medium, including some instructions are used so that a computer
It is each that equipment (can be personal computer, server or the network equipment etc.) or processor (processor) execute the present invention
The part steps of embodiment the method.And storage medium above-mentioned includes：USB flash disk, mobile hard disk, read-only memory (Read-
Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic or disk etc. it is various
It can store the medium of program code.
Those skilled in the art can be understood that, for convenience and simplicity of description, only with above-mentioned each functional module
Division progress for example, in practical application, can according to need and above-mentioned function distribution is complete by different functional modules
At the internal structure of device being divided into different functional modules, to complete all or part of the functions described above.On
The specific work process for stating the device of description, can refer to corresponding processes in the foregoing method embodiment, and details are not described herein.
Finally it should be noted that：The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Present invention has been described in detail with reference to the aforementioned embodiments for pipe, those skilled in the art should understand that：Its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (15)
1. a kind of access control method, which is characterized in that including：
Processor executes memory setting instruction, and the memory setting instruction includes instruction code, original memory address range and target
Value, described instruction code are the identification informations of the memory setting instruction；
The processor generates memory setting information after executing the memory setting instruction, and the memory setting information includes target
Memory address range and the target value；
The processor sends the memory setting information to Memory Controller Hub, so that the Memory Controller Hub is according to the memory
The value of the corresponding target area of target memory address range described in memory is set the target value by setting information.
2. the method according to claim 1, wherein the address that the original memory address range indicates is virtual
Address；The processor generates memory setting information after executing the memory setting instruction, including：
The virtual address is converted to the physical address acquisition target memory address range and generates memory by the processor
Setting information.
3. method according to claim 1 or 2, which is characterized in that the processor includes cache；The method is also
Including：
The processor by the value of the corresponding target area of the target memory address range stored in the cache into
Row write time is invalid.
4. according to the method described in claim 3, it is characterized in that, the processor is set to the Memory Controller Hub transmission memory
After confidence breath, further include：
The processor receives the mark information that the Memory Controller Hub returns, the mark information be the Memory Controller Hub at
The information of the processor is returned to after function setting memory.
5. according to the method described in claim 4, it is characterized in that, the processor receives the mark that the Memory Controller Hub returns
After remembering information, further include：
The processor generates interruption.
6. a kind of access control method, which is characterized in that including：
Memory Controller Hub receives the memory setting information that processor is sent, and the memory setting information includes target memory address model
It encloses and target value, the memory setting information is that the processor executes the information generated after memory setting instruction, the memory
Setting instruction includes instruction code, original memory address range and the target value, and described instruction code is the memory setting instruction
Identification information；
The Memory Controller Hub is according to the memory setting information by the corresponding target of target memory address range described in memory
The value in region is set as the target value.
7. according to the method described in claim 6, it is characterized in that, the Memory Controller Hub will according to the memory setting information
The value of the corresponding target area of target memory address range described in memory is set as after the target value, further includes：
The Memory Controller Hub is to the processor return label information, and the mark information is for indicating the Memory Controller Hub
Memory is arranged in success.
8. a kind of memory access control device, which is characterized in that including：
Instruction execution module, for executing memory setting instruction, the memory setting instruction includes instruction code, original memory address
Range and target value, described instruction code are the identification informations of the memory setting instruction；
Memory setting information generating module, for generating memory setting information, the memory setting information includes target memory
Location range and the target value；
Sending module, for sending the memory setting information to Memory Controller Hub, so that the Memory Controller Hub is according to described in
The value of the corresponding target area of target memory address range described in memory is set the target value by memory setting information.
9. memory access control device according to claim 8, which is characterized in that the ground that the original memory address range indicates
Location is virtual address；
The memory setting information generating module is specifically used for being converted to the virtual address into the physical address acquisition target
Memory address range simultaneously generates memory setting information.
10. memory access control device according to claim 8 or claim 9, which is characterized in that further include：
Cache coherence processing unit, the corresponding mesh of the target memory address range for will be stored in cache
The value in mark region is write back or in vain.
11. memory access control device according to claim 10, which is characterized in that further include：
Receiving module, the mark information returned for receiving the Memory Controller Hub, the mark information is the Memory control
The information that processor is returned to after memory is successfully arranged in device.
12. memory access control device according to claim 11, which is characterized in that further include：
Interrupt module generates interruption after receiving the mark information for the receiving module.
13. a kind of Memory Controller Hub, which is characterized in that including：
Memory setting information receiving module, for receiving the memory setting information of processor transmission, the memory setting packet
Target memory address range and target value are included, the memory setting information is generated after the processor executes memory setting instruction
Information, memory setting instruction includes instruction code, original memory address range and the target value, and described instruction code is institute
State the identification information of memory setting instruction；
Memory setting module, for according to the memory setting information by the corresponding mesh of target memory address range described in memory
The value in mark region is set as the target value.
14. Memory Controller Hub according to claim 13, which is characterized in that further include：
Mark information sending module, for the processor return label information, the mark information to be for indicating described interior
Memory is successfully arranged in memory controller.
15. a kind of memory access control system, which is characterized in that including memory, the described in any item memory access controls of such as claim 8-12
Memory Controller Hub described in device processed and claim 13 or 14.
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