CN105848371A - Household wiring-free LED decorative lighting controller - Google Patents

Abstract

The invention provides a household wiring-free LED decorative lighting controller. The input end of the AC power supply of each decorative lighting controller is connected with an original socket and the wiring end of a switching load and the load is removed so that decorative lighting is installed during holidays and unloaded when decorative lighting is not used with no requirement for communication wires or wiring. When an air switch is connected through poking, synchronous operation is performed under the coordinated control of synchronization time and software of each decorative lighting controller.

Description

Household exempts from the LED decorative lamp controller of wiring

(1) technical field:

The ac power input end of each lamp controller is all connected to former socket, the connecing of switching load On line end and remove load, so, loading onto lamp decoration when festivals or holidays, the used time is not unloaded, Need not connect up without order wire, after putting through described air switch, at lock in time and each lamp decoration The software coordinates of controller controls lower synchronous operation.

(2) background technology:

Thered is provided the control system of power supply by power network, its each electronic equipment or intermodule are all by specially With line traffic, correct the timing time of each electronic equipment or electronic module, reach to synchronize fortune Row purpose.Owing to using special circuit communication make wiring complicate and increase cost, if timing Time is not corrected by line traffic, then due to tradition timing error, after running a few hours, its Accumulation timing error can make system control action inconsistent, is likely to result in system crash, at some Often design for change, its products application of occasion that wiring installation amount is big is restricted.

(3) summary of the invention:

The LED decoration system of preset collaborative Synchronization Control, example is used between existing each LED LED such as internal control mode is adornd, and it is to use conventional timing mode to realize Synchronization Control, due to The timing cumulative error of conventional timing mode is big, and each LED is complete in can only being limited in finite time Becoming lamp decoration pattern, its light decorative effect can not be made the most complicated.The present invention relates to household and exempt from wiring LED decorative lamp controller is to set up the lock in time corrected by grid cyclic wave, enables the system to keep long Synchronizing for a long time, capacity of resisting disturbance is strong.

On household self-contained flat main switchboard, miniature circuit breaker comprises multichannel independent air switch, and it is Guide tracked installation and presser type wiring are easy to loading and unloading, and each air switch controls a road electrical equipment and bears Carrying, such as socket, illumination are a road electric appliance load etc., need to select an air according to system Switch, the socket of all or part electric appliance load that this air switch is controlled, device for switching Changing lamp decoration use into, other is constant.A set of self-contained flat installs several lamp controllers, each lamp decoration The ac power input end of controller is all connected on the terminals of described socket, device for switching and moves Removing former device for switching, so, load onto lamp decoration when festivals or holidays, the used time is not unloaded, need not Order wire need not connect up, and after putting through described air switch, controls in lock in time and each lamp decoration Under the software coordinates of device controls, jointly complete overall light decorative effect, the most regular the brightest, Light the darkest, dreamlike, mutually beat and pile up, the multiple Display pattern such as flowing, and keep The permanent rule that synchronizes shows.It shows model selection, is one section of special time after just start, (chase, flicker, pile up, draw curtain etc.) when each lamp controller shows different modes the most jointly, Then selecting the display pattern shutdown corresponding with display mode to preserve, it is to work as in the numbering period When can't detect grid cyclic wave signal, single-chip microcomputer relies on the energy storage of its power capacitor will numbering data It is stored in nonvolatile storage.

The present invention utilizes the positive half cycle ascent stage of power network cycle, takes three and screens some realization to cycle The identification decision of signal, recycling the cycle time set up lock in time, it is achieved each lamp decoration in system The synchronous operation of controller.

The cycle identification circuit of each lamp controller is as in figure 2 it is shown, used hysteresis to compare by three The voltage comparator composition of device, all comprises filter circuit, its voltage ratio in each voltage comparator The reference voltage of relatively device is provided by mu balanced circuit.System arranges clock timer and synchrotimer. If be detected that adjacent two cycle signals are very, then take out this two adjacent cycle letters Clock timer timing time between number zero passage, is sequentially stored in cycle time memory cell, This cycle time memory cell can deposit 100 cycle times, is often stored in a cycle when being filled with Time, the most first remove the cycle time being stored at first, and calculate cycle time of being stored in Meansigma methods Tz also preserves, and utilizes Tz value to differentiate cycle signal to be identified, to reduce power network frequency The impact of rate fluctuation, uses three to screen point simultaneously and reduces erroneous judgement probability.

Three comparators are respectively used to three and screen point, i.e. screen point 0, examination point 1, screen point 2, As shown in Figure 1.At the cycle zero passage of cycle positive half cycle ascent stage, i.e. screen point 0 and electricity is set Pressing through zero comparator, remaining two comparator is separately positioned on cycle positive half cycle ascent stage, peak value Point 1 and the examination point 2 at 50% to 70% place are screened by 35% to 50% place of voltage.

Cycle signal determining: single-chip microcomputer is had no progeny in the setting time opens, and clock timer resets and opens Beginning timing, when cycle voltage zero-cross, is arranged on voltage zero-crossing comparator V0 of examination point 0 Output voltage overturns, and produces at its voltage trailing edge and interrupts, records its zero crossing break period Th0 And close interruption；Hereafter, the output voltage of voltage comparator V1 at point 1 is screened in single-chip microcomputer scanning, When week, wave voltage reached the threshold voltage of V1, output voltage overturns from high to low, scans record Its flip-flop transition Th1；Same scanning record is screened voltage comparator V2 output voltage at point 2 and is turned over Turn time Th2, by output voltage setting value flip-flop transition of Th0 Yu voltage zero-crossing comparator V0 Ts0 makes comparisons；Output voltage setting value Ts1 flip-flop transition of Th1 and voltage comparator V1 with And output voltage setting value Ts2 flip-flop transition of Th2 and voltage comparator V2 makes comparisons respectively, If in the range of allowable error, then this discriminator signal detected is true, is otherwise false.On State and judge that discriminator signal, as true time, calculates this cycle signal zero passage and once screens letter before adjacent Number it is the clock timer timing time Tzu between the cycle signal zero passage of true time, during by it with cycle Between meansigma methods Tz make comparisons, if less than set cycle time error Tzv; cycle signal It is true, at this moment preserves Tzu and take 20ms and be added with synchrotimer timing time, will add up Value be stored in synchrotimer.

When clock timer starts timing with cycle voltage zero-cross, then timing is to 16ms to 18.5ms Between open interruption, clock timer timing to 25ms to 27ms when opening break period setting value Tk Between pass break period setting value Tn time close interrupt.

After system boot, clock timer starts timing, when first all wave voltage mistake being detected When zero, it is arranged on the output voltage upset of voltage zero-crossing comparator V0 screening point 0, thus produces Raw interruption, the time T0 taking out cycle voltage over zero preserves, and is reset by clock timer and opens Beginning timing, at this moment cycle time voltage crosses zero Th0 is 0, and single-chip microcomputer scans as stated above simultaneously And judge discriminator signal.Due to detection is first cycle, and clock timer is at cycle electricity Starting timing when pressing through zero, the value of its Th0, Th1 and Th2 must add cycle time 20ms Deduct out the difference of break period setting value Tk, if three discriminator signals are true, the week of taking-up The time T0 of wave voltage zero crossing is stored in synchrotimer as initial time, and the most i.e. Once opening the break period takes Tk.Being otherwise fictitious time, now the clock timer time must add T0, Continue detection.

When detecting first and during adjacent second cycle voltage zero-cross, owing to not preserving inspection Survey the cycle time, therefore the clock timer timing time between twice cycle signal zero passage be with The cycle time, 20ms made comparisons, it is determined that cycle signal is true time, then be to take 20ms to subtract Th0 Difference be added with synchrotimer timing time, preserve the standard cycle time 20 i.e. for the first time Ms, need to deduct its Th0 value, this is because detect that cycle signal is true time, all the most every time Restart timing after being reset by clock timer when opening interruption, and be will when opening interruption The standard cycle time counts in synchrotimer, and clock timer of having no progeny in opening resets, and otherwise judges Cycle signal is fictitious time, and now the clock timer time must continue by upper plus T1=T0+Tk Method of stating detects first cycle again.After first cycle signal of detection is very, recover with Upper described cycle signal determining.

As it is shown in figure 1, if be detected that cycle signal is false, open the break period all exists next time After this opens the break period, when meansigma methods Tz of time delay cycle time, open interruption, and in opening Have no progeny time delay Tns time close interrupt, arrange pass the break period be when cycle signal screen point 0 time Do not produce interruption, at this moment must start to sweep more than the setting time point of Ts0 allowable error scope Retouch, and when scanning is screened point 1 and screens point 2, voltage comparator output voltage does not produce Upset, is all closing the interruption of break period Tns pass and is stopping scanning, and Tns is:

Tns=Tn-Tk

If be detected that cycle signal is true, then next cycle is opened break period Tks and is:

Tks=Tk+Th0

I.e. from opening for the first time after the break period takes Tk, clock timer is all that timing is opened to Tks Interrupt, and restart timing after clearing, close during timing to Tns and interrupt, so that synchrometer Time the device time corrected by cycle time voltage crosses zero.

Repeat said process.If the upper cycle signal detected described in is true, and this cycle judges Time, discriminator signal is false, or the cycle time detected compares with meansigma methods Tz of cycle time Exceed setting cycle time error Tzv, or clock timer timing is to closing break period setting value During Tns, voltage zero-crossing comparator V0 output voltage does not overturns, and does not produce interruption, then time To closing interruption during Tns during clock timer, at this moment remember that not counting cycle N is 1 and stores, under Once opening the break period is to open the break period in last time to open interruption after Tz, judges the most every time The cycle signal true and false, though if false or this detection discriminator signal is true last time is false, then take N, To restore in memorizer after N+1, clock timer have no progeny in opening unclear zero continue timing, this Time, next cycle of setting opens the break period and temporarily uses out break period interim setting value Tkz instead:

Tkz=(N+1) × Tz

Meanwhile, next cycle pass break period temporarily uses instead and closes break period interim setting value Tnz:

Tnz=Tkz+Tns

When clock timer to after Tkz, scanning is screened the time of point and can be obtained by simple computation ?.If at this moment detecting that cycle signal is true, then take out N in memorizer and preserve, and will deposit N zero setting in reservoir, makes the clock timer clocking value Ts be: (Ts-Tkz) → Ts, at this moment takes (N+1) value of × 20ms is added in synchrotimer, and recover use setting value Tks with Tns, recovered clock timer is had no progeny clearing in opening.

The system synchronization time is the time of synchrotimer, adds current just at the clock meter of timing Time device time.

When judging to screen the some signal true and false, Th0, Th1, Th2 are by exporting with voltage comparator Voltage setting value Ts0 flip-flop transition, Ts1, Ts2 make comparisons and see the most overproof, judge to screen The point signal true and false, can select: Th0, Th1, Th2 are this cycle discriminator signal of true time and are Very, or Th0 is true, and one of Th1, Th2 are true time simultaneously, or Th1, Th2 are true Time, this cycle discriminator signal is true, depending on to judging that cycle signal true and false difference requires.

If system fault, when N is more than a setting value between 25 to 70, owing to being Respectively synchronizing lamp controller in system, the Tz value of its detection may be different with N value, at this moment, and electric power Net frequency cumulative error, being likely to result in the synchrotimer time cannot be by detecting true cycle Corrected during signal, when detecting that cycle signal is true time, use clock timer at Tkz The clocking value at place is directly added in synchrotimer, to reduce the asynchronous time of system, electric power In the case of net normal operation, N is much smaller than 25.

The cycle time error Tzv allowed and the flip-flop transition of voltage comparator output voltage set Value, is taken its meansigma methods by test assessment and obtains.

(4) accompanying drawing explanation:

Fig. 1 is that cycle screens data relationship schematic diagram；

Fig. 2 is cycle discriminator circuit structural representation；

Fig. 3 is the circuit structure block diagram that household exempts from the LED decorative lamp controller of wiring.

(5) detailed description of the invention:

Fig. 3 is the circuit structure block diagram that household exempts from the LED decorative lamp controller of wiring, including: LED 10, lamp controller 11, cycle discriminator circuit 12, electrical equipment 13, Wherein in cycle discriminator circuit 12 and Fig. 2, single-chip microcomputer U0 is included in each lamp decoration respectively In controller 11, electrical equipment 13 finger original electrical equipment in on-off circuit.

Fig. 2 is the structural representation of cycle discriminator circuit 12, by: input circuit S0, Voltage zero-cross detection module V0, voltage comparator V1, voltage comparator V2 structure Become.In Fig. 2, single-chip microcomputer U0 refers to the single-chip microcomputer of lamp controller 11.Wherein input Circuit S0, for mains AC voltage is passed through resistance and the dividing potential drop of diode, is converted to The input voltage that voltage comparator is the most stable.Single-chip microcomputer U0 uses 89C55WD, electricity Press through zero detection module V0, voltage comparator V1, voltage comparator V2 all make With special voltage comparator LM339, its reference voltage is that the mu balanced circuit using stabilivolt comes The threshold voltage of burning voltage comparator.

When mains AC voltage cycle signal zero passage, voltage zero-cross detection module V0's Output voltage saltus step, single-chip microcomputer U0 produces interruption, records break period, simultaneously single-chip microcomputer U0 is additionally operable to the output electricity of scanning voltage comparator V1 and voltage comparator V2 Pressure, when output voltage saltus step record bound-time, be used for judging power network cycle signal thus Produce lock in time.

Claims (2)

1. the present invention relates to household and exempt from the LED decorative lamp controller of wiring, it is characterized in that, by air The socket of all or part electric appliance load, device for switching that switch is controlled change lamp decoration use into, its It is constant, and several lamp controllers installed by a set of self-contained flat, and the power supply of each lamp controller is defeated Enter end be all connected on the terminals of described socket, device for switching and remove device for switching, its display Model selection, is one section of special time after just start, and each lamp controller shows the most jointly When showing different display mode, the display pattern shutdown corresponding with display mode is selected to preserve, it It is that single-chip microcomputer relies on its power capacitor in the numbering period when can't detect grid cyclic wave signal Numbering data are stored in nonvolatile storage by energy storage；

The present invention utilizes the positive half cycle ascent stage of power network cycle, takes three and screens some realization to cycle The identification decision of signal, recycling the cycle time set up lock in time, it is achieved each lamp decoration in system The synchronous operation of controller；

The cycle identification circuit of each lamp controller, by three voltage ratios using hysteresis loop comparator Relatively device forms, and all comprises filter circuit in each voltage comparator, and system arranges clock timer And synchrotimer, if be detected that adjacent two cycle signals are very, then take out this two Clock timer timing time between individual adjacent cycle signal zero passage, when being sequentially stored in cycle Between in memory element, be often stored in a cycle time when being filled with 100 cycle time, the most first move Except the cycle time being stored at first, and calculate meansigma methods Tz of the cycle time being stored in and protect Deposit, utilize Tz value to differentiate cycle signal to be identified；

Three comparators are respectively used to three and screen point, i.e. screen point 0, examination point 1, screen point 2, At the cycle zero passage of cycle positive half cycle ascent stage, i.e. screen point 0 and voltage zero-crossing comparator be set, Remaining two comparator is separately positioned on the cycle positive half cycle ascent stage, the 35% of crest voltage to Examination point 1 at 50% and the examination point 2 at 50% to 70% place；

Cycle signal determining: single-chip microcomputer is had no progeny in the setting time opens, and clock timer resets and opens Beginning timing, when cycle voltage zero-cross, is arranged on voltage zero-crossing comparator V0 of examination point 0 Output voltage overturns, and produces at its voltage trailing edge and interrupts, records its zero crossing break period Th0 And close interruption；Hereafter, the output voltage of voltage comparator V1 at point 1 is screened in single-chip microcomputer scanning, When week, wave voltage reached the threshold voltage of V1, output voltage overturns from high to low, scans record Its flip-flop transition Th1；Same scanning record is screened voltage comparator V2 output voltage at point 2 and is turned over Turn time Th2, if this examination in the range of allowable error, then detected above-mentioned flip-flop transition Signal is true, is otherwise false, above-mentioned judges that discriminator signal, as true time, calculates this cycle signal Clock timer meter between zero passage with the cycle signal zero passage that an adjacent front discriminator signal is true time Time time Tzu, it is made comparisons with meansigma methods Tz of cycle time, if less than set week Ripple time error Tzv then cycle signal is true, at this moment preserves Tzu and takes 20ms and synchrometer Time device timing time be added, the value that will add up is stored in synchrotimer；

When clock timer starts timing with cycle voltage zero-cross, then timing is to 16ms to 18.5ms Between open interruption, clock timer timing to 25ms to 27ms when opening break period setting value Tk Between pass break period setting value Tn time close interrupt；

When first cycle voltage zero-cross being detected, it is arranged on the voltage zero-cross ratio screening point 0 The output voltage upset of relatively device V0, thus produce interruption, take out the time of cycle voltage over zero T0 preserves, and is reset by clock timer and starts timing, at this moment cycle time voltage crosses zero Th0 Being 0, single-chip microcomputer scans as stated above and judges discriminator signal simultaneously, its Th0, Th1 and Th2 Value must deduct open the difference of break period setting value Tk plus cycle time 20ms, if Three discriminator signals are true, and the time T0 of the cycle voltage over zero of taking-up deposits as initial time Entering in synchrotimer, i.e. for the first time open the break period takes Tk next time, is otherwise fictitious time, this Shi Shizhong timer periods must continue detection plus T0；

When detecting first and during adjacent second cycle voltage zero-cross, it is determined that cycle signal For true time, then it is to take 20ms to subtract the difference of Th0 and be added with synchrotimer timing time, no Then judge cycle signal as fictitious time, now the clock timer time must continue plus T1=T0+Tk Continuous first cycle of detection the most again, after first cycle signal of detection is very, Recover above-described cycle signal determining；

If be detected that cycle signal is false, open the break period all when this opens interruption next time After between, when meansigma methods Tz of time delay cycle time, open interruption, and the time delay Tns that has no progeny in opening Time close and interrupt, arranging the pass break period is when cycle signal is being screened as fictitious time, all interrupts closing Time Tns closes and interrupts and stop scanning, and Tns is:

Tns=Tn-Tk

If be detected that cycle signal is true, then next cycle is opened break period Tks and is:

Tks=Tk+Th0

I.e. from opening for the first time after the break period takes Tk, clock timer is all that timing is opened to Tks Interrupt, and restart timing after clearing, close during timing to Tns and interrupt, so that synchrometer Time the device time corrected by cycle time voltage crosses zero；

Repeat said process, if described in the upper cycle signal that detects be true, this cycle judges Time, discriminator signal is false, then close when clock timer timing to Tns and interrupt, at this moment remember not Meter cycle N be 1 and store, open next time the break period be last time opened the break period pass through Open interruption after Tz, judge the cycle signal true and false the most every time, if false or letter is screened in this detection Though number being true but last time is false, then take N, will restore after N+1 in memorizer, clock timer Have no progeny in opening unclear zero continue timing, at this moment, it is temporary transient that next cycle of setting opens the break period Use out break period interim setting value Tkz instead:

Tkz=(N+1) × Tz

Meanwhile, next cycle pass break period temporarily uses instead and closes break period interim setting value Tnz:

Tnz=Tkz+Tns

When clock timer to after Tkz, scanning is screened the time of point and can be obtained by simple computation , if at this moment detecting that cycle signal is true, then take out N in memorizer and preserve, and will deposit N zero setting in reservoir, makes the clock timer clocking value Ts be: (Ts-Tkz) → Ts, at this moment takes (N+1) value of × 20ms is added in synchrotimer, and recover use setting value Tks with Tns, recovered clock timer is had no progeny clearing in opening；

The system synchronization time is the time of synchrotimer, adds current just at the clock meter of timing Time device time；

When judging to screen the some signal true and false, select: Th0, Th1, Th2 are this cycle of true time and discriminate Level signal is true, or Th0 is true, and one of Th1, Th2 are true time simultaneously, or Th1, Th2 is true time, and this cycle discriminator signal is true, depending on to judgement cycle signal true and false difference requirement Fixed；

When N is more than a setting value between 25 to 70, use clock timer at Tkz Clocking value is directly added in synchrotimer.

Household the most according to claim 1 exempts from the LED decorative lamp controller of wiring, its feature It is to include:

LED 10, lamp controller 11, cycle discriminator circuit 12, monolithic Machine U0 and cycle discriminator circuit 12 are included in each lamp controller 11 respectively In；

Wherein cycle discriminator circuit 12, by: input circuit S0, voltage zero-cross detect Module V0, voltage comparator V1, voltage comparator V2 are constituted, and wherein input Circuit S0, for mains AC voltage is passed through resistance and the dividing potential drop of diode, is converted to The input voltage that voltage comparator is the most stable.