CN105842610A

CN105842610A - FPGA circuit transmission delay rest system and method based on TDC

Info

Publication number: CN105842610A
Application number: CN201610199881.3A
Authority: CN
Inventors: 来金梅; 石超; 王健
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2016-03-31
Filing date: 2016-03-31
Publication date: 2016-08-10

Abstract

The invention belongs to the integrated circuit technical filed, and concretely discloses an FPGA (Field Programmable Gate Array) circuit transmission delay test system and method based on a TDC (time-digital converter) method. The test system comprises: a circuit module to be tested, a test excitation generation module, a TDC module, a decoding output module, a time calibration module and a control module. The system can utilize a TDC method to count delay chains, test transmission delay of an FPGA internal circuit more conveniently, and utilize internal resources in an FPGA chip to construct BIST (Build-in Self Test) for test, has the characteristics of low test cost, sound anti-interference performance, great transportability, independence of test tools, etc., and has great application values on test various transmission delay parameters in an FPGA including switch parameters, interconnection delay, combinational logic delay and CLK-Q delay of a configurable logic block (CLB), a programmable input output box (IOB), a block random access memory (BRAM), a digital signal processor (DSP) and a programmable interconnection FPGA combination module circuit.

Description

FPGA circuitry transmission delay based on TDC test system and method

Technical field

The invention belongs to technical field of integrated circuits, be specifically related to a kind of signal to circuit all kinds of in FPGA circuitry chip Transmission delay carries out the system and method tested.

Background technology

Field programmable gate array (Field Programmable Gate Array, FPGA), be a kind of PAL, A kind of semi-custom circuit that developed on the basis of the programming devices such as GAL, CPLD.After chip manufacturing completes, it can also By the way of programming, function is changed according to user's request, and can the most erasable amendment so that during system debug upgrading not Need additionally to change hardware designs, substantially increase design flexibility, shorten the design cycle, reduce design cost.Modern FPGA Being characterized in the programmable logic cells (CLB:Configurable Logic Block) except traditional F PGA, input able to programme is defeated Go out outside unit (IOB:Input Output Box) and interconnection resources, be also integrated with at block storage (BRAM), digital signal The multiple resources such as reason device (DSP:Digital Signal Processing), timer manager (CM:clock managers).

For different application, the function within fpga chip is ever-changing.Although the motility in this design is System design is provided convenience, but also brings stern challenge for system designer.For the development person of fpga chip, remove Ensure fpga chip logically true outside, it is also contemplated that whether the sequential of chip internal meets requirement, the most just can meet User's requirement.

In ASIC field, ATE (Automatic Test Equipment, ATE) is typically used to survey Examination.It is high that such way is faced with testing cost, strong to tester's professional technique requirement property, there is the problems such as off-chip interference. And ATE equipment can only carry out Off-chip test by I/O pin, it is difficult to test chip internal module.Fpga chip can due to it Programming characteristic, it is possible to use self-test on resource composition sheet in sheet (Build-In Self Test, BIST) system, utilizes simple Test instrunment, reach the test result of degree of precision.

Along with FPGA scale, the raising of performance, application scenarios gets more and more, and its timing performance is particularly significant, the lowest one-tenth This, and transmission delay to FPGA internal resource carries out test and becomes a good problem to study [1-quickly and easily 2]。

List of references:

1. Shao Qi, Zhou Hao, next golden prunus mume (sieb.) sieb.et zucc., the realization on FPGA of delay interpolation method TDC of band DLL feedback, " Fudan Journal: natural Science version " the 1st phase in 2015

2. wangdan, Wang Jian, next golden prunus mume (sieb.) sieb.et zucc., a kind of time based on FPGA the Fast Carry Logic, " Fudan Journal: natural science edition ", 1st phase in 2016.

Summary of the invention

It is an object of the invention to provide a kind of easy to use, with low cost, portable good, strong right of capacity of resisting disturbance The system and method tested is carried out in fpga chip internal module signal transmission delay.

The system that the transmission delay to fpga chip internal module that the present invention provides is tested, is based on TDC (Time-to-Digital Converter's, time m-digital converter), its typical structure as shown in Fig. 1, including: treat side Circuit module, test and excitation generation module, TDC module, decoding output module, module time calibration and control module.Wherein, survey Examination excitation generation module is for producing the pumping signal meeting test request, and inputs circuit under test module and TDC module.To be measured The output response of circuit module is same to be accessed in TDC module；TDC module is to from above-mentioned test and excitation generation module and TDC mould Two signals of block process, and produce test result；The output of TDC module is then converted to be easy to reading by decoding output module Binary data；Time calibration, module utilized known stable clock signal to calibrate TDC circuit, it is ensured that measuring accuracy；Control Molding block is then for controlling test and excitation generation module, TDC circuit module and the co-ordination of module time calibration.

TDC circuit developed through decades, and structure is more.Delay interpolation method and slide gauge can be roughly classified into from principle Two kinds of forms of method.Particular circuit configurations is also had multiple optimization to deform by certainty of measurement, device property with the needs etc. of tester.With As a example by conventional delay chain time interpolation method (refer to seminar's paper [1] [2]), its circuit structure is as shown in Figure 2.

As shown in Figure 2 in circuit, the delay of all delay cells is the most identical, is set to Tdelay, and all d type flip flop initial values are all It is 0.If the delay Tx between START rising edge and STOP signal rising edge.Assume that the rising edge of START signal prolongs through N number of Late after unit, STOP signal rising edge arrives and drives d type flip flop, then the Q of top n d type flip flop can be driven high.Utilize decoder After obtaining the value of N, if Tx is delay to be measured, i.e. there is Tx=Tdelay*N, obtain parameter to be measured.If otherwise Tx is known time delay, Then there is Tdelay=Tx/N, reached the purpose of time calibration.

The present invention utilizes FPGA eda tool to produce test circuit, and first-selection determines that parameter physical circuit to be measured realizes, it is ensured that After test and excitation signal provides a rising edge, circuit under test can export a rising edge equally.Then, utilize eda tool by be measured Circuit inserts test platform, and after completing the tasks such as comprehensive, packing, placement-and-routing, generation bit stream file, lower plate survey can be carried out Examination.

The present invention can complete the delayed test of multiple internal resource on fpga chip, and test content includes compiling of FPGA Journey logical block (CLB), input-output unit able to programme (IOB), block storage (BRAM), digital signal processor (DSP), can The switch parameter of the FPGA comprising modules circuit such as programming interconnection, interconnection delay, combination logic delay, CLK-Q delay etc..

Compared to other method of testing, the present invention is little to test device requirement, it is possible to substantially reduce the equipment needed for test And human cost.Have portable strong, the features such as versatility is good, and capacity of resisting disturbance is strong simultaneously.

Accompanying drawing explanation

Fig. 1 delayed test based on TDC technology system block diagram.

Fig. 2 time interpolation method TDC circuit basic structure.

Fig. 3 tests bit stream product process.

Detailed description of the invention

Present system substantially realize flow process as shown in Fig. 2.

Wherein, eda tool is typically chosen the eda tool that fpga chip manufacturer provides voluntarily, such as the ISE system of Xilinx company Row software, or altera corp's Quartus groupware etc..Test platform typically describes with the HDL code form of industrywide standard, And select suitable TDC structure according to the characteristic of FPGA to be measured.Circuit under test can select according to testing requirement to use firmly flexibly The method such as grand (hard macro), IP kernel, HDL code description, only needs it can accept eda tool comprehensively.

As a example by a kind of testing process based on ISE eda software, wherein TDC test platform describes with HDL linguistic form, Circuit under test, for avoiding integrated interference, describes with hard macro form.Before starting test, a first newly-built test in ISE software Engineering also imports the HDL code of TDC circuit, followed by the hard macro literary composition of ISE subordinate's FPGA editor tool making circuit under test Part, finally carries out example to circuit under test hard macro in testing engineering and calls and suitably optimize.By circuit under test and test After platform combines, eda tool can be allowed to automatically generate bit stream.During test, bit stream file is downloaded such as FPGA, and provide and taken After clock and control signal, measurement result can be obtained from outfan.

The present invention directly can obtain digitized measurement result from outfan, for the delay test of FPGA internal resource Particularly convenient, there is testing cost low, the features such as portability is good, highly versatile.

Claims

1. FPGA circuitry transmission delay based on a TDC test system, it is characterised in that including: treat lateral circuit module, test Excitation generation module, TDC module, decoding output module, module time calibration and control module；Wherein, test and excitation generates mould Block meets the pumping signal of test request for producing, and inputs circuit under test module and TDC module；Circuit under test module defeated Go out in response same access TDC module；TDC module is to two signals from above-mentioned test and excitation generation module and TDC module Process, produce test result；The output of TDC module is converted to the binary data being easy to read by decoding output module； Time calibration, module utilized known stable clock signal to calibrate TDC circuit, it is ensured that measuring accuracy；Control module is used for controlling Test and excitation generation module processed, TDC circuit module and the co-ordination of module time calibration.

FPGA circuitry transmission delay based on TDC the most according to claim 1 test system, it is characterised in that test content Including the programmable logic cells (CLB) of FPGA, input-output unit able to programme (IOB), block storage (BRAM), digital signal The switch parameter of the FPGA comprising modules circuit such as processor (DSP), interconnection able to programme, interconnection postpone, combination logic postpones, CLK- Q postpones.

3. based on the FPGA circuitry transmission delay method of testing testing system described in claim 1 or 2, it is characterised in that specifically walk Suddenly it is: utilizing eda tool to produce test circuit, first-selection determines that parameter physical circuit to be measured realizes, it is ensured that test and excitation signal carries For after a rising edge, circuit under test can export a rising edge equally；Then, utilize eda tool that circuit under test is inserted test flat Platform, and after completing comprehensive, packing, placement-and-routing's task, generate bit stream file, lower board test can be carried out.