CN105786719A - NAND Flash memorizer and processing method of bad blocks in memorizer - Google Patents
NAND Flash memorizer and processing method of bad blocks in memorizer Download PDFInfo
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- CN105786719A CN105786719A CN201610121503.3A CN201610121503A CN105786719A CN 105786719 A CN105786719 A CN 105786719A CN 201610121503 A CN201610121503 A CN 201610121503A CN 105786719 A CN105786719 A CN 105786719A
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- 238000003672 processing method Methods 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000002372 labelling Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
Abstract
The embodiment of the invention discloses an NAND Flash memorizer and a processing method of bad blocks in the memorizer. The memorizer comprises a plurality of storage blocks and a mark memorizer body; the mark memorizer body comprises a first storage area, and the number of bits in the first storage area is the same as that of the storage blocks; each bit in the first storage area is in one-to-one correspondence to the corresponding storage block; the values of bits in the first storage area identify the block states of the storage blocks corresponding to the bits. By means of the NAND Flash memorizer and the processing method of bad blocks in the memorizer, the speed in inquiring whether the storage blocks are bad blocks or not is high, work efficiency of the storage process is improved, a standby storage space is arranged in the mark memorizer body, the situation that use of the storage blocks is affected is avoided, and reliability of the memorizer is improved.
Description
Technical field
The present embodiments relate to technical field of memory, particularly relate to the processing method of bad block in a kind of NANDFlash memorizer and memorizer.
Background technology
NANDFlash is the one of Flash internal memory, belongs to non-volatile memory device (Non-volatileMemoryDevice).
Generally comprising X row Y row in NANDFlash chip in memory block (block) unit, (such as with adjacent lines short circuit or certain row open circuit) when damaging occurs in certain row of X-direction time, this memory block cannot normally employ.Owing to General N ANDFlash chip can comprise multiple memory block, more than general thousand, in order to improve chip service efficiency, it is necessary to whether the memory block in NANDFlash chip is damaged and is managed, i.e. bad block management (BadBlockManagement, BBM).The bad block message of this chip is mainly safeguarded, preserves and update to the function of BBM module, it is common that whether preserve this memory block the plug-in bad block latch (badblocklatch) of each memory block is bad mark；Whether each memory block can, when chip dispatches from the factory test, be that the result of bad block is saved in its corresponding bad block latch by BBM module.If again carrying out bad block test in chip uses, testing result can be updated in the bad block latch that each memory block is corresponding by BBM module.Fig. 1 is the structural representation of a kind of NANDFlash memorizer in prior art, referring to Fig. 1.The corresponding memory block of each bad block latch, in FIG, bad block latch 0, bad block latch 1 ..., bad block latch n are corresponding with memory block 0, memory block 1 ..., memory block n respectively, in bad block latch 0, whether what storage had memory block 0 is the information of bad block, in Fig. 1, dotted line with arrow can represent the corresponding relation of bad block storage and memory block, is absent from practice.After the state of detection memory block, the value of bad block latch can by port set put 1 or port rst set to 0, indicate that when the value in bad block latch is 1 the memory block corresponding with this bad block latch is bad block, when the value in bad block latch is 0, indicate the memory block as well block corresponding with this bad block latch.In use, when whether needs reading memory block is bad block, can passing through to enable bblsel port, the value reading bad block latch judges.Such as, after enabling bad block latch 0 by bblsel0, the value of bad block latch 0 can be transmitted to latch bus bblbus, can read the value of latch bus at bblout port, the i.e. value of bad block latch 0, and then can judge whether memory block 0 is bad block according to the value of bad block latch 0.
The defect of the method for above-mentioned plug-in bad block latch has: owing to bad block latch can in use repeatedly be read, and damages so there is a strong possibility, and the bad block latch after damage can not be used for identifying corresponding memory block；It addition, read the value being required for being read bad block latch by latch bus every time, this plug-in bad block latch is that the load of latch bus is big, and reading speed is limited.
Summary of the invention
The embodiment of the present invention provides the processing method of bad block in a kind of NANDFlash memorizer and memorizer, to solve the deficiency of existing bad block management, improves bad block management efficiency.
First aspect, embodiments provides a kind of NANDFlash memorizer, including:
Multiple memory blocks and mark memory；
Described mark memory includes the first memory area, and in described first memory area, number of bits is equal with the number of described memory block；
Each bit in described first memory area and described memory block one_to_one corresponding；
The value of the bit in described first memory area identifies the bulk state of the memory block corresponding with described bit.
Further, described mark memory also includes the second memory area；
Described second memory area includes multiple bit, for replacing the fault bit in described first memory area, and identifies the memory block corresponding with the fault bit in described first memory area.
Further, the value of the bit in described first memory area identifies the bulk state of the memory block corresponding with described bit, including:
When the value of the bit in described first memory area is 1, indicate that the memory block corresponding with described bit is bad block；
When the value of the bit in described first memory area is 0, indicate that the memory block corresponding with described bit is normal blocks.
Wherein, described mark memory is random access memory.
Second aspect, embodiments provides and a kind of includes for the processing method of bad block in the NANDFlash memorizer described in first aspect:
Detect the bulk state of multiple memory blocks in described NANDFlash memorizer, the value of each bit in described first memory area is set according to the bulk state of the plurality of memory block.
Further, when detecting that memory block is bad block, the bit in the mark memory corresponding with described memory block is put 1；
When described memory block is normal blocks, the bit in the described mark memory corresponding with described memory block is set to 0.
Wherein, described mark memory is random access memory.
The technical scheme that the embodiment of the present invention provides, the bulk state of the memory block corresponding with bit is identified with the bit in mark memory, owing to reading the speed of bit, so inquiry memory block whether be the speed of bad block also very fast, improve the work efficiency of memory block, mark memory is provided with spare storage space, bit in spare storage space can be replaced the bit of fault and realize the bad block mark function to memory block, avoid affecting the use of memory block, improve the reliability of memory block use procedure in memorizer.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, introduce the accompanying drawing used required in embodiment or description of the prior art is done one simply below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the structural representation of a kind of NANDFlash memorizer in prior art；
Fig. 2 is the structural representation of a kind of NANDFlash memorizer that the embodiment of the present invention one provides；
Fig. 3 is the structural representation of a kind of NANDFlash memorizer that the embodiment of the present invention two provides；
Fig. 4 is a kind of for the schematic flow sheet of the processing method of bad block in NANDFlash memorizer of the embodiment of the present invention three offer.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearly, hereinafter with reference to the accompanying drawing in the embodiment of the present invention, technical scheme is described clearly and completely by embodiment, it is clear that, described embodiment is a part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under not making creative work premise, broadly fall into the scope of protection of the invention.
Embodiment one
Fig. 2 is the structural representation of a kind of NANDFlash memorizer that the embodiment of the present invention one provides.Referring to Fig. 2, the NANDFlash memorizer that the present embodiment provides includes:
Multiple memory blocks and mark memory；
Wherein, multiple memory blocks are NANDflash memory block, and whether mark memory is bad block for labelling memory block.
Described mark memory includes the first memory area 10, and in described first memory area 10, bit (bite) number is equal with the number of described memory block；
Wherein, mark memory can adopt random access memory.Such as can adopt static RAM (StaticRandomAccessMemory, SRAM) or dynamic random access memory (DynamicRandomAccessMemory, DRAM).First memory area 10 of mark memory stores data with bit for elementary cell.Exemplary, the first memory area 10 there is i bit (bit 0, bit 1 ..., bit i), NANDFlash memorizer have i memory block (memory block 0, memory block 1 ..., memory block i).
Each bit in described first memory area 10 and described memory block one_to_one corresponding；
The value of the bit in described first memory area 10 identifies the bulk state of the memory block corresponding with described bit.
In fig. 2, the bit bit 0 in the first memory area 10, bit 1 ..., bit i respectively with memory block 0, memory block 1 ..., memory block i one_to_one corresponding.The dotted line (being absent from memory) with arrow in figure can represent the one-to-one relationship of the bit in the first memory area 10 and memory block.Bit 0, bit 1 ..., bit i value identify the bulk state of memory block 0, memory block 1 ..., memory block i respectively.Such as, the value of bit 0, the i.e. numerical value of storage in bit 0, for identifying the bulk state of the memory block 0 corresponding with bit 0, mark memory block 0 is normal blocks or bad block.
Further, the value of the bit in described first memory area 10 identifies the bulk state of the memory block corresponding with described bit, including:
When the value of the bit in described first memory area 10 is 1, indicate that the memory block corresponding with described bit is bad block；
When the value of the bit in described first memory area 10 is 0, indicate that the memory block corresponding with described bit is normal blocks.
The technical scheme that the present embodiment provides, the bit in mark memory is used to identify the bulk state of the memory block corresponding with bit, owing to reading the speed of bit, so inquiry memory block whether be the speed of bad block also very fast, need not be read out hanging over outside all bits in mark memory a bus, simple in construction, reading speed is fast, saves hardware resource.
Embodiment two
Fig. 3 is the structural representation of a kind of NANDFlash memorizer that the embodiment of the present invention two provides.Referring to Fig. 3, on the basis of above-described embodiment one, described mark memory also includes:
Second memory area 20；
Described second memory area 20 includes multiple bit, for replacing the fault bit in described first memory area 10, and identifies the memory block corresponding with the fault bit in described first memory area 10.
Using mark memory in memory block bulk state labeling process, mark memory is it is possible that fault.The bit in the second memory area 20 can be used to replace the fault bit in the first memory area 10, for identifying the bulk state of memory block.
Exemplary, referring to Fig. 3, the second memory area 20 can include multiple bit (bit i+1, bit i+2, bit i+3 ...).When bit 2 fault in the first memory area 10, bit i+1 can be used to replace the memory block 2 that bit 2 mark is corresponding with bit 2.
It should be noted that, it is illustrative of in figure 3 illustrating to use the bit in the second standby memory area 20 to replace the fault bit in the first memory area 10, when bit 2 fault, also available bits bit i+2 replaces the memory block 2 that bit 2 mark is corresponding with bit 2, the fallback relationship of the bit in the second standby memory area 20 and the bit in the first memory area 10 is not defined.It addition, the physical address of the physical address of bit i+1 and bit i both can be continuous print, it is also possible to be discontinuous.
The technical scheme that the present embodiment provides, use the second memory area in mark memory as spare storage space, after bit fail in the mark memory of original use, it is possible to use the bit in spare storage space has continued bad block mark function, it is to avoid affect the use of memory block.
Embodiment three
Fig. 4 is a kind of for the processing method of bad block in the NANDFlash memorizer in any of the above-described embodiment of the embodiment of the present invention three offer, and referring to Fig. 4, described method includes:
S310, detect the bulk state of multiple memory blocks in described NANDFlash memorizer；
Generally, when dispatching from the factory or power on, system can detect the bulk state of multiple memory blocks in NANDFlash memorizer, can detect that memory block is normal blocks or bad block by corresponding bad block detection method.
S320, bulk state according to the plurality of memory block arrange the value of each bit in described first memory area.
Further, when detecting that memory block is bad block, the bit in the mark memory corresponding with described memory block is put 1, when described memory block is normal blocks, the bit in the described mark memory corresponding with described memory block is set to 0.
When using the bulk state of mark memory labelling memory block, it is possible to first by the physical address one_to_one corresponding of the physical address of the bit of the first memory area in mark memory Yu memory block.In the bulk state labeling process to memory block, the value of corresponding bit can be set with the corresponding relation of memory block according to bit in mark memory.
Wherein, described mark memory can adopt random access memory.
The technical scheme that the present embodiment provides, uses mark memory to realize the record to the state of memory block, it is achieved that the labelling of bad block in memory block is processed, and facilitates the state use memory block of the memory block that user identify according to mark memory.
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that and the invention is not restricted to specific embodiment described here, various obvious change can be carried out for a person skilled in the art, readjust and substitute without departing from protection scope of the present invention.Therefore, although the present invention being described in further detail by above example, but the present invention is not limited only to above example, when without departing from present inventive concept, other Equivalent embodiments more can also be included, and the scope of the present invention is determined by appended right.
Claims (7)
1. a NANDFlash memorizer, it is characterised in that including:
Multiple memory blocks and mark memory；
Described mark memory includes the first memory area, and in described first memory area, number of bits is equal with the number of described memory block；
Each bit in described first memory area and described memory block one_to_one corresponding；
The value of the bit in described first memory area identifies the bulk state of the memory block corresponding with described bit.
2. memorizer according to claim 1, it is characterised in that described mark memory also includes the second memory area；
Described second memory area includes multiple bit, for replacing the fault bit in described first memory area, and identifies the memory block corresponding with the fault bit in described first memory area.
3. memorizer according to claim 1 and 2, it is characterised in that the value of the bit in described first memory area identifies the bulk state of the memory block corresponding with described bit, including:
When the value of the bit in described first memory area is 1, indicate that the memory block corresponding with described bit is bad block；
When the value of the bit in described first memory area is 0, indicate that the memory block corresponding with described bit is normal blocks.
4. memorizer according to claim 1 and 2, it is characterised in that described mark memory is random access memory.
5. one kind for the processing method of bad block in the arbitrary described NANDFlash memorizer of claim 1-4, it is characterised in that including:
Detect the bulk state of multiple memory blocks in described NANDFlash memorizer；
Bulk state according to the plurality of memory block arranges the value of each bit in described first memory area.
6. method according to claim 5, it is characterised in that when detecting that memory block is bad block, the bit in the mark memory corresponding with described memory block is put 1；
When described memory block is normal blocks, the bit in the described mark memory corresponding with described memory block is set to 0.
7. the method according to claim 5 or 6, it is characterised in that described mark memory is random access memory.
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| CN201610121503.3A CN105786719A (en) | 2016-03-03 | 2016-03-03 | NAND Flash memorizer and processing method of bad blocks in memorizer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110570898A (en) * | 2019-08-13 | 2019-12-13 | 深圳市金泰克半导体有限公司 | Method and device for detecting data processing speed of memory |
| CN112068781A (en) * | 2020-09-10 | 2020-12-11 | 深圳芯邦科技股份有限公司 | Data reading and writing method of memory and related equipment |
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| US20070109856A1 (en) * | 2005-11-08 | 2007-05-17 | Stmicroelectronics S.R.I | Method of managing fails in a non-volatile memory device and relative memory device |
| CN104317733A (en) * | 2014-10-28 | 2015-01-28 | 陕西千山航空电子有限责任公司 | NAND FLASH bad block management method |
| CN104765695A (en) * | 2015-04-03 | 2015-07-08 | 上海交通大学 | NAND FLASH bad block management system and method |
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2016
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Patent Citations (3)
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| US20070109856A1 (en) * | 2005-11-08 | 2007-05-17 | Stmicroelectronics S.R.I | Method of managing fails in a non-volatile memory device and relative memory device |
| CN104317733A (en) * | 2014-10-28 | 2015-01-28 | 陕西千山航空电子有限责任公司 | NAND FLASH bad block management method |
| CN104765695A (en) * | 2015-04-03 | 2015-07-08 | 上海交通大学 | NAND FLASH bad block management system and method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110570898A (en) * | 2019-08-13 | 2019-12-13 | 深圳市金泰克半导体有限公司 | Method and device for detecting data processing speed of memory |
| CN112068781A (en) * | 2020-09-10 | 2020-12-11 | 深圳芯邦科技股份有限公司 | Data reading and writing method of memory and related equipment |
| CN112068781B (en) * | 2020-09-10 | 2024-03-22 | 深圳芯邦科技股份有限公司 | Data reading and writing method of memory and related equipment |
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