CN105743636A - Method for realizing cipher algorithm - Google Patents

Abstract

The invention discloses a method for realizing a high-speed cipher algorithm. The method comprises the following steps: step one, additionally adding one group or multiple groups of data registers in a cipher algorithm module; step two, when data in any one group or any groups of the data registers meets operation conditions, hardware automatically starting operation; and step three, at the time when the hardware calculates one group of the data registers, software writing the data into other groups of data registers. According to the invention, the time of waiting for the software to write the data can be reduced or eliminated, and the computation can be completed more rapidly.

Description

The method realizing cryptographic algorithm

Technical field

The present invention relates to field of cryptography, particularly relate to a kind of method realizing high speed password algorithm.

Background technology

In the current information age, a large amount of sensitive informations such as court records, proprietary documents, software source code, bank transaction, insurance document etc. swap often through public communication infrastructure or computer network, in order to ensure the privacy of these information, integrity, verity etc., it is necessary to use cryptographic algorithm that raw information is processed.

Cryptographic algorithm is the mathematical function for encrypting and deciphering, for the safety of guarantee information, it is provided that discriminating, integrity, resisting denying etc. service, and existing cryptographic algorithm is broadly divided into symmetric key algorithm, asymmetric key algorithm and hash algorithm three major types.Symmetric key algorithm is also known as secret-key algorithm, and its encryption key is identical with decruption key, or is substantially the same, and is prone to release another from one.The safety of symmetric key algorithm depends on the secrecy to key, and leakage key means that anyone the message deciphering that they can be sent or receive, so the confidentiality of key is most important.Asymmetric key algorithm is also known as public key algorithm, and public key algorithm uses a key to be encrypted, and is decrypted with another key；Wherein encryption key can disclose, and also known as public-key cryptography, is called for short PKI, and decruption key must maintain secrecy, and also known as private key, is called for short private key.Hash algorithm does not need key, but by hash (" hash " or title " Hash ") function, the message Iteration Contraction of random length is become the eap-message digest of regular length, and this Iteration Contraction process is unidirectional, in order to guarantee message integrity.

Fig. 1 is existing conventional cipher algorithm flow chart.In traditional process realizing cryptographic algorithm, before cryptographic algorithm module arithmetic, write key, data and other relevant configured parameters firstly the need of software；Then software starts hardware and starts computing, and after these group data current complete etc. hardware computation are stopped, software could write next group data, and software is restarted hardware and started computing, so circulates, until having calculated all of data；Running it can be seen that this method is software and hardware serial, after only hardware has calculated these group data current, software could write next group data, wastes the time of more wait software write data.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of method realizing high speed password algorithm, it is possible to reduces or eliminates the time waiting software write data, completing computing faster.

For solving above-mentioned technical problem, the method realizing high speed password algorithm of the present invention, comprise the steps:

Step 1, extra one or more groups data register of increase in cryptographic algorithm module；

Step 2, after the data in any one group or multi-group data depositor meet calculation condition (such as length etc.), hardware starts computing automatically；

Step 3, when hardware is while computing one of which data register, is organized write data in data register by software to other.

Further, it is additionally included in step 1, additionally increases one or more groups cipher key register in cryptographic algorithm module.

The present invention is by increasing by one group of data register, these group data current for hardware computation and software are write next group data relatively independent, allow the data in one group of data register while participating in hardware computation, software is organizing data register write data toward another, after these group data current complete etc. hardware computation, software or write or be currently written into next organize calculative data, no matter it is any situation, can greatly reduce or eliminate the time waiting software write data, improve hardware utilization fully, thus decreasing the operation time of entirety, therefore, it is possible to complete computing faster.

Other advantages of the present invention, purpose and feature will partly illustrate in the description that follows, and for those of ordinary skills, partial content will be made apparent from when examining following content, or can be learnt by the practice of the present invention.Utilize the structure specifically noted in written description and claim and accompanying drawing thereof, it is possible to achieve with reach the purpose of the present invention and other advantages.

Accompanying drawing explanation

Below in conjunction with accompanying drawing, the present invention is further detailed explanation with detailed description of the invention:

Fig. 1 is existing cryptographic algorithm flow chart；

Fig. 2 is the described flow chart realizing high speed password algorithm；

Fig. 3 is the flow chart realizing high speed SM3 hash algorithm.

Detailed description of the invention

Shown in Fig. 2, the described method realizing high speed password algorithm is as follows:

Step 1, increases one or more groups data register to cryptographic algorithm module.

Step 2, the relevant configured parameter of write cryptographic algorithm module.

Step 3, the key of write cryptographic algorithm module.

Step 4, writes first group of testing data B⁽⁰⁾, hardware starts computing automatically, and namely hardware calculates grouped data B⁽ⁱ⁾, i=0.While hardware computation, software continue to write next group testing data toward another group data register.

Step 5, it is judged that whether software writes grouped data B⁽ⁱ⁺¹⁾, if so, then perform step 6, otherwise hardware stops calculatings, and wait software writes grouped data B⁽ⁱ⁺¹⁾。

Step 6, hardware calculates grouped data B⁽ⁱ⁺¹⁾, i=i+1.

Step 7, it is judged that whether hardware has calculated last grouped data, if so, then performs step 8, otherwise returns step 5.

Step 8, terminates this computing.

If hardware has calculated one group of data, to write one group of data than software fast, then software is but without writing next group data after having calculated these group data current for hardware, and therefore hardware needs to be stopped for after software writes next group data self-starting again and calculates；Otherwise, if hardware has calculated one group of data, to write one group of data than software slow, so hardware is but without having calculated these group data current when writing next group data for software, and therefore software needs to be stopped for hardware and calculated currently write data again after these group data.

Repetitive cycling step 5 and step 6, until all testing data computings are complete.

Carry out the principle realizing high speed password algorithmic method below illustrating:

Realizing the core concept of the method for high speed password algorithm is software is write data and hardware computation is relatively independent, and therefore software writes one group of data and the complete one group of data of hardware computation exist speed speed problem, is divided into two kinds of situations here:

The first situation be software write one group of data than hardware computation complete one group of data slow, after complete these group data current of hardware computation, software is but without writing next group data, hardware needs to be stopped for after software writes next group data self-starting again and calculates, and therefore decreases the time waiting software write data；

The second situation be software write one group of data than hardware computation complete one group of data fast, software write next group data after hardware but without complete these group data current of computing, therefore software needs to be stopped for after complete these group data current of hardware computation write data again, it is thus eliminated that wait the time of software write data.

Shown in Fig. 3, the embodiment that realize high speed SM3 hash algorithm being presented herein below, concrete implementation flow process is as follows:

Step one, is filled with the origination message m that length is L bit, obtains the filling message m of the extension of n times that length is 512 bits '.

Step 2, will the filling message m of extension ' it is divided into the message packet of n 512 bit lengths, i.e. m '=B⁽⁰⁾…B^(n-1)。

Step 3, write SM3 hash algorithm module relevant configured parameter and first message packet B⁽⁰⁾。

Step 4, hardware starts calculating automatically, and namely hardware calculates packet packet B⁽ⁱ⁾, i=0.While hardware computation, continue toward the next message packet B of another group data register write software⁽ⁱ⁾。

Step 5, it is judged that whether software writes message packet B⁽ⁱ⁺¹⁾.At the complete current message packet B of hardware computation⁽ⁱ⁾After, if software has write next message packet B⁽ⁱ⁺¹⁾, hardware will continue computing message packet B⁽ⁱ⁺¹⁾And do not stop；If software does not write next message packet B⁽ⁱ⁺¹⁾, hardware will temporarily cease computing, wait software to write next message packet B⁽ⁱ⁺¹⁾After self-starting computing again.

Step 6, repeats step 5, until all message packet B⁽⁰⁾～B^(n-1)Computing is complete.

Step 7, terminates this hash computing and reads the digest value of message m from summary depositor.

Above by detailed description of the invention, the present invention is described in detail, but these have not been construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art it may also be made that many deformation and improvement, and these also should be regarded as protection scope of the present invention.

Claims (2)

1. the method realizing cryptographic algorithm, it is characterised in that:

Step 1, additionally increases one or more groups data register in cryptographic algorithm module；

Step 2, after the data in any one group or multi-group data depositor meet calculation condition, hardware starts computing automatically；

Step 3, when hardware is while computing one of which data register, is organized write data in data register by software to other.

2. the method for claim 1, it is characterised in that: it is additionally included in step 1, additionally increases one or more groups cipher key register in cryptographic algorithm module.