CN105721360B - A kind of terminal reception device and its data receiver method - Google Patents
A kind of terminal reception device and its data receiver method Download PDFInfo
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Abstract
The present invention relates to field of communication technology, a kind of terminal reception device and its data receiver method are disclosed.In the present invention, terminal reception device includes: antenna, pre-processing module, channel estimation module, HS-SCCH receiving module, HS-SCCH send signal recovery module, HS-SCCH assisted channel estimation module and/or HS-SCCH interference cancellation module；Antenna is connected with pre-processing module, and pre-processing module is connected with channel estimation module, HS-SCCH receiving module, and HS-SCCH receiving module is connected with channel estimation module；HS-SCCH sends signal recovery module and is connected with HS-SCCH receiving module, HS-SCCH assisted channel estimation module sends signal recovery module with HS-SCCH respectively, channel estimation module is connected, and HS-SCCH interference cancellation module sends signal recovery module with HS-SCCH respectively, channel estimation module is connected.In this way, making full use of correctly received HS-SCCH as Given information when carrying out HS-PDSCH reception processing, carrying out assisted channel estimation, channel estimating performance can be promoted；And/or interference elimination is carried out to HS-SCCH, HS-PDSCH receptivity can be improved.
Description
Technical field
The present invention relates to field of communication technology, in particular to a kind of terminal reception device and its data receiver method.
Background technique
WCDMA (wideband code division multiple access) is 3G one of the mainstream standard, and current development is highly developed, key technology
It is CDMA (CDMA).For WCDMA, terminal receiver generally uses RAKE (rake) receiver, in WCDMA downlink
It is middle to provide Packet data service using HSDPA (high-speed slender body theory).
For HSDPA, because spreading factor only has 16, in order to improve receptivity, Chip level equaliser is generally used.
General WCDMA HSDPA receiver is as shown in Figure 1, (high comprising: antenna, pre-processing module, channel estimation module, HS-SCCH
Fast shared control channel) receiving module, Chip level equaliser, descrambling and de-spreading demodulation module and bit level processor.
Wherein, antenna, for receiving data；
Pre-processing module, for the received data of antenna to be transformed to base band data, can be also used for base band data into
Row some pretreatments, such as direct current offset elimination, frequency offset correction etc.；
HS-SCCH receiving module for receiving pretreated data, and carries out decoding to received data and obtains HS-
SCCH information；
Channel estimation module, for carrying out channel estimation using CPICH (CPICH Common Pilot Channel)；
Chip level equaliser for the result to channel estimation and receives data in Chip grades of progress equilibrium treatments；
Descrambling and de-spreading demodulation module for removing scrambling code, spread spectrum to the data after equilibrium treatment, and is demodulated to obtain soft
Bit；
Bit level processor, for the processing such as being deinterleaved, solving rate-matched, decoding to soft bit.
HSDPA business is dynamic dispatching, and terminal is by blind Detecting HS-SCCH, if being correctly detecting HS-SCCH,
It goes to solve its corresponding HS-PDSCH (High-Speed Physical Downlink Shared Channel).Specifically, it is once configured with HSDPA information,
Terminal needs to monitor HS-SCCH channel set, if terminal detects the HS-SCCH control command of oneself, and the channel of its configuration
Change code and modulation system meets the ability of terminal, terminal just starts to receive HS-PDSCH channel.
Wherein, HS-SCCH and HS-PDSCH sending time difference is 2 Slot (time slot), and UE (terminal) is demodulating HS-
The first part of SCCH determines whether to need to receive subsequent HS-PDSCH channel.The timed-shutoff of HS-SCCH and HS-PDSCH
System is as shown in Fig. 2A and Fig. 2 B (Data Packet is data packet), and HS-SCCH ratio HS-PDSCH shifts to an earlier date 2 time slots and sends, UE
First time slot for receiving HS-SCCH just obtains whether current information issues oneself using the demodulation of a time slot, keeps away
The data buffer storage of HS-PDSCH chip-level is exempted from, to reduce the pressure of buffer and the restitution delay of HS-PDSCH.
The above-mentioned design to reduce buffer, when primarily directed to rigid introducing HSDPA, the lower terminal of ability rating, and
Nowadays, after HSPA+ (enhanced high-speed grouping access) introduces 64QAM (phase quadrature amplitude modulation), for depositing for soft bit
Reserves demand has been over the storage demand of Chip grades of data, therefore Chip grades of data buffer storages have not been the bottlenecks of design
?.Wherein, the amount of storage that 2ms Chip grades of data need is 245.76kbits；2ms soft bit need amount of storage be
345.6kbits。
From the above analysis, the memory of soft bit is stored, the Chip grade data of about 4.2 time slots can be cached.
In addition, the energy power limit of data processing is also smaller and smaller with the promotion of receiver processor ability.
However, HS-SCCH is correctly received, has changed into known letter when carrying out HS-PDSCH reception processing
Breath, current receiver do not make full use of this point.
Summary of the invention
The purpose of the present invention is to provide a kind of terminal reception device and its data receiver methods, can make full use of HS-
SCCH carries out assisted channel estimation as Given information, promotes channel estimating performance；And/or HS-SCCH can be done
Elimination is disturbed, HS-PDSCH receptivity is improved.
In order to solve the above technical problems, embodiments of the present invention provide a kind of terminal reception device, include: antenna,
Pre-processing module, channel estimation module, high-speed shared control channel HS-SCCH receiving module, HS-SCCH send signal and restore mould
Block, HS-SCCH assisted channel estimation module and/or HS-SCCH interference cancellation module；
Antenna is connected with pre-processing module, and pre-processing module is connected with channel estimation module, HS-SCCH receiving module,
HS-SCCH receiving module is connected with channel estimation module；HS-SCCH sends signal recovery module and HS-SCCH receiving module phase
Even, HS-SCCH assisted channel estimation module sends signal recovery module with HS-SCCH respectively, channel estimation module is connected, HS-
SCCH interference cancellation module sends signal recovery module with HS-SCCH respectively, channel estimation module is connected；
The antenna, for receiving data；
The pre-processing module, for being converted to base band data to the received data of antenna, and to the base band data into
Row pretreatment；
The channel estimation module obtains the first channel and estimates for carrying out channel estimation using CPICH Common Pilot Channel CPICH
Count result H1；
The HS-SCCH receiving module is carried out for receiving pretreated data and the H1, and to received data
Decoding obtains HS-SCCH information；
The HS-SCCH sends signal recovery module, for carrying out coded modulation to the HS-SCCH information, spread spectrum, adding
It disturbs, restores HS-SCCH and send signal；
The HS-SCCH assisted channel estimation module is estimated for sending signal using the HS-SCCH as pilot tone progress channel
Meter obtains second channel estimated result H2, and is weighted and averaged to the H1 and the H2, the channel estimation after obtaining weighting
As a result H；
The HS-SCCH interference cancellation module sends signal for restoring HS-SCCH interference signal, and from HS-SCCH
In subtract the HS-SCCH interference signal of recovery.
Embodiments of the present invention additionally provide a kind of data receiver method comprising the steps of:
The received data of antenna are converted to base band data by pre-processing module, and are pre-processed to the base band data；
Channel estimation module carries out channel estimation using CPICH Common Pilot Channel CPICH, obtains the first channel estimation results H1；
HS-SCCH receiving module receives pretreated data and the H1, and carries out decoding acquisition to received data
HS-SCCH information；
HS-SCCH sends signal recovery module and carries out coded modulation, spread spectrum, scrambling to the HS-SCCH information, restores
HS-SCCH sends signal；
It is that pilot tone carries out channel estimation, acquisition that HS-SCCH assisted channel estimation module, which sends signal using the HS-SCCH,
Two channel estimation results H2, and the H1 and the H2 are weighted and averaged, the channel estimation results H after obtaining weighting；With/
Or
HS-SCCH interference cancellation module restores HS-SCCH interference signal, and sends in signal from HS-SCCH and subtract recovery
HS-SCCH interference signal.
Embodiment of the present invention is in terms of existing technologies, sufficiently sharp when carrying out HS-PDSCH reception processing
It uses correctly received HS-SCCH as Given information, assisted channel estimation is carried out, in this way, channel estimation can be promoted
Energy；And/or interference elimination is carried out to HS-SCCH, in this way, HS-PDSCH receptivity can be improved.
Further, the HS-SCCH receiving module, the HS-SCCH of each subframe can be received after again into
Row joint decoding, and verified using cyclic redundancy check code CRC.In this way, decoding result is more reliable.
In addition, the HS-SCCH interference cancellation module, is rolled up by sending signal to the H1 and HS-SCCH
Product restores HS-SCCH interference signal.Restore the technology that interference signal is existing maturation by convolution, ensure that implementation of the present invention
The feasibility of mode.
Detailed description of the invention
Fig. 1 is the block diagram of WCDMA HSDPA receiver in the prior art；
Fig. 2A is the timing relationship schematic diagram of HS-SCCH and HS-PDSCH in the prior art；
Fig. 2 B is the timing relationship schematic diagram of HS-SCCH and HS-PDSCH in the prior art；
Fig. 3 is the structural schematic diagram of the terminal reception device of first embodiment according to the present invention；
Fig. 4 is the timing relationship schematic diagram of the HS-SCCH in first embodiment and HS-PDSCH according to the present invention；
Fig. 5 is the structural schematic diagram of the terminal reception device in second embodiment according to the present invention；
Fig. 6 is the timing relationship schematic diagram of the HS-SCCH in second embodiment and HS-PDSCH according to the present invention；
Fig. 7 is the structural schematic diagram of the terminal reception device of third embodiment according to the present invention；
Fig. 8 is the data receiver method flow diagram of the 4th embodiment according to the present invention；
Fig. 9 is the data receiver method flow diagram of the 5th embodiment according to the present invention；
Figure 10 is the data receiver method flow diagram of sixth embodiment according to the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to each reality of the invention
The mode of applying is explained in detail.However, it will be understood by those skilled in the art that in each embodiment of the present invention,
In order to make the reader understand this application better, many technical details are proposed.But even if without these technical details and base
In the various changes and modifications of following embodiment, each claim of the application technical side claimed also may be implemented
Case.
It is specific as shown in figure 3, including antenna, preceding place the first embodiment of the present invention is related to a kind of terminal reception device
It manages module, channel estimation module, High-Speed Shared Control Channel (HS-SCCH) receiving module, HS-SCCH and sends signal recovery mould
Block, HS-SCCH assisted channel estimation module, Chip level equaliser, descrambling and de-spreading demodulation module, bit level processor, first are delayed
Rush memory and the second buffer storage.
Wherein, antenna is connected with pre-processing module, for receiving data, and received data is exported to pre-treatment mould
Block.The received data of antenna can be rf data.
Pre-processing module is connected with channel estimation module, HS-SCCH receiving module.Pre-processing module is received to antenna
Data are converted to base band data, and carry out the pretreatment such as direct current offset elimination, frequency offset correction to base band data, after also pre-processing
Data exported respectively to channel estimation module, HS-SCCH receiving module.Pre-processing module to the pretreatment of data be it is existing at
Ripe technology, details are not described herein.
Channel estimation module and pre-processing module, HS-SCCH receiving module, HS-SCCH assisted channel estimation module are homogeneous
Even.Channel estimation module carries out channel estimation to the pretreated data of pre-processing module using CPICH Common Pilot Channel (CPICH),
It obtains the first channel estimation results (H1), and the H1 that will acquire is exported respectively to HS-SCCH receiving module, HS-SCCH auxiliary letter
Road estimation module.The technology that channel estimation is existing maturation is carried out using CPICH, details are not described herein.
HS-SCCH receiving module and pre-processing module, channel estimation module, HS-SCCH transmission signal recovery module are homogeneous
Even.HS-SCCH receiving module receives the H1 of the pretreated data of pre-processing module and channel estimation module output, and to reception
Data carry out decoding obtain HS-SCCH information, the HS-SCCH information that also will acquire export to HS-SCCH send signal restore
Module.In the present embodiment, HS-SCCH receiving module individually translates first time slot of each HS-SCCH subframe
Code.According to the processing capacity of current mainstream processor, HS-SCCH receiving module receive decoding processing a time slot time delay it
It is interior to complete.
First buffer storage is connected with HS-SCCH receiving module, for caching pretreated data.In this embodiment party
In formula, the first buffer storage only caches the Chip grade data of 3 time slots, specifically as shown in figure 4, in HS-SCCH 3N+4
At the end of gap (dotted arrow position in figure), completes the HS-SCCH decoding of n-th subframe and send signal recovery, 3N
The decoding and the corresponding transmission signal recovery for sending signal of+3 time slots, at this moment start the HS-PDSCH data to n-th subframe
It receives, can use recovered HS-SCCH information (n-th subframe and the 3N+3 time slot) in this way and carry out auxiliary channel
Estimation promotes channel estimating performance.
HS-SCCH sends signal recovery module and HS-SCCH receiving module, HS-SCCH assisted channel estimation module are homogeneous
Even.HS-SCCH sends signal recovery module and carries out coded modulation according to standardising process to received HS-SCCH information, spread spectrum, adds
It disturbs, restores HS-SCCH and send signal, it can obtain the corresponding Chip grades of transmission data of HS-SCCH, the process is fully according to rule
Model requires to carry out.Wherein, standardising process herein is that channel as defined in 3GPP (third generation partner program) standardizes is compiled
Code and spectrum-spreading and scrambling process.HS-SCCH sends signal recovery module and also exports the HS-SCCH transmission signal of recovery to HS-
SCCH assisted channel estimation module.
HS-SCCH assisted channel estimation module and channel estimation module, HS-SCCH send signal recovery module, Chip grades
Balanced device is connected.HS-SCCH assisted channel estimation module sends the HS-SCCH hair that signal recovery module is restored with HS-SCCH
The number of delivering letters is that pilot tone carries out channel estimation, is obtained second channel estimated result (H2), and H2 and channel estimation module are exported
H1 is weighted and averaged, the channel estimation results (H) after obtaining weighting.HS-SCCH assisted channel estimation module also by H export to
Chip level equaliser.In this way, obtaining the channel estimation after weighting by being weighted to H1, H2, channel estimation can be improved
Performance.
Specifically, H and H1, H2 meet following relationship:
H=a*H1+ (1-a) * H2
Wherein, a is weighted factor；The value of a is
Wherein, s is Transfer Parameters, and the value of s is
Wherein, SF1 And SF2 The respectively corresponding spreading factor of CPICH, HS-SCCH；P1 And P2 Respectively CPICH, HS-
The transmission power of SCCH.
Chip level equaliser and pre-processing module, HS-SCCH assisted channel estimation module, descrambling and de-spreading demodulation module are homogeneous
Even.Chip level equaliser is to the pretreated data of pre-processing module and HS-SCCH assisted channel estimation module channel estimation
As a result (H) is in Chip grades of progress equilibrium treatments, and the data after equilibrium treatment are exported to descrambling and de-spreading demodulation module.Chip grades
Balanced device and its equalization technic are existing well-known techniques, and details are not described herein.
Descrambling and de-spreading demodulation module is connected with Chip level equaliser, bit level processor.Descrambling and de-spreading demodulation module pair
Data removal scrambling code, spread spectrum after equilibrium treatment, and the soft bit demodulated is exported to bit level processor.Descrambling
Despread and demodulator is the device of existing maturation, ensure that the feasibility of embodiment of the present invention.
Bit level processor is connected with descrambling and de-spreading demodulation module, the second buffer storage, for demodulating to descrambling and de-spreading
The soft bit of module output is deinterleaved, solves rate-matched and decoding processing.Second buffer storage is for caching descrambling solution
Expand the soft bit of demodulation module output.
Present embodiment in terms of existing technologies, when carrying out HS-PDSCH reception processing, makes full use of
Correctly received HS-SCCH carries out assisted channel estimation, in this way, channel estimating performance can be promoted as Given information.
Second embodiment of the present invention is related to a kind of terminal reception device.Second embodiment is big with first embodiment
It causes identical, is in place of the main distinction: in the first embodiment, having made full use of correctly received HS-SCCH as
Know information, carries out assisted channel estimation, improve channel estimating performance.And in second embodiment of the invention, it makes full use of
Correctly received HS-SCCH carries out interference elimination as Given information, to HS-SCCH, improves HS-PDSCH acceptance
Energy.
It is specific as shown in figure 5, including antenna, pre-treatment mould specifically, the terminal reception device in present embodiment
Block, channel estimation module, HS-SCCH receiving module, HS-SCCH send signal recovery module, HS-SCCH interference cancellation module,
Chip level equaliser, descrambling and de-spreading demodulation module, bit level processor, the first buffer storage and the second buffer storage.
Wherein, antenna, pre-processing module, channel estimation module, HS-SCCH receiving module, HS-SCCH transmission signal are extensive
Multiple module, descrambling and de-spreading demodulation module, bit level processor, the first buffer storage, the second buffer storage are respectively with first
Antenna, pre-processing module, channel estimation module, HS-SCCH receiving module, HS-SCCH in embodiment send signal and restore
Module, descrambling and de-spreading demodulation module, bit level processor, the first buffer storage, the second buffer storage are identical, herein no longer
It repeats one by one.The difference with first embodiment is only introduced below:
In the present embodiment, HS-SCCH receiving module is combined after receiving to the HS-SCCH of each subframe
Decoding, and verified using cyclic redundancy check code (CRC).According to the processing capacity of current mainstream processor, HS-SCCH is connect
Receiving module reception decoding processing can complete within the time delay of a time slot.CRC is recycled to be verified after joint decoding,
It is more reliable to decode result.
First buffer storage caches the Chip grade data of 5 time slots, specifically as shown in fig. 6, in HS-SCCH 3N+6
At the end of time slot (dotted arrow position in figure), completes the HS-SCCH decoding of the N+1 subframe and sends signal and restore,
At this moment start the HS-PDSCH data receiver to n-th subframe, recovered HS-SCCH information can be made full use of in this way
(n-th subframe and the N+1 subframe) carries out interference elimination.
First buffer storage can be multiplexed with the second buffer storage.Same block storage is used specifically, referring to
It can be time-multiplexed, memory consumption can be saved in this way.
HS-SCCH interference cancellation module sends signal recovery module, channel estimation module, Chip grades with HS-SCCH respectively
Balanced device is connected.HS-SCCH interference cancellation module, which receives HS-SCCH and sends the HS-SCCH that signal recovery module is restored and send, to be believed
The first channel estimation results (H1) number with channel estimation module, and convolution is carried out by sending signal to H1 and HS-SCCH,
Restore HS-SCCH interference signal, then send the HS-SCCH interference signal for subtracting recovery in signal from HS-SCCH, can fill in this way
Divide using correctly received HS-SCCH as Given information, interference elimination is carried out to HS-SCCH, improves HS-PDSCH
Receptivity.
Chip level equaliser is connected with pre-processing module, HS-SCCH interference cancellation module.Chip level equaliser is to pre- place
The data after data and elimination interference after reason are in Chip grades of progress equilibrium treatments.
Third embodiment of the present invention is related to a kind of terminal reception device.Third embodiment is in first embodiment
On the basis of be further improved, mainly the improvement is that: in third embodiment of the invention, also having made full use of just
True received HS-SCCH carries out interference elimination to HS-SCCH, improves HS-PDSCH receptivity as Given information.
It is specific as shown in fig. 7, including antenna, pre-treatment mould specifically, the terminal reception device in present embodiment
Block, channel estimation module, HS-SCCH receiving module, HS-SCCH send signal recovery module, HS-SCCH assisted channel estimation mould
Block, HS-SCCH interference cancellation module, Chip level equaliser, descrambling and de-spreading demodulation module, bit level processor, the first buffering are deposited
Reservoir and the second buffer storage.
Wherein, antenna, pre-processing module, channel estimation module, HS-SCCH receiving module, HS-SCCH transmission signal are extensive
Multiple module, HS-SCCH assisted channel estimation module, descrambling and de-spreading demodulation module, bit level processor, the first buffer storage,
Second buffer storage is identical as in first embodiment respectively, in HS-SCCH interference cancellation module and second embodiment
It is identical, details are not described herein.It only introduces and first embodiment, the difference of second embodiment below:
Channel estimation module and pre-processing module, HS-SCCH receiving module, HS-SCCH assisted channel estimation module, HS-
SCCH interference cancellation module is connected；Chip level equaliser and pre-processing module, HS-SCCH assisted channel estimation module, HS-
SCCH interference cancellation module is connected.
Chip level equaliser is to the data after pretreated data, the result of channel estimation (H), elimination interference in Chip
Grade carries out equilibrium treatment.
Terminal reception device in present embodiment not only can be abundant when carrying out HS-PDSCH reception processing
Using correctly received HS-SCCH as Given information, assisted channel estimation is carried out, promotes channel estimating performance；May be used also
To carry out interference elimination to HS-SCCH, HS-PDSCH receptivity is improved.
Four embodiment of the invention is related to a kind of data receiver method, as shown in Figure 8 comprising the steps of:
Step 801, antenna receives data.Wherein, the received data of antenna can be rf data.
Step 802, the received data of antenna are converted to base band data by pre-processing module, and are located in advance to base band data
Reason.
Step 803, channel estimation module carries out channel estimation using CPICH Common Pilot Channel (CPICH), obtains the first channel
Estimated result (H1).
Step 804, the first buffer storage caches pretreated data.In this step, the first buffer storage is slow
Deposit the Chip grade data of 3 time slots.
Step 805, HS-SCCH receiving module receives pretreated data and H1, and decodes to received data
Obtain HS-SCCH information.In this step, HS-SCCH receiving module is independent to first time slot of each HS-SCCH subframe
Decoding.
Step 806, HS-SCCH sends signal recovery module and carries out coded modulation, spread spectrum, scrambling to HS-SCCH information, extensive
Multiple HS-SCCH sends signal.
Step 807, HS-SCCH assisted channel estimation module sends signal using HS-SCCH and carries out channel estimation as pilot tone, obtains
Take second channel estimated result H2.
Step 808, HS-SCCH assisted channel estimation module is weighted and averaged H1 and H2, the channel after obtaining weighting
Estimated result (H).Wherein, H and H1, H2 meet following relationship:
H=a*H1+ (1-a) * H2
Wherein, a is weighted factor；The value of a is
S is Transfer Parameters, and the value of s is
Wherein, SF1 And SF2 The respectively corresponding spreading factor of CPICH, HS-SCCH；P1 And P2 Respectively CPICH, HS-
The transmission power of SCCH.
Step 809, Chip level equaliser carries out the result (H) of pretreated data and channel estimation at Chip grades
Equilibrium treatment.
Step 810, descrambling and de-spreading demodulation module is to data removal scrambling code, the spread spectrum after equilibrium treatment, and demodulate
To soft bit.
Step 811, the second buffer storage caches the soft bit.
Step 812, bit level processor is deinterleaved the soft bit, solves rate-matched and decoding processing.
It is not difficult to find that present embodiment is embodiment of the method corresponding with first embodiment, present embodiment can be with
First embodiment is worked in coordination implementation.The relevant technical details mentioned in first embodiment still have in the present embodiment
Effect, in order to reduce repetition, which is not described herein again.Correspondingly, the relevant technical details mentioned in present embodiment are also applicable in
In first embodiment.
Fifth embodiment of the invention is related to a kind of data receiver method, and detailed process is as shown in Figure 9.5th embodiment
It is roughly the same with the 4th embodiment, it is in place of the main distinction: in the fourth embodiment, makes full use of correctly received
HS-SCCH as Given information, carry out assisted channel estimation, improve channel estimating performance.And implement in the present invention the 5th
It in mode, makes full use of correctly received HS-SCCH as Given information, interference elimination is carried out to HS-SCCH, is improved
HS-PDSCH receptivity.
Specifically, including step 901~912, wherein 901~903,905,910~912 in the present embodiment
Respectively in first embodiment step 801~803,805, it is 810~812 similar, details are not described herein.Below only to step
904, it 907~909 is introduced:
Step 904, the first buffer storage caches pretreated data.In this step, the first buffer storage is slow
Deposit the Chip grade data of 5 time slots.
Step 907, HS-SCCH interference cancellation module restores HS-SCCH interference signal.
Step 908, HS-SCCH interference cancellation module sends the HS-SCCH interference that recovery is subtracted in signal from HS-SCCH
Signal.
Step 909, Chip level equaliser carries out the data after pretreated data and elimination interference at Chip grades equal
Weighing apparatus processing.
Since second embodiment is corresponded to each other with present embodiment, present embodiment can be mutual with second embodiment
Match implementation.The relevant technical details mentioned in second embodiment are still effective in the present embodiment, implement second
The attainable technical effect of institute similarly may be implemented in the present embodiment in mode, no longer superfluous here in order to reduce repetition
It states.Correspondingly, the relevant technical details mentioned in present embodiment are also applicable in second embodiment.
Sixth embodiment of the invention is related to a kind of data receiver method, and detailed process is as shown in Figure 10.6th embodiment party
Formula is further improved on the basis of four embodiments, is mainly theed improvement is that: in sixth embodiment of the invention
In, it also makes full use of correctly received HS-SCCH as Given information, interference elimination is carried out to HS-SCCH, is improved
HS-PDSCH receptivity.
Specifically, including step 1001~1012, wherein step 1001~1006,1010 in the present embodiment
~1012 is identical as 801~806,810~812 difference in first embodiment respectively, and step 1007 is first embodiment
In step 807 and the step 907 in second embodiment merge, step 1008 is the step 808 in first embodiment
With merging for the step 908 in second embodiment, details are not described herein, and only step 1009 is slightly different:
Step 1009, Chip level equaliser is to pretreated data, the result of channel estimation (H) and after eliminating interference
Data are in Chip grades of progress equilibrium treatments.
Data receiver method in present embodiment not only can be abundant when carrying out HS-PDSCH reception processing
Using correctly received HS-SCCH as Given information, assisted channel estimation is carried out, promotes channel estimating performance；May be used also
To carry out interference elimination to HS-SCCH, HS-PDSCH receptivity is improved.
Since third embodiment is corresponded to each other with present embodiment, present embodiment can be mutual with third embodiment
Match implementation.The relevant technical details mentioned in third embodiment are still effective in the present embodiment, implement in third
The attainable technical effect of institute similarly may be implemented in the present embodiment in mode, no longer superfluous here in order to reduce repetition
It states.Correspondingly, the relevant technical details mentioned in present embodiment are also applicable in third embodiment.
The step of various methods divide above, be intended merely to describe it is clear, when realization can be merged into a step or
Certain steps are split, multiple steps are decomposed into, as long as comprising identical logical relation, all in the protection scope of this patent
It is interior；To adding inessential modification in algorithm or in process or introducing inessential design, but its algorithm is not changed
Core design with process is all in the protection scope of the patent.
It will be understood by those skilled in the art that the respective embodiments described above are to realize specific embodiments of the present invention,
And in practical applications, can to it, various changes can be made in the form and details, without departing from the spirit and scope of the present invention.
Claims (24)
1. a kind of terminal reception device is, characterized by comprising: antenna, pre-processing module, channel estimation module, high speed are shared
Control channel HS-SCCH receiving module and HS-SCCH send signal recovery module, also include HS-SCCH assisted channel estimation mould
Block and/or HS-SCCH interference cancellation module；
Antenna is connected with pre-processing module, and pre-processing module is connected with channel estimation module, HS-SCCH receiving module, HS-
SCCH receiving module is connected with channel estimation module；HS-SCCH sends signal recovery module and is connected with HS-SCCH receiving module,
HS-SCCH assisted channel estimation module sends signal recovery module with HS-SCCH respectively, channel estimation module is connected, HS-SCCH
Interference cancellation module sends signal recovery module with HS-SCCH respectively, channel estimation module is connected；
The antenna, for receiving data；
The pre-processing module for being converted to base band data to the received data of antenna, and carries out the base band data pre-
Processing；
The channel estimation module obtains the first channel estimation knot for carrying out channel estimation using CPICH Common Pilot Channel CPICH
Fruit H1；
The HS-SCCH receiving module is decoded for receiving pretreated data and the H1, and to received data
Obtain HS-SCCH information；
The HS-SCCH sends signal recovery module, for carrying out coded modulation, spread spectrum, scrambling to the HS-SCCH information,
Restore HS-SCCH and sends signal；
The HS-SCCH assisted channel estimation module carries out channel estimation as pilot tone for sending signal using the HS-SCCH,
Second channel estimated result H2 is obtained, and the H1 and the H2 are weighted and averaged, the channel estimation knot after obtaining weighting
Fruit H；
The HS-SCCH interference cancellation module for restoring HS-SCCH interference signal, and sends in signal from HS-SCCH and subtracts
The HS-SCCH interference signal of recovery.
2. terminal reception device according to claim 1, which is characterized in that the H and H1, H2 meet following relationship:
H=a*H1+ (1-a) * H2
Wherein, a is weighted factor；The value of a is
Wherein, s is Transfer Parameters, and the value of s is
Wherein, SF1 And SF2 The respectively described CPICH, the corresponding spreading factor of the HS-SCCH；P1 And P2 It is respectively described
The transmission power of CPICH, the HS-SCCH.
3. terminal reception device according to claim 1, which is characterized in that the HS-SCCH interference cancellation module passes through
Signal is sent to the H1 and HS-SCCH and carries out convolution, restores HS-SCCH interference signal.
4. terminal reception device according to claim 1, which is characterized in that the HS-SCCH receiving module, to each
First time slot of HS-SCCH subframe individually decodes.
5. terminal reception device according to claim 1, which is characterized in that the HS-SCCH receiving module, to every height
The HS-SCCH of frame carries out joint decoding after receiving, and is verified using cyclic redundancy check code CRC.
6. terminal reception device according to claim 1, which is characterized in that also include the first buffer storage；
First buffer storage is connected with the HS-SCCH receiving module, for caching the pretreated data.
7. terminal reception device according to claim 6, which is characterized in that first buffer storage, when caching 3
The Chip grade data of gap.
8. terminal reception device according to claim 6, which is characterized in that first buffer storage, when caching 5
The Chip grade data of gap.
9. terminal reception device according to claim 1, which is characterized in that also include Chip level equaliser；
The Chip level equaliser is connected with the pre-processing module, the HS-SCCH assisted channel estimation module, for pair
The result H of pretreated data and channel estimation is in Chip grades of progress equilibrium treatments；And/or
The Chip level equaliser is connected with the pre-processing module, HS-SCCH interference cancellation module；
The Chip level equaliser, for pretreated data with eliminate the data after interference at the balanced place of Chip grades of progress
Reason.
10. terminal reception device according to claim 9, which is characterized in that also include descrambling and de-spreading demodulation module；
The descrambling and de-spreading demodulation module is connected with the Chip level equaliser, for disturbing to the data removal after equilibrium treatment
Code, spread spectrum, and demodulated to obtain soft bit.
11. terminal reception device according to claim 10, which is characterized in that also include bit level processor；
The bit level processor is connected with the descrambling and de-spreading demodulation module, for being deinterleaved, solving to the soft bit
Rate-matched and decoding are handled.
12. terminal reception device according to claim 11, which is characterized in that also include the second buffer storage；
Second buffer storage, is connected with the bit level processor, for caching the soft bit.
13. a kind of data receiver method, which is characterized in that comprise the steps of:
The received data of antenna are converted to base band data by pre-processing module, and are pre-processed to the base band data；
Channel estimation module carries out channel estimation using CPICH Common Pilot Channel CPICH, obtains the first channel estimation results H1；
HS-SCCH receiving module receives pretreated data and the H1, and carries out decoding to received data and obtain HS-
SCCH information；
HS-SCCH sends signal recovery module and carries out coded modulation, spread spectrum, scrambling to the HS-SCCH information, restores HS-
SCCH sends signal；
Signal recovery module is sent in the HS-SCCH, coded modulation, spread spectrum, scrambling are carried out to the HS-SCCH information, restore
After HS-SCCH sends signals step, also include:
HS-SCCH assisted channel estimation module sends signal using the HS-SCCH and carries out channel estimation as pilot tone, obtains the second letter
Road estimated result H2, and the H1 and the H2 are weighted and averaged, the channel estimation results H after obtaining weighting；And/or
HS-SCCH interference cancellation module restores HS-SCCH interference signal, and the HS- that recovery is subtracted in signal is sent from HS-SCCH
SCCH interference signal.
14. data receiver method according to claim 13, which is characterized in that the H and H1, H2 meet following relationship:
H=a*H1+ (1-a) * H2
Wherein, a is weighted factor；The value of a is
S is Transfer Parameters, and the value of s is
Wherein, SF1 And SF2 The respectively described CPICH, the corresponding spreading factor of the HS-SCCH；P1 And P2 It is respectively described
The transmission power of CPICH, the HS-SCCH.
15. data receiver method according to claim 13, which is characterized in that in the HS-SCCH interference cancellation module
In the step of restoring HS-SCCH interference signal,
The HS-SCCH interference cancellation module carries out convolution by sending signal to the H1 and HS-SCCH, restores HS-
SCCH interference signal.
16. data receiver method according to claim 13, which is characterized in that received in the HS-SCCH receiving module
Pretreated data, and received data are carried out in the step of decoding obtains HS-SCCH information,
The HS-SCCH receiving module individually decodes first time slot of each HS-SCCH subframe.
17. data receiver method according to claim 13, which is characterized in that received in the HS-SCCH receiving module
Pretreated data, and received data are carried out in the step of decoding obtains HS-SCCH information,
The HS-SCCH receiving module carries out joint decoding after receiving to the HS-SCCH of each subframe, and utilizes circulation
Redundancy check code CRC is verified.
18. data receiver method according to claim 13, which is characterized in that received in the HS-SCCH receiving module
Pretreated data, and before the step of carrying out decoding acquisition HS-SCCH information to received data, it also include following step
It is rapid:
First buffer storage caches the pretreated data.
19. data receiver method according to claim 18, which is characterized in that cache institute in first buffer storage
In the step of stating pretreated data,
First buffer storage caches the Chip grade data of 3 time slots.
20. data receiver method according to claim 18, which is characterized in that cache institute in first buffer storage
In the step of stating HS-SCCH information,
First buffer storage caches the Chip grade data of 5 time slots.
21. data receiver method according to claim 13, which is characterized in that carried out described to the H1 and H2
After the step of being weighted and averaged, obtaining the channel estimation results H after weighting, also comprise the steps of:
Chip level equaliser is to the result H of pretreated data and channel estimation in Chip grades of progress equilibrium treatments；And/or
It also include following step described after the step of subtracting the HS-SCCH interference signal of recovery in HS-SCCH transmission signal
It is rapid:
The Chip level equaliser is to pretreated data and eliminates the data after interference in Chip grades of progress equilibrium treatments.
22. data receiver method according to claim 21, which is characterized in that in the Chip level equaliser to pretreatment
After the result of data and channel estimation afterwards is the Chip grades of progress equilibrium treatments the step of, and/or it is balanced at described Chip grades
Device also includes following to pretreated data and after eliminating the data after interference the Chip grade progress equilibrium treatments the step of
Step:
Descrambling and de-spreading demodulation module is demodulated to obtain soft bit to data removal scrambling code, the spread spectrum after equilibrium treatment.
23. data receiver method according to claim 22, which is characterized in that in the descrambling and de-spreading demodulation module to equal
Weighing apparatus treated data removal scrambling code, spread spectrum, and after being demodulated the step of obtaining soft bit, also comprise the steps of:
Bit level processor is deinterleaved the soft bit, solves rate-matched and decoding processing.
24. data receiver method according to claim 23, which is characterized in that in the bit level processor to described soft
Before bit is deinterleaved, solves the step of rate-matched and decoding processing, also comprise the steps of:
Second buffer storage caches the soft bit.
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