CN105720097A - Enhanced-mode high electron mobility transistor, preparation method thereof, and semiconductor device - Google Patents
Enhanced-mode high electron mobility transistor, preparation method thereof, and semiconductor device Download PDFInfo
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- CN105720097A CN105720097A CN201610274590.6A CN201610274590A CN105720097A CN 105720097 A CN105720097 A CN 105720097A CN 201610274590 A CN201610274590 A CN 201610274590A CN 105720097 A CN105720097 A CN 105720097A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 230000004888 barrier function Effects 0.000 claims abstract description 46
- 238000000407 epitaxy Methods 0.000 claims abstract description 28
- 238000002161 passivation Methods 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 17
- 229910002704 AlGaN Inorganic materials 0.000 claims description 11
- 230000012010 growth Effects 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 9
- 229910004205 SiNX Inorganic materials 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- -1 InAlN Inorganic materials 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052593 corundum Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 3
- 230000034655 secondary growth Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 2
- 229920006395 saturated elastomer Polymers 0.000 abstract 1
- 238000009616 inductively coupled plasma Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- 229910015844 BCl3 Inorganic materials 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000001883 metal evaporation Methods 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000007773 growth pattern Effects 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000007726 management method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The present invention provides an enhanced-mode high electron mobility transistor. The transistor includes a grid electrode, a source electrode, a drain electrode, a p type layer, a barrier layer, and a passivation layer arranged on the barrier layer. A part region on the passivation layer is provided with a secondary epitaxy figure formed by etching to the upper surface of the barrier layer. The barrier layer also includes a trench formed by further etching to the inner side of the barrier layer in a local region of the figure. The p type layer that is grown through secondary epitaxy is in the figure and the trench. The p type layer in the trench is contacted with a grid electrode metal on the p type layer in the trench. The p type layer that is not in the trench is contacted with a drain electrode metal on the p type layer that is not in the trench. The present invention also provides a preparation method of the transistor and a semiconductor device including the transistor. According to the transistor, due to a trench grid and the p type layer grown through secondary epitaxy in a selected region, a threshold voltage of the device is increased; and a part of the barrier layer is etched, so that a saturated current of the device is greater than the current of the trench grid type high electron mobility transistor (HEMT). In addition, the p type layer is also grown in a selected region of the drain electrode metal, so that the turn-off effect of the device is improved.
Description
Technical field
The invention belongs to technical field of semiconductors, particularly relate to a kind of enhancement type high electron mobility transistor and preparation method thereof, and comprise the semiconductor device of this transistor.
Background technology
GaN base power electronic devices had attracted the attention of many people in the last few years.GaN material can form heterojunction structure with the material such as AlGaN, InAlN.Owing to abarrier layer material exists piezoelectricity and spontaneous polarization effect, the two-dimensional electron gas (2DEG) of high concentration therefore can be formed at heterojunction boundary place.
The features such as GaN base HEMT (HEMT) device is high due to its saturation current, and breakdown voltage is high, switching speed is fast, have a wide range of applications in field of power electronics such as electric automobile, wind-power electricity generation, power managements.YoleDevelopment company is it is expected that the optimum voltage range of GaN device is 0～900V, and capacity is estimated to account for 2/3rds of power device market.GaN base HEMT device, due to the polarization characteristic of material self, also exists the two-dimensional electron gas of high concentration at heterojunction boundary place so that device is in the conduction state under zero grid voltage, i.e. depletion device, and its design of drive circuit is more complicated, adds energy loss.For simplifying the design of depletion type HEMT driving circuit structure, reducing energy loss and improve device security, enhancement mode HEMT becomes the emphasis of all circles' research.Wherein, groove grid and p-type cap layer structure realize enhancement mode HEMT is mainstream technology route.But, groove grid HEMT gate lower barrierlayer very thin thickness or be etched away completely, greatly reduce the saturation current of device, and need accurately to control etching technics to realize enhancement mode, threshold voltage is generally relatively low.The HEMT of current p-type layer structure adopts first full wafer epitaxial p-type layer substantially, then performs etching and retain the method for grid lower p-type layer to realize enhancement mode.But owing to etching technics damages, element leakage will increase, and reduce the breakdown voltage of device.
Summary of the invention
Based on the problems referred to above, it is an object of the invention to, enhancement type high electron mobility transistor and preparation method, semiconductor device.
For achieving the above object, according to an aspect of the present invention, it is provided that a kind of enhancement type high electron mobility transistor, including grid, source electrode, drain electrode, p-type layer, barrier layer and the passivation layer that is arranged on barrier layer, wherein:
Subregion on described passivation layer is provided with and is etched to the secondary epitaxy figure that barrier layer upper surface is formed；
Described barrier layer is additionally included in the regional area of described figure and etches the groove of formation further in barrier layer；
The p-type layer that secondary epitaxy grows is had in described figure and groove, wherein, the p-type layer in groove and the gate metal contact being positioned above, p-type layer in non-recessed and the drain metal contacts being positioned above and between grid, drain electrode.
A specific embodiments according to the present invention, the described recess etch degree of depth is 3nm-48nm, and less than barrier layer thickness.
A specific embodiments according to the present invention, described barrier layer is AlGaN, InAlN, AlN, InN or InGaN, and thickness is 5nm-50nm.
A specific embodiments according to the present invention, described p-type layer is the p-InGaN of p-GaN, p-InGaN, p-AlGaN, the p-AlGaN of content gradually variational or content gradually variational, and p-type layer doping content is 1016-1022cm-3, thickness is 2nm-500nm.
A specific embodiments according to the present invention, passivation layer is Al2O3、SiO2、HfO2、HfTiO、ZrO2、SiNx, SiNO or MgO, thickness is 10nm-1 μm.
According to an aspect of the present invention, it is provided that the preparation method of a kind of enhancement type high electron mobility transistor, comprise the following steps:
S1: prepare epitaxial layer on substrate, including preparing barrier layer；
S2: deposit passivation layer on described barrier layer；
S3: preparation constituency secondary epitaxy figure；
S4: at the regional area of constituency secondary epitaxy figure, from barrier layer, downward etching prepares groove；
S5: grow p-type layer on secondary epitaxy graphics field, constituency and groove；
S6: preparation source, drain electrode, wherein drain metal contacts with the p-type layer of growth in non-recessed；
S7: gate electrode is prepared on the p-type layer surface grown in a groove.
A specific embodiments according to the present invention, described p-type layer is prepared by the method grown by constituency secondary epitaxy, and the p-type layer under grid and drain metal is that same secondary growth obtains.
A specific embodiments according to the present invention, described p-type layer doping content is 1 × 1016-1×1022cm-3, thickness is 2nm-500nm.
According to an aspect of the present invention, it is provided that a kind of semiconductor device, including one described enhancement type high electron mobility transistor of any of the above.
(3) beneficial effect
By technique scheme, the beneficial effects of the present invention is:
(1) by arranging groove on barrier layer, grid lower barrierlayer only has fraction to be etched so that 2DEG concentration lowers, and reduces the requirement of high hole concentration during the secondary epitaxy p-type layer of constituency, is easier to realize enhancement mode.Compared to groove gate type HEMT, owing to being partial etching barrier layer, device saturation current can increase；
(2) by arranging groove and the threshold voltage of constituency secondary epitaxy growth p-type layer raising device, etch, after reducing full sheet growth p-type layer, the barrier layer surface damage that Shan Yuan grid leak district p-type layer is brought again, reduce HEMT device electric leakage, be conducive to improving device electric breakdown strength；
(3) by drain metal region also constituency secondary epitaxy growth p-type layer, wherein p-type layer is between grid and drain electrode and upper surface and drain metal contacts, when drain voltage increases, forward is opened by the pn-junction that p-type layer and barrier layer are formed, and does not affect the conducting of raceway groove.When device off state, owing to hole is to the diffusion of raceway groove, raceway groove 2DEG is had depletion action, increase channel resistance, reduce OFF leakage current, improve device electric breakdown strength further.
Accompanying drawing explanation
Fig. 1 is the structure chart of the enhancement type high electron mobility transistor of the present invention one specific embodiment.
Fig. 2 is the structure flow chart of the enhancement type high electron mobility transistor manufacture method of the present invention one specific embodiment.
Fig. 3 is SEM (scanning electron microscope) sectional view of the enhancement type high electron mobility transistor p-GaN of the present invention one specific embodiment.
Detailed description of the invention
In the present invention, represent each layer position relationship " on " and D score term refer on destination layer, be provided with other layer, contact or noncontact between this destination layer with other layer.It should be noted that " on ", D score relative to reference frame, whether be inverted unrelated with semiconductor device entirety.
According to present invention inventive concept generally, it is provided that a kind of enhancement type high electron mobility transistor, including grid, source electrode, drain electrode, p-type layer, barrier layer and the passivation layer that is arranged on barrier layer, wherein:
Subregion on described passivation layer is provided with and is etched to the constituency secondary epitaxy figure that barrier layer upper surface is formed；
Described barrier layer is additionally included in the regional area of described figure and etches the groove of formation further in barrier layer；
The p-type layer of constituency secondary epitaxy growth is had in described figure and groove, wherein, the p-type layer in groove and the gate metal contact being positioned above, p-type layer in non-recessed and the drain metal contacts being positioned above and between grid, drain electrode.
The degree of depth for groove, it is preferred that the recess etch degree of depth is 3nm-48nm, and less than barrier layer thickness.
For the selection of barrier layer, described barrier layer is AlGaN, InAlN, AlN, InN or InGaN, and thickness is 5nm-50nm.
For the selection of p-type layer, p-type layer is the p-InGaN of p-GaN, p-InGaN, p-AlGaN, the p-AlGaN of content gradually variational or content gradually variational, and p-type layer maximum dopant concentration is 1016-1022cm-3, thickness is 2nm-500nm, it is preferred that p-type layer thickness is less than passivation layer thickness.
For the selection of passivation layer, passivation layer is Al2O3、SiO2、HfO2、HfTiO、ZrO2、SiNx, SiNO or MgO, thickness is 10nm-1 μm.
Selection for substrate, it is possible to be the substrate being commonly used in and preparing transistor, it is preferred that backing material is Si, sapphire, SiC or GaN.
For other epitaxial layer on transistor, also include cushion and GaN channel layer,
The material of described cushion is low temperature AI N or low temperature GaN, thickness 1nm-500nm；Described GaN channel layer thickness is 50nm-10 μm.
For drain electrode or source electrode, it is preferred that metal system is Ti/Al/Ti/Au, it is preferred that Ti in system, each layer of Al, Ti and Au thickness be 20nm, 40nm, 50nm and 70nm.
For grid, it is preferred that metal system is Ni/Au, it is preferred that in system, each layer thickness of Ni and Au is 5 and 30nm.
Based on same inventive concept, the preparation method that the present invention provides a kind of enhancement type high electron mobility transistor, comprise the following steps:
S1: prepare epitaxial layer on substrate, including preparing barrier layer；
S2: deposit passivation layer on described barrier layer；
S3: preparation constituency secondary epitaxy mask；
S4: at the regional area of constituency secondary epitaxy mask, from barrier layer, downward etching prepares groove；
S5: grow p-type layer on secondary epitaxy mask regions, constituency and groove；
S6: prepare source electrode, drain electrode, wherein drain electrode contacts with the p-type layer metal of growth in non-recessed；
S7: gate electrode is prepared on the p-type layer surface grown in a groove.
Preferably, described p-type layer doping content 1 × 1016-1×1022cm-3, it is preferred that thickness is 2nm-500nm.
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in further detail.Following it is intended to the explanation of embodiment of the present invention with reference to accompanying drawing the present general inventive concept of the present invention is made an explanation, and is not construed as a kind of restriction to the present invention.
Referring to Fig. 2, the present invention provides the structure and preparation method that constituency secondary epitaxy realizes enhancement mode HEMT, comprises the steps:
Step S1: in substrate Epitaxial growth GaN base HEMT-structure, is followed successively by substrate (1), cushion (2), GaN channel layer (3), barrier layer (4) from substrate side；Described substrate (1) can be Si, sapphire, SiC or GaN, and cushion (2) can be low temperature AI N or low temperature GaN, and thickness 50nm, GaN channel layer (3) thickness is 3 μm, and barrier layer (4) is Al0.25Ga0.75N, thickness 30nm.Described epitaxy method can be MOCVD.
Step S2: by LPCVD method deposit passivation layer (5) SiNx, thickness is 300nm；
Step S3: the mask pattern of preparation constituency secondary epitaxy, available wet etching or dry etching, as inductively coupled plasma (ICP) etches, by the grid of unglazed photoresist mask covering and drain region passivation layer (5) SiNxAll etching is clean.
Step S4: prepare groove on barrier layer.Barrier layer (4) can be performed etching, perform etching with ICP, etch thicknesses 15nm.By reduce ICP etching time power and etching gas Ar, Cl2、BCl3Flow reduce etching injury under grid.It can be 450/10W for AC power/dc power that the ICP adopted etches power, Ar, Cl2、BCl3Flow is 10sccm, 5sccm, 5sccm respectively.
Step S5: constituency secondary epitaxy growth p-type layer (6) p-GaN, growth pattern can be selected for MOCVD, p-GaN thickness 120-200nm, selects Mg as adulterant, doping content 1 × 1019cm-3.Constituency secondary epitaxy growth time can be controlled so that pGaN thickness is less than passivation layer (5) thickness.
Step S6: mesa-isolated.Available ICP performs etching, and is sequentially etched passivation layer SiNx(5), AlGaN potential barrier (4), GaN channel layer (3).
Step S7: to source-drain regions passivation layer (5) SiNxCarry out ICP etching, etch into barrier layer (4) upper surface.
Step S8: prepare source-drain electrode.Electron beam evaporation (EB) can be adopted to carry out source-drain electrode metal evaporation, and evaporation metal system is Ti/Al/Ti/Au (20/40/50/70nm), then carries out peeling off and rapid thermal annealing formation Ohmic contact.Annealing conditions can be: N2Atmosphere, 850 DEG C, 30s.
Step S9: prepare gate electrode.Electron beam evaporation (EB) can be adopted to carry out gate metal evaporation, and evaporation metal system is Ni/Au (5/30nm), then peels off.Prepare the schematic diagram of product as it is shown in figure 1, the SEM of p-GaN schemes as shown in Figure 3.
Particular embodiments described above; the purpose of the present invention, technical scheme and beneficial effect have been further described; it it should be understood that; the foregoing is only specific embodiments of the invention; it is not limited to the present invention; all within the spirit and principles in the present invention, any amendment of making, equivalent replacement, improvement etc., should be included within protection scope of the present invention.
Claims (9)
1. an enhancement type high electron mobility transistor, including grid, source electrode, drain electrode, p-type layer, barrier layer and the passivation layer that is arranged on barrier layer, it is characterised in that:
Subregion on described passivation layer is provided with and is etched to the constituency secondary epitaxy figure that barrier layer upper surface is formed；
Described barrier layer is additionally included in the regional area of described figure and etches the groove of formation further in barrier layer；
The p-type layer that secondary epitaxy grows is had in described figure and groove, wherein, the p-type layer in groove and the gate metal contact being positioned above, p-type layer in non-recessed and the drain metal contacts being positioned above and between grid, drain electrode.
2. enhancement type high electron mobility transistor according to claim 1, it is characterised in that the described recess etch degree of depth is 3nm-48nm, and less than barrier layer thickness.
3. enhancement type high electron mobility transistor according to claim 1, it is characterised in that described barrier layer is AlGaN, InAlN, AlN, InN or InGaN, thickness is 5nm-50nm.
4. enhancement type high electron mobility transistor according to claim 1, it is characterised in that described p-type layer is the p-InGaN of p-GaN, p-InGaN, p-AlGaN, the p-AlGaN of content gradually variational or content gradually variational, and p-type layer doping content is 1016-1022cm-3, thickness is 2nm-500nm.
5. enhancement type high electron mobility transistor according to claim 1, it is characterised in that passivation layer is Al2O3、SiO2、HfO2、HfTiO、ZrO2、SiNx, SiNO or MgO, thickness is 10nm-1 μm.
6. the preparation method of an enhancement type high electron mobility transistor, it is characterised in that comprise the following steps:
S1: prepare epitaxial layer on substrate, including preparing barrier layer；
S2: deposit passivation layer on described barrier layer；
S3: preparation constituency secondary epitaxy figure；
S4: at the regional area of constituency secondary epitaxy figure, from barrier layer, downward etching prepares groove；
S5: grow p-type layer on secondary epitaxy graphics field, constituency and groove；
S6: preparation source, drain electrode, wherein drain metal contacts with the p-type layer of growth in non-recessed；
S7: gate electrode is prepared on the p-type layer surface grown in a groove.
7. preparation method according to claim 6, it is characterised in that described p-type layer is prepared by the method grown by constituency secondary epitaxy, and the p-type layer under grid and drain metal is that same secondary growth obtains.
8. preparation method according to claim 7, it is characterised in that described p-type layer doping content is 1 × 1016-1×1022cm-3, thickness is 2nm-500nm.
9. a semiconductor device, including the enhancement type high electron mobility transistor described in claim 1-5 any one.
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